From: lkcl <lkcl@web>
Date: Fri, 7 May 2021 11:22:02 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~967
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc3c9e9b5f5ed744da7d5172596352cfad72ec62;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index c26a646b7..39cb7ff24 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -208,6 +208,13 @@ src and dest predicate mask is "All 1s".
 Bear in mind that srcstep+deststep are a form of back-to-back
 VGATHER+VSCATTER
 
+Watch out in zeroing! CR0 will *not* be set (itself) to zero:
+the CR0.eq flag will be set because the *result* is still tested.
+correction: CR0-and-any-other-Vector-of-CR-fields (Vector elements
+have their corresponding CR field, so the test of zero needs to
+be done for the associated *element* result, not jam absolutely
+every element vector test *into* CR0)
+
 Progress:
 
 * TestIssuer <https://bugs.libre-soc.org/show_bug.cgi?id=617>