From: whitequark <cz@m-labs.hk>
Date: Mon, 18 Nov 2019 10:39:55 +0000 (+0000)
Subject: back.rtlil: extend shorter operand of a binop when matching sign.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc6483f43788229cd7ea6952a425b92e2a0e21c6;p=nmigen.git

back.rtlil: extend shorter operand of a binop when matching sign.

This is necessary because converting a large unsigned value to
a signed value of the same width may change its sign.

Fixes #271.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 5cd9f97..7806ace 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -490,6 +490,7 @@ class _RHSValueCompiler(_ValueCompiler):
             rhs_wire = self(rhs)
         else:
             lhs_sign = rhs_sign = True
+            lhs_bits = rhs_bits = max(lhs_bits, rhs_bits)
             lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
             rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
         res_bits, res_sign = value.shape()