From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 10 Nov 2006 09:14:25 +0000 (-0500)
Subject: Set the ASI register to be something explicitly so that simulation is deterministic.
X-Git-Tag: m5_2.0_beta2~66^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc6af9fbf7bbbe29e431190867a2fed6fdcce8b5;p=gem5.git

Set the ASI register to be something explicitly so that simulation is deterministic.

--HG--
extra : convert_revision : 38cd06f946fc0cc22288f71f567e77ce8fdfea99
---

diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index a3b7dde7c..11a799ccb 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -29,6 +29,7 @@
  *          Ali Saidi
  */
 
+#include "arch/sparc/asi.hh"
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/process.hh"
 #include "base/loader/object_file.hh"
@@ -105,6 +106,8 @@ SparcLiveProcess::startup()
     threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
     //Set the trap level to 0
     threadContexts[0]->setMiscReg(MISCREG_TL, 0);
+    //Set the ASI register to something fixed
+    threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
 }
 
 m5_auxv_t buildAuxVect(int64_t type, int64_t val)