From: Paul Mackerras <paulus@ozlabs.org>
Date: Wed, 22 Apr 2020 03:54:38 +0000 (+1000)
Subject: execute1: Don't execute ld/st instruction when taking interrupt
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc6b1df653a860bf704aebc515da87e89cc34512;p=microwatt.git

execute1: Don't execute ld/st instruction when taking interrupt

This fixes a bug in the logic where we would still send a load
or store instruction to loadstore1 even though we have decided
to take an asynchronous interrupt.

Reported-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---

diff --git a/execute1.vhdl b/execute1.vhdl
index 6915a43..2c0a558 100644
--- a/execute1.vhdl
+++ b/execute1.vhdl
@@ -248,6 +248,7 @@ begin
 
 	v := r;
 	v.e := Execute1ToWritebackInit;
+        lv := Execute1ToLoadstore1Init;
 
 	-- XER forwarding. To avoid having to track XER hazards, we
 	-- use the previously latched value.
@@ -773,6 +774,7 @@ begin
             when OP_LOAD | OP_STORE =>
                 -- loadstore/dcache has its own port to writeback
                 v.e.valid := '0';
+                lv.valid := '1';
 
             when others =>
 		terminate_out <= '1';
@@ -865,10 +867,6 @@ begin
 	v.e.write_enable := result_en;
 
         -- Outputs to loadstore1 (async)
-        lv := Execute1ToLoadstore1Init;
-        if e_in.valid = '1' and (e_in.insn_type = OP_LOAD or e_in.insn_type = OP_STORE) then
-            lv.valid := '1';
-        end if;
         if e_in.insn_type = OP_LOAD then
             lv.load := '1';
         end if;