From: Giacomo Travaglini Date: Fri, 6 Sep 2019 13:44:47 +0000 (+0100) Subject: arch-arm: ISV bit in DataAbort should check for translation stage X-Git-Tag: v19.0.0.0~540 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc70987e470d66f584e0ddf606e9f07da994ba75;p=gem5.git arch-arm: ISV bit in DataAbort should check for translation stage According to the ESR spec, the ISV bit is set to 1 only for stage 2 aborts. Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980 Maintainer: Andreas Sandberg Tested-by: kokoro --- diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index ba5151944..c5858c9ae 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1371,7 +1371,7 @@ DataAbort::iss() const val = AbortFault::iss(); // ISS is valid if not caused by a stage 1 page table walk, and when taken // to AArch64 only when directed to EL2 - if (!s1ptw && (!to64 || toEL == EL2)) { + if (!s1ptw && stage2 && (!to64 || toEL == EL2)) { val |= isv << 24; if (isv) { val |= sas << 22;