From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 24 Aug 2019 22:05:44 +0000 (-0700)
Subject: Wire with init on FF part, 1'bx on non-FF part
X-Git-Tag: working-ls180~1095^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc87372a97d515563ccccd517ef8f35662870fe6;p=yosys.git

Wire with init on FF part, 1'bx on non-FF part
---

diff --git a/tests/sat/initval.v b/tests/sat/initval.v
index fcec9dd8c..81f71b5ba 100644
--- a/tests/sat/initval.v
+++ b/tests/sat/initval.v
@@ -1,4 +1,4 @@
-module test(input clk, input [3:0] bar, output [3:0] foo);
+module test(input clk, input [3:0] bar, output [3:0] foo, asdf);
   reg [3:0] foo = 0;
   reg [3:0] last_bar = 0;
   reg [3:0] asdf = 4'b1xxx;
@@ -12,6 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
   always @(posedge clk)
     last_bar <= bar;
 
+  always @(posedge clk)
+    asdf[3] <= bar[3];
   always @*
     asdf[2:0] = 3'b111;