From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Fri, 8 Oct 2021 12:51:57 +0000 (+0200)
Subject: Fix a regression from #3035.
X-Git-Tag: yosys-0.11~50
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc8da76282e806e7ffd632af3e6c11d645ff5699;p=yosys.git

Fix a regression from #3035.
---

diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc
index 4ca5bcbb4..c65108413 100644
--- a/kernel/ffmerge.cc
+++ b/kernel/ffmerge.cc
@@ -157,7 +157,7 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pai
 }
 
 bool FfMergeHelper::find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits) {
-	ff = FfData();
+	ff = FfData(module, initvals, NEW_ID);
 	sigmap->apply(sig);
 
 	bool found = false;
diff --git a/tests/memories/trans_addr_enable.v b/tests/memories/trans_addr_enable.v
new file mode 100644
index 000000000..f366f41ad
--- /dev/null
+++ b/tests/memories/trans_addr_enable.v
@@ -0,0 +1,21 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+
+module top(input clk, we, rae, input [7:0] addr, wd, output [7:0] rd);
+
+reg [7:0] mem[0:255];
+
+reg [7:0] rra;
+
+always @(posedge clk) begin
+	if (we)
+		mem[addr] <= wd;
+
+	if (rae)
+		rra <= addr;
+end
+
+assign rd = mem[rra];
+
+endmodule