From: Luke Kenneth Casson Leighton Date: Wed, 27 May 2020 14:35:09 +0000 (+0100) Subject: add links to bugreports into ALu formal proof as well X-Git-Tag: div_pipeline~793 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc96e9ce372a68ced5d598eb198704b2f36ed5d0;p=soc.git add links to bugreports into ALu formal proof as well --- diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py index 5b871f5a..a6ce3802 100644 --- a/src/soc/fu/alu/formal/proof_main_stage.py +++ b/src/soc/fu/alu/formal/proof_main_stage.py @@ -1,5 +1,11 @@ -# Proof of correctness for partitioned equal signal combiner +# Proof of correctness for ALU pipeline, main stage # Copyright (C) 2020 Michael Nolan +""" +Links: +* https://bugs.libre-soc.org/show_bug.cgi?id=306 +* https://bugs.libre-soc.org/show_bug.cgi?id=305 +* https://bugs.libre-soc.org/show_bug.cgi?id=343 +""" from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl, signed) diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py index 4d02df67..d76a5e27 100644 --- a/src/soc/fu/alu/formal/proof_output_stage.py +++ b/src/soc/fu/alu/formal/proof_output_stage.py @@ -1,4 +1,4 @@ -# Proof of correctness for partitioned equal signal combiner, output stage +# Proof of correctness for ALU pipeline, output stage # Copyright (C) 2020 Michael Nolan """ Links: