From: Xiang, Haihao <haihao.xiang@intel.com>
Date: Fri, 24 Dec 2010 01:34:50 +0000 (+0800)
Subject: i965: use align1 access mode for instructions with execSize=1 in VS
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc987adc9f5f9f851be124985fa6bbcdbfa4a7a5;p=mesa.git

i965: use align1 access mode for instructions with execSize=1 in VS

All operands must be 16-bytes aligned in aligh16 mode. This fixes l_xxx.c
in oglconform.
---

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index f8a3044dd0a..88131c432ec 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1727,6 +1727,7 @@ void brw_dp_READ_4_vs(struct brw_compile *p,
 
    /* Setup MRF[1] with location/offset into const buffer */
    brw_push_insn_state(p);
+   brw_set_access_mode(p, BRW_ALIGN_1);
    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
    brw_set_mask_control(p, BRW_MASK_DISABLE);
    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
@@ -1774,6 +1775,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
 
    /* Setup MRF[1] with offset into const buffer */
    brw_push_insn_state(p);
+   brw_set_access_mode(p, BRW_ALIGN_1);
    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
    brw_set_mask_control(p, BRW_MASK_DISABLE);
    brw_set_predicate_control(p, BRW_PREDICATE_NONE);