From: Joern Rennecke <joern.rennecke@embecosm.com>
Date: Tue, 18 Jun 2002 15:54:44 +0000 (+0000)
Subject: 	* interp.c (sim_resume): Fix setting of bus error for
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dc9feb5c97ab95cb328406040f47f20f986f0e58;p=binutils-gdb.git

	* interp.c (sim_resume): Fix setting of bus error for
	instruction fetch.
---

diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog
index a18645f683b..d8a8f70ef43 100644
--- a/sim/sh/ChangeLog
+++ b/sim/sh/ChangeLog
@@ -1,3 +1,8 @@
+Tue Jun 18 16:53:11 2002  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* interp.c (sim_resume): Fix setting of bus error for
+	instruction fetch.
+
 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 
 	* configure: Regenerated to track ../common/aclocal.m4 changes.
diff --git a/sim/sh/interp.c b/sim/sh/interp.c
index 286dd2dccba..6abff0050a2 100644
--- a/sim/sh/interp.c
+++ b/sim/sh/interp.c
@@ -1717,7 +1717,7 @@ sim_resume (sd, step, siggnal)
     }
   /* Check for SIGBUS due to insn fetch.  */
   else if (! saved_state.asregs.exception)
-    saved_state.asregs.exception == SIGBUS;
+    saved_state.asregs.exception = SIGBUS;
 
   saved_state.asregs.ticks += get_now () - tick_start;
   saved_state.asregs.cycles += cycles;