From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Jun 2020 09:18:57 +0000 (+0100)
Subject: use PortInterface connect_port
X-Git-Tag: div_pipeline~231
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dca3d47c97c0b82db0a2b10d96baeb63e3ca83d3;p=soc.git

use PortInterface connect_port
---

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 9ebaa732..fcc8ad0b 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -176,18 +176,7 @@ class LDSTPort(Elaboratable):
 
     def connect_port(self, inport):
         print ("connect_port", self.pi, inport)
-        return [self.pi.is_ld_i.eq(inport.is_ld_i),
-                self.pi.is_st_i.eq(inport.is_st_i),
-                self.pi.data_len.eq(inport.data_len),
-                self.pi.go_die_i.eq(inport.go_die_i),
-                self.pi.addr.data.eq(inport.addr.data),
-                self.pi.addr.ok.eq(inport.addr.ok),
-                self.pi.st.eq(inport.st),
-                inport.ld.eq(self.pi.ld),
-                inport.busy_o.eq(self.pi.busy_o),
-                inport.addr_ok_o.eq(self.pi.addr_ok_o),
-                inport.addr_exc_o.eq(self.pi.addr_exc_o),
-                ]
+        return self.pi.connect_port(inport)
 
     def __iter__(self):
         yield self.pi.is_ld_i