From: lkcl <lkcl@web>
Date: Mon, 2 May 2022 15:54:44 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2513
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dcaa6b666109537aeb2de3c1137ed54e88d4901f;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 81e77284c..591afccdd 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -274,7 +274,9 @@ perform its operation at **half** the ELWIDTH then padded back out
 to ELWIDTH.  `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
-v3.0B "single" FP.
+v3.0B "single" FP.  Any FP operation ending in "s" where ELWIDTH=f16
+or ELWIDTH=bf16 is reserved and must raise an illegal instruction
+(IEEE754 FP8 or BF8 are not defined). 
 
 ## Elwidth for CRs: