From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Apr 2019 05:54:19 +0000 (+0100)
Subject: disable buffermode in test 12
X-Git-Tag: ls180-24jan2020~1307
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dcade61bf4aed307b7ea847f0a818f1a447e7136;p=ieee754fpu.git

disable buffermode in test 12
---

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index ae035054..6f81998a 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -136,7 +136,6 @@ class Test3:
                     send = True
                 else:
                     send = randint(0, send_range) != 0
-                send = True
                 o_p_ready = yield self.dut.p.o_ready
                 if not o_p_ready:
                     yield
@@ -210,6 +209,7 @@ class Test5:
                     send = True
                 else:
                     send = randint(0, send_range) != 0
+                #send = True
                 o_p_ready = yield self.dut.p.o_ready
                 if not o_p_ready:
                     yield
@@ -228,7 +228,7 @@ class Test5:
             stall_range = randint(0, 3)
             for j in range(randint(1,10)):
                 ready = randint(0, stall_range) != 0
-                ready = True
+                #ready = True
                 yield self.dut.n.i_ready.eq(ready)
                 yield
                 o_n_valid = yield self.dut.n.o_valid
@@ -627,7 +627,7 @@ class ExampleBufDelayedPipe(BufferedPipeline):
     def __init__(self):
         stage = ExampleStageDelayCls(valid_trigger=3)
         BufferedPipeline.__init__(self, stage, stage_ctl=True,
-                                    buffermode=False)
+                                    buffermode=True)
 
     def elaborate(self, platform):
         m = BufferedPipeline.elaborate(self, platform)