From: lkcl <lkcl@web>
Date: Sun, 5 Sep 2021 16:31:14 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~216
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dcb484de36f031d6ffb99ea517986806e05ca0cf;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index e52d3e075..40b5793dd 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -47,7 +47,7 @@ a number of different modes:
 Also included in SVP64 LD/ST is both signed and unsigned Saturation,
 as well as Eement-width overrides and Twin-Predication.
 
-*Missing* from Scalar Power ISA v3.0B is a scalar [[mv.x] instruction
+*Missing* from Scalar Power ISA v3.0B is a scalar [[mv.x]] instruction
 on top of which any good Vector ISA provides Vector Scatter-Gather.
 Due to the way that SVP64 is desigbed, this needs to be added separately
 (to Scalar Power ISA) before the