From: Jan Beulich Date: Thu, 26 Apr 2018 06:29:09 +0000 (+0200) Subject: x86: tighten assertion in build_modrm_byte() X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dcd7e323760ab296262a2e18e9869d37ff59f340;p=binutils-gdb.git x86: tighten assertion in build_modrm_byte() All VEX3SOURCES cases should have VexW set, and all should have a SIMD register destination. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 057a45fb0fb..7cd0a106b39 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2018-04-26 Jan Beulich + + * config/tc-i386.c (build_modrm_byte): Extend assertion in + vex_3_sources handling to cover more cases. + 2018-04-26 Jan Beulich * config/tc-i386.c (build_modrm_byte): Drop code dealing with diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 014720ea3c2..7126ca47fd1 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -6591,10 +6591,9 @@ build_modrm_byte (void) && i.tm.opcode_modifier.vexvvvv == VEXXDS && (i.tm.opcode_modifier.veximmext || (i.imm_operands == 1 - && i.types[0].bitfield.vec_imm4 - && (i.tm.opcode_modifier.vexw == VEXW0 - || i.tm.opcode_modifier.vexw == VEXW1) - && i.tm.operand_types[dest].bitfield.regsimd))); + && i.types[0].bitfield.vec_imm4)) + && i.tm.opcode_modifier.vexw + && i.tm.operand_types[dest].bitfield.regsimd); if (i.imm_operands == 0) {