From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 7 Feb 2015 10:40:19 +0000 (+0100)
Subject: Added cell->known(), cell->input(portname), cell->output(portname)
X-Git-Tag: yosys-0.5~24
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dce1fae777bcc9791c2f49be4b53f1de53df7502;p=yosys.git

Added cell->known(), cell->input(portname), cell->output(portname)
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 8c64217bb..b1e2c0e8e 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -19,6 +19,7 @@
 
 #include "kernel/yosys.h"
 #include "kernel/macc.h"
+#include "kernel/celltypes.h"
 #include "frontends/verilog/verilog_frontend.h"
 #include "backends/ilang/ilang_backend.h"
 
@@ -1928,6 +1929,39 @@ const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
 	return connections_;
 }
 
+bool RTLIL::Cell::known() const
+{
+	if (yosys_celltypes.cell_known(type))
+		return true;
+	if (module && module->design && module->design->module(type))
+		return true;
+	return false;
+}
+
+bool RTLIL::Cell::input(RTLIL::IdString portname) const
+{
+	if (yosys_celltypes.cell_known(type))
+		return yosys_celltypes.cell_input(type, portname);
+	if (module && module->design) {
+		RTLIL::Module *m = module->design->module(type);
+		RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
+		return w && w->port_input;
+	}
+	return false;
+}
+
+bool RTLIL::Cell::output(RTLIL::IdString portname) const
+{
+	if (yosys_celltypes.cell_known(type))
+		return yosys_celltypes.cell_output(type, portname);
+	if (module && module->design) {
+		RTLIL::Module *m = module->design->module(type);
+		RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
+		return w && w->port_output;
+	}
+	return false;
+}
+
 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
 {
 	return parameters.count(paramname) != 0;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index c17ede3d0..985bffe5e 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1140,6 +1140,11 @@ public:
 	const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const;
 	const dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;
 
+	// information about cell ports
+	bool known() const;
+	bool input(RTLIL::IdString portname) const;
+	bool output(RTLIL::IdString portname) const;
+
 	// access cell parameters
 	bool hasParam(RTLIL::IdString paramname) const;
 	void unsetParam(RTLIL::IdString paramname);