From: lkcl <lkcl@web>
Date: Sat, 23 Jan 2021 21:21:27 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~371
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dce47f70ab0d4a6bff1efcbd847f3d42a9f7fb92;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 7c1ffbaa5..58493763f 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -646,6 +646,8 @@ For actual assembler:
 
 Qualifiers:
 
+* m={pred}: predicate mask mode
+* sm={pred}: source-predicate mask mode (only allowed in Twin-predication)
 * vec{N}: vec2 OR vec3 OR vec4 - sets SUBVL=2/3/4
 * ew={N}: ew=8/16/32 - sets elwidth override
 * sw={N}: sw=8/16/32 - sets source elwidth override