From: chmousset <ch.mousset@gmail.com>
Date: Fri, 12 Jul 2019 14:37:23 +0000 (+0200)
Subject: [fix] Slave interface HP0 clk name
X-Git-Tag: 24jan2021_ls180~1107^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dcf55ad4f32664eb9edfc5d9f8f03e1778ef4713;p=litex.git

[fix] Slave interface HP0 clk name
---

diff --git a/litex/soc/integration/soc_zynq.py b/litex/soc/integration/soc_zynq.py
index a5451b25..4758cccb 100644
--- a/litex/soc/integration/soc_zynq.py
+++ b/litex/soc/integration/soc_zynq.py
@@ -142,7 +142,7 @@ class SoCZynq(SoCCore):
         self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout())
         self.ps7_params.update(
             # axi hp0 clk
-            i_M_AXI_HP0_ACLK=ClockSignal("sys"),
+            i_S_AXI_HP0_ACLK=ClockSignal("sys"),
 
             # axi hp0 aw
             i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid,