From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 16 Apr 2021 20:08:14 +0000 (+0100)
Subject: upload 32-bit wishbone data not 64-bit test data
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dcfe04fdaa5603e1b12308ae9893644b40fa8c71;p=soc-cocotb-sim.git

upload 32-bit wishbone data not 64-bit test data
---

diff --git a/ls180/post_pnr/cocotb/test.py b/ls180/post_pnr/cocotb/test.py
index 718faf5..a96846c 100644
--- a/ls180/post_pnr/cocotb/test.py
+++ b/ls180/post_pnr/cocotb/test.py
@@ -172,12 +172,12 @@ def wishbone_basic(dut):
     yield master.load_ir(cmd_MEMREADWRITE)
     dut._log.info("Writing memory")
 
-    data_in.binstr = "01010101" * 8
+    data_in.binstr = "01010101" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
 
-    data_in.binstr = "10101010" * 8
+    data_in.binstr = "10101010" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
     yield master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))