From: Diego Novillo Date: Thu, 7 Oct 1999 06:19:24 +0000 (+0000) Subject: Forgot to add these files in the previous commit. This is the X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd04745b740947b822d14c822603d9bce80dd6bf;p=binutils-gdb.git Forgot to add these files in the previous commit. This is the testsuite for the new instructions added to d10v gas. --- diff --git a/gas/testsuite/gas/d10v/d10.exp b/gas/testsuite/gas/d10v/d10.exp new file mode 100644 index 00000000000..9d437281d20 --- /dev/null +++ b/gas/testsuite/gas/d10v/d10.exp @@ -0,0 +1,19 @@ +# +# Driver for D10V assembler testsuite +# +proc run_list_test { name opts } { + global srcdir subdir + set testname "D10V $name" + set file $srcdir/$subdir/$name + gas_run ${name}.s $opts ">&dump.out" + if {[regexp_diff "dump.out" "${file}.l"] } { + fail $testname + verbose "output is [file_contents "dump.out"]" 2 + return + } + pass $testname +} + +if {[istarget d10v-*-*]} { + run_dump_test "inst" +} diff --git a/gas/testsuite/gas/d10v/inst.d b/gas/testsuite/gas/d10v/inst.d new file mode 100644 index 00000000000..ae3dafc820a --- /dev/null +++ b/gas/testsuite/gas/d10v/inst.d @@ -0,0 +1,22 @@ +#objdump: -dr +#name: D10V basic instruction test output +#as: + +.*: +file format elf32-d10v + +Disassembly of section .text: + +00000000 : + 0: a9 04 c2 29 sac r0, a0 <- sachi r1, a0 + 4: a9 06 c2 2d rac r0, a0, -0x2 <- rachi r1, a0, -0x2 + 8: 2f 00 32 26 nop || slae a0, r3 + c: f2 11 08 00 ld r1, @0x800 + 10: f3 01 08 00 ld2w r0, @0x800 + 14: f7 01 08 00 st2w r0, @0x800 + 18: f6 11 08 00 st r1, @0x800 + 1c: 6f 00 5e 00 nop -> nop + 20: 6f 00 5e 00 nop -> nop + 24: 2f 00 5e 00 nop || nop + 28: af 00 5e 00 nop <- nop + 2c: 23 11 de 00 not r1 || nop + 30: 63 21 de 00 not r2 -> nop diff --git a/gas/testsuite/gas/d10v/inst.s b/gas/testsuite/gas/d10v/inst.s new file mode 100644 index 00000000000..0a0fa744131 --- /dev/null +++ b/gas/testsuite/gas/d10v/inst.s @@ -0,0 +1,31 @@ +# test all instructions. FIXME: many instructions missing. + +start: + sachi r1, a0 + sac r0, a0 + # + # disassembler test. sachi&sac should not + # be confused with rachi&rac + # + rachi r1, a0, -0x2 + rac r0, a0, -0x2 + slae a0, r3 + ld r1, @0x0800 + ld2w r0, @0x0800 + st2w r0, @0x0800 + st r1, @0x0800 + +# VLIW syntax test + nop + nop + nop -> nop + nop || nop + nop <- nop + +# try changing sections + not r1 + .section .foo + add3 r10,r12,6 + .text + not r2 + nop