From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Mon, 16 Mar 2015 09:10:17 +0000 (-0700)
Subject: revamp vector tests with new privileged spec, and add scalar pt tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd0d4036430dc812c9168fad8870d58ce151f498;p=riscv-tests.git

revamp vector tests with new privileged spec, and add scalar pt tests
---

diff --git a/env b/env
index 4ea6fea..be65116 160000
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 4ea6feac5fe663fe82de53632883ced6205f57f8
+Subproject commit be6511639c2d9291e9050682c4d7ce3e7042d061
diff --git a/isa/Makefile b/isa/Makefile
index 9c7f37e..4c84815 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -6,9 +6,9 @@ isa_src_dir := .
 
 include $(isa_src_dir)/rv64ui/Makefrag
 include $(isa_src_dir)/rv64uf/Makefrag
-#include $(isa_src_dir)/rv64uv/Makefrag
+include $(isa_src_dir)/rv64uv/Makefrag
 include $(isa_src_dir)/rv64si/Makefrag
-#include $(isa_src_dir)/rv64sv/Makefrag
+include $(isa_src_dir)/rv64sv/Makefrag
 include $(isa_src_dir)/rv32ui/Makefrag
 include $(isa_src_dir)/rv32si/Makefrag
 
@@ -45,7 +45,7 @@ $$($(1)_p_tests): $(1)-p-%: $(1)/%.S
 $(1)_tests += $$($(1)_p_tests)
 
 $$($(1)_pt_tests): $(1)-pt-%: $(1)/%.S
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/pt -I$(isa_src_dir)/macros/scalar -T$(isa_src_dir)/../env/p/link.ld $$< -o $$@
+	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/pt -I$(isa_src_dir)/macros/scalar -T$(isa_src_dir)/../env/pt/link.ld $$< -o $$@
 $(1)_tests += $$($(1)_pt_tests)
 
 $$($(1)_pm_tests): $(1)-pm-%: $(1)/%.S
diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
index 81052a6..b4d0d78 100644
--- a/isa/macros/scalar/test_macros.h
+++ b/isa/macros/scalar/test_macros.h
@@ -570,9 +570,8 @@ test_ ## testnum: \
 #-----------------------------------------------------------------------
 
 #define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
-  csrs status, SR_EI; \
   la a0, handler ## testnum; \
-  csrw evec, a0; \
+  csrw stvec, a0; \
   vsetcfg nxreg, nfreg; \
   li a0, 4; \
   vsetvl a0, a0; \
@@ -631,9 +630,8 @@ handler ## testnum: \
   bne a1,a2,fail; \
 
 #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
-  csrs status, SR_EI; \
   la a0, handler ## testnum; \
-  csrw evec, a0; \
+  csrw stvec, a0; \
   vsetcfg nxreg, nfreg; \
   li a0, 4; \
   vsetvl a0, a0; \
diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag
index 942f8f7..9d90b92 100644
--- a/isa/rv32ui/Makefrag
+++ b/isa/rv32ui/Makefrag
@@ -3,7 +3,7 @@
 #-----------------------------------------------------------------------
 
 rv32ui_sc_tests = \
-   simple \
+	simple \
 	add addi \
 	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w \
 	and andi \
@@ -29,6 +29,7 @@ rv32ui_mc_tests = \
 	lrsc
 
 rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
+rv32ui_pt_tests = $(addprefix rv32ui-pt-, $(rv32ui_sc_tests))
 rv32ui_pm_tests = $(addprefix rv32ui-pm-, $(rv32ui_mc_tests))
 
-spike_tests += $(rv32ui_p_tests) $(rv32ui_pm_tests)
+spike_tests += $(rv32ui_p_tests) $(rv32ui_pt_tests) $(rv32ui_pm_tests)
diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index e42dacd..a2c9827 100644
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   li a0,33
   slli a0,a0,6
diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index 2923d90..db07744 100644
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   li a0,33
   vsetcfg a0
diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S
index add9918..ae46fe0 100644
--- a/isa/rv64sv/illegal_inst.S
+++ b/isa/rv64sv/illegal_inst.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   .word 0xff00002b
 
diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S
index 7ca7fba..a2090ac 100644
--- a/isa/rv64sv/illegal_tvec_regid.S
+++ b/isa/rv64sv/illegal_tvec_regid.S
@@ -10,18 +10,9 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA
-  csrs status, a0
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
-
   TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2)
   TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2)
 
diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index 235f52b..dd61697 100644
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4
diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S
index 2c2a5e6..24745dc 100644
--- a/isa/rv64sv/illegal_vt_regid.S
+++ b/isa/rv64sv/illegal_vt_regid.S
@@ -10,18 +10,9 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA
-  csrs status, a0
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
-
   TEST_ILLEGAL_VT_REGID(2, 5, 5, add, x7, x1, x2)
   TEST_ILLEGAL_VT_REGID(3, 5, 5, add, x1, x7, x2)
   TEST_ILLEGAL_VT_REGID(4, 5, 5, add, x1, x2, x7)
diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index 3bd7437..398396e 100644
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4
diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index fbece59..1390b54 100644
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -10,19 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
-  li a0, SR_EA | SR_EI
-  csrs status, a0
 
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4
diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index 77e5f04..4276b64 100644
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4
diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index ec76a86..2271e8f 100644
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4
diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index 6a17825..25c23c5 100644
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -10,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4
diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index 818c11f..b7b169e 100644
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -10,24 +10,18 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
-
-  la a0, SR_U64
-  csrs status, a0
-  csrc status, SR_S
+  csrw stvec,a3 # set exception handler
+
+  li a3, SSTATUS_PS
+  csrc sstatus, a3
+  la t0, 1f
+  csrw sepc, t0
+  sret
+1:
 
 privileged_inst:
   vxcptcause a3 # privileged inst
diff --git a/isa/rv64uf/Makefrag b/isa/rv64uf/Makefrag
index bf5cd33..f9ed202 100644
--- a/isa/rv64uf/Makefrag
+++ b/isa/rv64uf/Makefrag
@@ -7,12 +7,13 @@ rv64uf_sc_tests = \
 	ldst move structural \
 
 rv64uf_sc_vec_tests = \
-#	fadd fcmp fcvt fcvt_w fmadd fmin fsgnj \
+	fadd fcmp fcvt fcvt_w fmadd fmin fsgnj \
 
 rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests))
+rv64uf_pt_tests = $(addprefix rv64uf-pt-, $(rv64uf_sc_tests))
 rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests))
-#rv64uf_p_vec_tests = $(addprefix rv64uf-p-vec-, $(rv64uf_sc_vec_tests))
-#rv64uf_pt_vec_tests = $(addprefix rv64uf-pt-vec-, $(rv64uf_sc_vec_tests))
-#rv64uf_v_vec_tests = $(addprefix rv64uf-v-vec-, $(rv64uf_sc_vec_tests))
+rv64uf_p_vec_tests = $(addprefix rv64uf-p-vec-, $(rv64uf_sc_vec_tests))
+rv64uf_pt_vec_tests = $(addprefix rv64uf-pt-vec-, $(rv64uf_sc_vec_tests))
+rv64uf_v_vec_tests = $(addprefix rv64uf-v-vec-, $(rv64uf_sc_vec_tests))
 
-spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests) $(rv64uf_p_vec_tests) $(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests)
+spike_tests += $(rv64uf_p_tests) $(rv64uf_pt_tests) $(rv64uf_v_tests) $(rv64uf_p_vec_tests) $(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests)
diff --git a/isa/rv64ui/Makefrag b/isa/rv64ui/Makefrag
index a0f974d..53f9a7f 100644
--- a/isa/rv64ui/Makefrag
+++ b/isa/rv64ui/Makefrag
@@ -30,23 +30,24 @@ rv64ui_mc_tests = \
 	lrsc
 
 rv64ui_sc_vec_tests = \
-	#add addi addiw addw \
-	#and andi \
-	#lui \
-	#mul mulh mulhsu mulhu mulw \
-	#or ori \
-	#sll slli slliw sllw \
-	#slt slti sltiu sltu \
-	#sra srai sraiw sraw \
-	#srl srli srliw srlw \
-	#sub subw \
-	#xor xori \
+	add addi addiw addw \
+	and andi \
+	lui \
+	mul mulh mulhsu mulhu mulw \
+	or ori \
+	sll slli slliw sllw \
+	slt slti sltiu sltu \
+	sra srai sraiw sraw \
+	srl srli srliw srlw \
+	sub subw \
+	xor xori \
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests))
+rv64ui_pt_tests = $(addprefix rv64ui-pt-, $(rv64ui_sc_tests))
 rv64ui_pm_tests = $(addprefix rv64ui-pm-, $(rv64ui_mc_tests))
 rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests))
 rv64ui_p_vec_tests = $(addprefix rv64ui-p-vec-, $(rv64ui_sc_vec_tests))
 rv64ui_pt_vec_tests = $(addprefix rv64ui-pt-vec-, $(rv64ui_sc_vec_tests))
 rv64ui_v_vec_tests = $(addprefix rv64ui-v-vec-, $(rv64ui_sc_vec_tests))
 
-spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) $(rv64ui_v_tests) $(rv64ui_p_vec_tests) $(rv64ui_pt_vec_tests) $(rv64ui_v_vec_tests)
+spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) $(rv64ui_pt_tests) $(rv64ui_v_tests) $(rv64ui_p_vec_tests) $(rv64ui_pt_vec_tests) $(rv64ui_v_vec_tests)
diff --git a/isa/rv64uv/Makefrag b/isa/rv64uv/Makefrag
index b65d7c0..856721b 100644
--- a/isa/rv64uv/Makefrag
+++ b/isa/rv64uv/Makefrag
@@ -19,7 +19,6 @@ rv64uv_sc_tests = \
 	fcvt fma fma_many \
 	fmovn fmovz \
 	vvadd_d vvadd_w vvadd_fd vvadd_fw \
-	vvadd_packed \
 	vvmul_d \
 
 rv64uv_sc_vec_tests = \