From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 5 Jun 2019 21:16:24 +0000 (-0700)
Subject: Error out if no top module given before 'sim'
X-Git-Tag: yosys-0.9~87^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd134914cc93f7506504ad95aad438a468bb0fe8;p=yosys.git

Error out if no top module given before 'sim'
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 53e248adf..4c3022c70 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -88,6 +88,8 @@ struct SimInstance
 	SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
 			shared(shared), module(module), instance(instance), parent(parent), sigmap(module)
 	{
+		log_assert(module);
+
 		if (parent) {
 			log_assert(parent->children.count(instance) == 0);
 			parent->children[instance] = this;
@@ -848,6 +850,9 @@ struct SimPass : public Pass {
 
 		if (design->full_selection()) {
 			top_mod = design->top_module();
+
+			if (!top_mod)
+				log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
 		} else {
 			auto mods = design->selected_whole_modules();
 			if (GetSize(mods) != 1)