From: Michael Nolan <mtnolan2640@gmail.com>
Date: Thu, 21 May 2020 18:59:49 +0000 (-0400)
Subject: OP_CROP now working
X-Git-Tag: div_pipeline~973
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd188fe4a745e31e420a34fce8b327f645efc96e;p=soc.git

OP_CROP now working
---

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 38d708b0..3c794343 100644
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -58,7 +58,6 @@ class CRTestCase(FHDLTestCase):
                       self.test_name)
         test_data.append(tc)
 
-    @unittest.skip("broken")
     def test_crop(self):
         insns = ["crand", "cror", "crnand", "crnor", "crxor", "creqv",
                  "crandc", "crorc"]
@@ -71,7 +70,6 @@ class CRTestCase(FHDLTestCase):
             cr = random.randint(0, (1<<32)-1)
             self.run_tst_program(Program(lst), initial_cr=cr)
 
-    @unittest.skip("broken")
     def test_crand(self):
         for i in range(20):
             lst = ["crand 0, 11, 13"]
@@ -136,6 +134,7 @@ class TestRunner(FHDLTestCase):
     def set_inputs(self, alu, dec2, simulator):
         full_reg = yield dec2.e.read_cr_whole
 
+        print(simulator.cr.get_range().value)
         if full_reg:
             yield alu.p.data_i.full_cr.eq(simulator.cr.get_range().value)
         else:
@@ -226,6 +225,7 @@ class TestRunner(FHDLTestCase):
                     while not vld:
                         yield
                         vld = yield alu.n.valid_o
+                    yield
                     yield from self.assert_outputs(alu, pdecode2, simulator)
 
         sim.add_sync_process(process)