From: lkcl <lkcl@web>
Date: Sun, 21 Aug 2022 13:30:46 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~810
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd34b61983a29c72731fb0d3c68e384b83113b94;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 3c7a34456..dafa81d6e 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -292,11 +292,13 @@ Indexed LD is:
 
 Note in both cases that [[sv/svp64]] allows RA-as-a-dest in "update" mode (`ldux`) to be effectively a *completely different* register from RA-as-a-source.  This because there is room in svp64 to extend RA-as-src as well as RA-as-dest, both independently as scalar or vector *and* independently extending their range.
 
-*Programmer's note: being able to set RA-as-a-source to Vector
- but RA-as-a-destination as Scalar is **extremely valuable**
+*Programmer's note: being able to set RA-as-a-source
+ as separate from RA-as-a-destination as Scalar is **extremely valuable**
  once it is remembered that Simple-V element operations must
- be in Program Order. What that means is that the very last
- update to RA will *
+ be in Program Order, especially in loops, for saving on
+ multiple address computations. Care does have
+ to be taken however that RA-as-src is not overwritten by
+ RA-as-dest especially in element-strided Mode.*
 
 # LD/ST Indexed vs Indexed REMAP