From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 17 May 2020 17:17:24 +0000 (+0100)
Subject: whitespace cleanup
X-Git-Tag: div_pipeline~1105
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd34e38cc4ea07f44714c189644c61d6a4e4488c;p=soc.git

whitespace cleanup
---

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index afa97224..51001663 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -75,8 +75,6 @@ class ALUMainStage(PipeModBase):
                 for i in range(8):
                     comb += eqs[i].eq(src1 == self.i.b[8*i:8*(i+1)])
                 comb += self.o.cr0.eq(Cat(Const(0, 2), eqs.any(), Const(0, 1)))
-                    
-                
 
         ###### sticky overflow and context, both pass-through #####