From: whitequark <cz@m-labs.hk>
Date: Fri, 30 Aug 2019 08:35:52 +0000 (+0000)
Subject: build.dsl: allow both str and int resource attributes.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd40d6ef7a33e0d6d5d93fb3c6d625848df448a7;p=nmigen.git

build.dsl: allow both str and int resource attributes.
---

diff --git a/nmigen/build/dsl.py b/nmigen/build/dsl.py
index 7bcb9aa..ce685f7 100644
--- a/nmigen/build/dsl.py
+++ b/nmigen/build/dsl.py
@@ -92,8 +92,9 @@ def DiffPairsN(*args, **kwargs):
 class Attrs(OrderedDict):
     def __init__(self, **attrs):
         for key, value in attrs.items():
-            if not (value is None or isinstance(value, str) or hasattr(value, "__call__")):
-                raise TypeError("Value of attribute {} must be None, str, or callable, not {!r}"
+            if not (value is None or isinstance(value, (str, int)) or hasattr(value, "__call__")):
+                raise TypeError("Value of attribute {} must be None, int, str, or callable, "
+                                "not {!r}"
                                 .format(key, value))
 
         super().__init__(**attrs)
@@ -103,10 +104,8 @@ class Attrs(OrderedDict):
         for key, value in self.items():
             if value is None:
                 items.append("!" + key)
-            elif hasattr(value, "__call__"):
-                items.append(key + "=" + repr(value))
             else:
-                items.append(key + "=" + value)
+                items.append(key + "=" + repr(value))
         return "(attrs {})".format(" ".join(items))
 
 
diff --git a/nmigen/test/test_build_dsl.py b/nmigen/test/test_build_dsl.py
index bff2721..06d2667 100644
--- a/nmigen/test/test_build_dsl.py
+++ b/nmigen/test/test_build_dsl.py
@@ -109,9 +109,9 @@ class DiffPairsTestCase(FHDLTestCase):
 
 class AttrsTestCase(FHDLTestCase):
     def test_basic(self):
-        a = Attrs(IO_STANDARD="LVCMOS33", PULLUP="1")
+        a = Attrs(IO_STANDARD="LVCMOS33", PULLUP=1)
         self.assertEqual(a["IO_STANDARD"], "LVCMOS33")
-        self.assertEqual(repr(a), "(attrs IO_STANDARD=LVCMOS33 PULLUP=1)")
+        self.assertEqual(repr(a), "(attrs IO_STANDARD='LVCMOS33' PULLUP=1)")
 
     def test_remove(self):
         a = Attrs(FOO=None)
@@ -126,8 +126,8 @@ class AttrsTestCase(FHDLTestCase):
 
     def test_wrong_value(self):
         with self.assertRaises(TypeError,
-                msg="Value of attribute FOO must be None, str, or callable, not 1"):
-            a = Attrs(FOO=1)
+                msg="Value of attribute FOO must be None, int, str, or callable, not 1.0"):
+            a = Attrs(FOO=1.0)
 
 
 class ClockTestCase(FHDLTestCase):
@@ -142,7 +142,7 @@ class SubsignalTestCase(FHDLTestCase):
     def test_basic_pins(self):
         s = Subsignal("a", Pins("A0"), Attrs(IOSTANDARD="LVCMOS33"))
         self.assertEqual(repr(s),
-            "(subsignal a (pins io A0) (attrs IOSTANDARD=LVCMOS33))")
+            "(subsignal a (pins io A0) (attrs IOSTANDARD='LVCMOS33'))")
 
     def test_basic_diffpairs(self):
         s = Subsignal("a", DiffPairs("A0", "B0"))
@@ -223,7 +223,7 @@ class ResourceTestCase(FHDLTestCase):
         self.assertEqual(repr(r), "(resource serial 0"
                                   " (subsignal tx (pins o A0))"
                                   " (subsignal rx (pins i A1))"
-                                  " (attrs IOSTANDARD=LVCMOS33))")
+                                  " (attrs IOSTANDARD='LVCMOS33'))")
 
     def test_family(self):
         ios = [Subsignal("clk", Pins("A0", dir="o"))]