From: lkcl <lkcl@web>
Date: Thu, 23 Mar 2023 00:35:53 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls001_v3~94
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd42bf4c5c5a954cbcb6ea9545425e5d8283a0d1;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index d9b5b45b9..0f855974d 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -177,9 +177,9 @@ It requires certain guarantees to be provided.
 * Secondly, that no instruction shall change meaning to produce
   different results on different hardware (present or future).
 * Thirdly, that Scalar "defined words" (32 bit instruction
-  encodings) if Vwctorised will also always be implemented as
+  encodings) if Vectorised will also always be implemented as
   identical Scalar instructions (the sole semi-exception being
-  Vevtorised Branch-Conditional)
+  Vectorised Branch-Conditional)
 * Fourthly, that implementors are not permitted to either add
   arbitrary features nor implement features in an incompatible
   way. *(Performance may differ, but differing results are