From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Jul 2020 11:56:42 +0000 (+0100)
Subject: add SPR pipeline
X-Git-Tag: div_pipeline~162^2~98
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd47d2caf101216ca1675f1fcd8d490e65684f16;p=soc.git

add SPR pipeline
---

diff --git a/src/soc/fu/spr/pipeline.py b/src/soc/fu/spr/pipeline.py
new file mode 100644
index 00000000..fc3c7c29
--- /dev/null
+++ b/src/soc/fu/spr/pipeline.py
@@ -0,0 +1,22 @@
+from nmutil.singlepipe import ControlBase
+from nmutil.pipemodbase import PipeModBaseChain
+from soc.fu.trap.main_stage import SPRMainStage
+
+class SPRStages(PipeModBaseChain):
+    def get_chain(self):
+        main = SPRMainStage(self.pspec)
+        return [main]
+
+
+class SPRBasePipe(ControlBase):
+    def __init__(self, pspec):
+        ControlBase.__init__(self)
+        self.pspec = pspec
+        self.pipe1 = SPRStages(pspec)
+        self._eqs = self.connect([self.pipe1])
+
+    def elaborate(self, platform):
+        m = ControlBase.elaborate(self, platform)
+        m.submodules.pipe = self.pipe1
+        m.d.comb += self._eqs
+        return m