From: Sebastien Bourdeauducq Date: Tue, 9 Oct 2012 17:08:37 +0000 (+0200) Subject: Remove uses of the RE signal on field registers X-Git-Tag: 24jan2021_ls180~3083 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd6eacba622a8773d53a5910c7dd5f848b1db88b;p=litex.git Remove uses of the RE signal on field registers --- diff --git a/milkymist/dfii/__init__.py b/milkymist/dfii/__init__.py index 3f6c7a0a..cedca621 100644 --- a/milkymist/dfii/__init__.py +++ b/milkymist/dfii/__init__.py @@ -15,6 +15,7 @@ class PhaseInjector: self._rden = Field("rden", 1, WRITE_ONLY, READ_ONLY) self._command = RegisterFields("command", [self._cs, self._we, self._cas, self._ras, self._wren, self._rden]) + self._command_issue = RegisterRaw("command_issue") self._address = RegisterField("address", len(self.phase.address)) self._baddress = RegisterField("baddress", len(self.phase.bank)) @@ -23,13 +24,13 @@ class PhaseInjector: self._rddata = RegisterField("rddata", len(self.phase.rddata), READ_ONLY, WRITE_ONLY) def get_registers(self): - return [self._command, + return [self._command, self._command_issue, self._address, self._baddress, self._wrdata, self._rddata] def get_fragment(self): comb = [ - If(self._command.re, + If(self._command_issue.re, self.phase.cs_n.eq(~self._cs.r), self.phase.we_n.eq(~self._we.r), self.phase.cas_n.eq(~self._cas.r), @@ -42,8 +43,8 @@ class PhaseInjector: ), self.phase.address.eq(self._address.field.r), self.phase.bank.eq(self._baddress.field.r), - self.phase.wrdata_en.eq(self._command.re & self._wren.r), - self.phase.rddata_en.eq(self._command.re & self._rden.r), + self.phase.wrdata_en.eq(self._command_issue.re & self._wren.r), + self.phase.rddata_en.eq(self._command_issue.re & self._rden.r), self.phase.wrdata.eq(self._wrdata.field.r), self.phase.wrdata_mask.eq(0) ] diff --git a/milkymist/minimac3/__init__.py b/milkymist/minimac3/__init__.py index cb0699f4..98beba8a 100644 --- a/milkymist/minimac3/__init__.py +++ b/milkymist/minimac3/__init__.py @@ -26,7 +26,7 @@ class MiniMAC: self._rx_count_0 = RegisterField("rx_count_0", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._rx_count_1 = RegisterField("rx_count_1", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._tx_count = RegisterField("tx_count", _count_width, access_dev=READ_WRITE) - self._tx_start = RegisterField("tx_start", access_bus=WRITE_ONLY) + self._tx_start = RegisterRaw("tx_start") regs = [self._phy_reset, self._rx_count_0, self._rx_count_1, self._tx_count, self._tx_start] self._rx_event_0 = EventSourcePulse() diff --git a/software/bios/sdram.c b/software/bios/sdram.c index 233d1912..b80637e5 100644 --- a/software/bios/sdram.c +++ b/software/bios/sdram.c @@ -23,6 +23,18 @@ static void setaddr(int a) CSR_DFII_AL_P1 = a & 0x00ff; } +static void command_p0(int cmd) +{ + CSR_DFII_COMMAND_P0 = cmd; + CSR_DFII_COMMAND_ISSUE_P0 = 1; +} + +static void command_p1(int cmd) +{ + CSR_DFII_COMMAND_P1 = cmd; + CSR_DFII_COMMAND_ISSUE_P1 = 1; +} + static void init_sequence(void) { int i; @@ -34,33 +46,33 @@ static void init_sequence(void) /* Precharge All */ setaddr(0x0400); - CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS; + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); /* Load Extended Mode Register */ CSR_DFII_BA_P0 = 1; setaddr(0x0000); - CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS; + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); CSR_DFII_BA_P0 = 0; /* Load Mode Register */ setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */ - CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS; + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); cdelay(200); /* Precharge All */ setaddr(0x0400); - CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS; + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); /* 2x Auto Refresh */ for(i=0;i<2;i++) { setaddr(0); - CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS; + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS); cdelay(4); } /* Load Mode Register */ setaddr(0x0032); /* CL=3, BL=4 */ - CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS; + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); cdelay(200); } @@ -84,7 +96,7 @@ void ddrrow(char *_row) if(*_row == 0) { setaddr(0x0000); CSR_DFII_BA_P0 = 0; - CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS; + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); cdelay(15); printf("Precharged\n"); } else { @@ -95,7 +107,7 @@ void ddrrow(char *_row) } setaddr(row); CSR_DFII_BA_P0 = 0; - CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CS; + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS); cdelay(15); printf("Activated row %d\n", row); } @@ -119,7 +131,7 @@ void ddrrd(char *startaddr) setaddr(addr); CSR_DFII_BA_P0 = 0; - CSR_DFII_COMMAND_P0 = DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA; + command_p0(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA); cdelay(15); for(i=0;i<8;i++) @@ -152,7 +164,7 @@ void ddrwr(char *startaddr) setaddr(addr); CSR_DFII_BA_P1 = 0; - CSR_DFII_COMMAND_P1 = DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA; + command_p1(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA); } #define TEST_SIZE (4*1024*1024) diff --git a/software/include/hw/dfii.h b/software/include/hw/dfii.h index d90c75a8..fce38cf3 100644 --- a/software/include/hw/dfii.h +++ b/software/include/hw/dfii.h @@ -12,46 +12,48 @@ #define DFII_CONTROL_CKE 0x02 #define CSR_DFII_COMMAND_P0 DFII_CSR(0x04) -#define CSR_DFII_AH_P0 DFII_CSR(0x08) -#define CSR_DFII_AL_P0 DFII_CSR(0x0C) -#define CSR_DFII_BA_P0 DFII_CSR(0x10) -#define CSR_DFII_WD0_P0 DFII_CSR(0x14) -#define CSR_DFII_WD1_P0 DFII_CSR(0x18) -#define CSR_DFII_WD2_P0 DFII_CSR(0x1C) -#define CSR_DFII_WD3_P0 DFII_CSR(0x20) -#define CSR_DFII_WD4_P0 DFII_CSR(0x24) -#define CSR_DFII_WD5_P0 DFII_CSR(0x28) -#define CSR_DFII_WD6_P0 DFII_CSR(0x2C) -#define CSR_DFII_WD7_P0 DFII_CSR(0x30) -#define CSR_DFII_RD0_P0 DFII_CSR(0x34) -#define CSR_DFII_RD1_P0 DFII_CSR(0x38) -#define CSR_DFII_RD2_P0 DFII_CSR(0x3C) -#define CSR_DFII_RD3_P0 DFII_CSR(0x40) -#define CSR_DFII_RD4_P0 DFII_CSR(0x44) -#define CSR_DFII_RD5_P0 DFII_CSR(0x48) -#define CSR_DFII_RD6_P0 DFII_CSR(0x4C) -#define CSR_DFII_RD7_P0 DFII_CSR(0x50) - -#define CSR_DFII_COMMAND_P1 DFII_CSR(0x54) -#define CSR_DFII_AH_P1 DFII_CSR(0x58) -#define CSR_DFII_AL_P1 DFII_CSR(0x5C) -#define CSR_DFII_BA_P1 DFII_CSR(0x60) -#define CSR_DFII_WD0_P1 DFII_CSR(0x64) -#define CSR_DFII_WD1_P1 DFII_CSR(0x68) -#define CSR_DFII_WD2_P1 DFII_CSR(0x6C) -#define CSR_DFII_WD3_P1 DFII_CSR(0x70) -#define CSR_DFII_WD4_P1 DFII_CSR(0x74) -#define CSR_DFII_WD5_P1 DFII_CSR(0x78) -#define CSR_DFII_WD6_P1 DFII_CSR(0x7C) -#define CSR_DFII_WD7_P1 DFII_CSR(0x80) -#define CSR_DFII_RD0_P1 DFII_CSR(0x84) -#define CSR_DFII_RD1_P1 DFII_CSR(0x88) -#define CSR_DFII_RD2_P1 DFII_CSR(0x8C) -#define CSR_DFII_RD3_P1 DFII_CSR(0x90) -#define CSR_DFII_RD4_P1 DFII_CSR(0x94) -#define CSR_DFII_RD5_P1 DFII_CSR(0x98) -#define CSR_DFII_RD6_P1 DFII_CSR(0x9C) -#define CSR_DFII_RD7_P1 DFII_CSR(0xA0) +#define CSR_DFII_COMMAND_ISSUE_P0 DFII_CSR(0x08) +#define CSR_DFII_AH_P0 DFII_CSR(0x0C) +#define CSR_DFII_AL_P0 DFII_CSR(0x10) +#define CSR_DFII_BA_P0 DFII_CSR(0x14) +#define CSR_DFII_WD0_P0 DFII_CSR(0x18) +#define CSR_DFII_WD1_P0 DFII_CSR(0x1C) +#define CSR_DFII_WD2_P0 DFII_CSR(0x20) +#define CSR_DFII_WD3_P0 DFII_CSR(0x24) +#define CSR_DFII_WD4_P0 DFII_CSR(0x28) +#define CSR_DFII_WD5_P0 DFII_CSR(0x2C) +#define CSR_DFII_WD6_P0 DFII_CSR(0x30) +#define CSR_DFII_WD7_P0 DFII_CSR(0x34) +#define CSR_DFII_RD0_P0 DFII_CSR(0x38) +#define CSR_DFII_RD1_P0 DFII_CSR(0x3C) +#define CSR_DFII_RD2_P0 DFII_CSR(0x40) +#define CSR_DFII_RD3_P0 DFII_CSR(0x44) +#define CSR_DFII_RD4_P0 DFII_CSR(0x48) +#define CSR_DFII_RD5_P0 DFII_CSR(0x4C) +#define CSR_DFII_RD6_P0 DFII_CSR(0x50) +#define CSR_DFII_RD7_P0 DFII_CSR(0x54) + +#define CSR_DFII_COMMAND_P1 DFII_CSR(0x58) +#define CSR_DFII_COMMAND_ISSUE_P1 DFII_CSR(0x5C) +#define CSR_DFII_AH_P1 DFII_CSR(0x60) +#define CSR_DFII_AL_P1 DFII_CSR(0x64) +#define CSR_DFII_BA_P1 DFII_CSR(0x68) +#define CSR_DFII_WD0_P1 DFII_CSR(0x6C) +#define CSR_DFII_WD1_P1 DFII_CSR(0x70) +#define CSR_DFII_WD2_P1 DFII_CSR(0x74) +#define CSR_DFII_WD3_P1 DFII_CSR(0x78) +#define CSR_DFII_WD4_P1 DFII_CSR(0x7C) +#define CSR_DFII_WD5_P1 DFII_CSR(0x80) +#define CSR_DFII_WD6_P1 DFII_CSR(0x84) +#define CSR_DFII_WD7_P1 DFII_CSR(0x88) +#define CSR_DFII_RD0_P1 DFII_CSR(0x8C) +#define CSR_DFII_RD1_P1 DFII_CSR(0x90) +#define CSR_DFII_RD2_P1 DFII_CSR(0x94) +#define CSR_DFII_RD3_P1 DFII_CSR(0x98) +#define CSR_DFII_RD4_P1 DFII_CSR(0x9C) +#define CSR_DFII_RD5_P1 DFII_CSR(0xA0) +#define CSR_DFII_RD6_P1 DFII_CSR(0xA4) +#define CSR_DFII_RD7_P1 DFII_CSR(0xA8) #define DFII_COMMAND_CS 0x01 #define DFII_COMMAND_WE 0x02