From: Cesar Strauss <cestrauss@gmail.com>
Date: Mon, 20 Jul 2020 22:00:59 +0000 (-0300)
Subject: Document the move of sdir from data_i to op.
X-Git-Tag: semi_working_ecp5~665
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd7b67691a24e7b3ec2efab04c66b8c8064edc38;p=soc.git

Document the move of sdir from data_i to op.

Also, give op.sdir a name based on "op", to distinguish it
from internal signals.
---

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index f3b67264..1bc9661d 100644
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -53,7 +53,9 @@ class Shifter(Elaboratable):
     *                 On POWER, range is 0 to 63 for 32-bit,
     *                 and 0 to 127 for 64-bit.
     *                 Other values wrap around.
-    * p.data_i.sdir:   shift direction (0 = left, 1 = right)
+
+    Operation type
+    * op.sdir:       shift direction (0 = left, 1 = right)
 
     Next port data:
     * n.data_o.data: shifted value
@@ -82,7 +84,7 @@ class Shifter(Elaboratable):
         self.n.data_o = Shifter.NextData(width)
 
         # more pieces to make this example class comply with the CompALU API
-        self.op = CompFSMOpSubset()
+        self.op = CompFSMOpSubset(name="op")
         self.p.data_i.ctx.op = self.op
         self.i = self.p.data_i._get_data()
         self.out = self.n.data_o._get_data()