From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 18 Sep 2022 08:06:04 +0000 (+0300)
Subject: power_insn: simplify subvl disassembly
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dd9c1edac3d6bba07cff6370cf1499bc53c3f11b;p=openpower-isa.git

power_insn: simplify subvl disassembly
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index a86e281f..2007aade 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1283,12 +1283,13 @@ class BaseRM(_Mapping):
 
     @property
     def specifiers(self):
-        if self.subvl == 1:
-            yield "vec2"
-        elif self.subvl == 2:
-            yield "vec3"
-        elif self.subvl == 3:
-            yield "vec4"
+        subvl = int(self.subvl)
+        if subvl > 0:
+            yield {
+                1: "vec2",
+                2: "vec3",
+                3: "vec4",
+            }[subvl]
 
     def disassemble(self, verbosity=Verbosity.NORMAL):
         if verbosity >= Verbosity.VERBOSE: