From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 1 Jul 2019 16:46:32 +0000 (-0700)
Subject: Merge branch 'master' into eddie/script_from_wire
X-Git-Tag: working-ls180~1227^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dda2ec3cc5554f610bfcb86272dfb0a412abad66;p=yosys.git

Merge branch 'master' into eddie/script_from_wire
---

dda2ec3cc5554f610bfcb86272dfb0a412abad66
diff --cc CHANGELOG
index af9642d66,5535ce418..b54897d89
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -2,13 -2,18 +2,24 @@@
  List of major changes and improvements between releases
  =======================================================
  
 +Yosys 0.9 .. Yosys 0.9-dev
 +--------------------------
 +
 + * Various
 +    - Added "script -select"
 +
  
+ Yosys 0.9 .. Yosys 0.9-dev
+ --------------------------
+ 
+  * Various
+     - Added "write_xaiger" backend
+     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
+     - Added "synth_xilinx -abc9" (experimental)
+     - Added "synth_ice40 -abc9" (experimental)
+     - Added "synth -abc9" (experimental)
+ 
+ 
  Yosys 0.8 .. Yosys 0.8-dev
  --------------------------