From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Sep 2019 11:42:01 +0000 (+0100)
Subject: mention AMD RDNA
X-Git-Tag: convert-csv-opcode-to-binary~4111
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ddcafd0087a52bde4ceb24c407394fd18d700471;p=libreriscv.git

mention AMD RDNA
---

diff --git a/ztrans_proposal.mdwn b/ztrans_proposal.mdwn
index 8a0fdf909..7a6b03803 100644
--- a/ztrans_proposal.mdwn
+++ b/ztrans_proposal.mdwn
@@ -462,7 +462,8 @@ Vivante Embedded/Mobile 3D (etnaviv <https://github.com/laanwj/etna_viv/blob/mas
 
 It also has fast variants of some of these, as a CSR Mode.
 
-AMD's R600 GPU (R600\_Instruction\_Set\_Architecture.pdf) has:
+AMD's R600 GPU (R600\_Instruction\_Set\_Architecture.pdf) and the
+RDNA ISA (RDNA\_Shader\_ISA\_5August2019.pdf, Table 22, Section 6.3) have:
 
     COS (appx)
     EXP2
@@ -472,6 +473,11 @@ AMD's R600 GPU (R600\_Instruction\_Set\_Architecture.pdf) has:
     SQRT
     SIN (appx)
 
+AMD RDNA has F16 and F32 variants of all the above, and also has F64
+variants of SQRT, RSQRT and RECIP.  It is interesting that even the
+modern high-end AMD GPU does not have TAN or ATAN, where MALI Midgard
+does.
+
 Also a general point, that customised optimised hardware targetting
 FP32 3D with less accuracy simply can neither be used for IEEE754 nor
 for FP64 (except as a starting point for hardware or software driven