From: Rob Clark Date: Fri, 24 Jul 2020 17:34:47 +0000 (-0700) Subject: freedreno: add CI for envytools tools X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ddcee248adfc5bdd4af25eb81ed981f2ec64d109;p=mesa.git freedreno: add CI for envytools tools This also tunes `.freedreno-rules` a bit so that it isn't triggered by various tools that don't effect the driver build. The .gitlab-ci directory is kept separate from the toplevel one so that updates to (for example) reference decode output do not trigger all the other-driver jobs to run. Signed-off-by: Rob Clark Part-of: --- diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 374e79def22..738ca9c02ff 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -221,7 +221,7 @@ x86_build: extends: - .use-x86_build-base variables: - FDO_DISTRIBUTION_TAG: &x86_build "2020-07-21-tracie" + FDO_DISTRIBUTION_TAG: &x86_build "2020-07-27-fdtools" .use-x86_build: variables: @@ -554,6 +554,7 @@ meson-gallium: script: - .gitlab-ci/meson-build.sh - .gitlab-ci/run-shader-db.sh + - src/freedreno/.gitlab-ci/run-fdtools.sh meson-classic: extends: .meson-build diff --git a/.gitlab-ci/container/x86_build.sh b/.gitlab-ci/container/x86_build.sh index b2220a61faa..1c6fd1ba641 100644 --- a/.gitlab-ci/container/x86_build.sh +++ b/.gitlab-ci/container/x86_build.sh @@ -26,6 +26,9 @@ apt-get update apt-get install -y --no-remove \ $STABLE_EPHEMERAL \ + libarchive-dev \ + liblua5.3-dev \ + libxml2-dev \ wine-development \ wine32-development diff --git a/.gitlab-ci/test-source-dep.yml b/.gitlab-ci/test-source-dep.yml index 93e67ceff0f..23561445a53 100644 --- a/.gitlab-ci/test-source-dep.yml +++ b/.gitlab-ci/test-source-dep.yml @@ -89,7 +89,17 @@ *gallium_core_file_list when: on_success - changes: - - src/freedreno/**/* + # Note: when https://gitlab.com/gitlab-org/gitlab/-/issues/198688 + # is supported, we can change the src/freedreno/ rule to explicitly + # exclude tools, rather than having to explicitly list everything + # else + - src/freedreno/common/**/* + - src/freedreno/drm/**/* + - src/freedreno/fdl/**/* + - src/freedreno/ir3/**/* + - src/freedreno/perfcntrs/**/* + - src/freedreno/registers/**/* + - src/freedreno/vulkan/**/* - src/gallium/drivers/freedreno/**/* - src/gallium/winsys/freedreno/**/* when: on_success diff --git a/src/freedreno/.gitlab-ci/README.rst b/src/freedreno/.gitlab-ci/README.rst new file mode 100644 index 00000000000..b232bc50d47 --- /dev/null +++ b/src/freedreno/.gitlab-ci/README.rst @@ -0,0 +1,33 @@ +Continuous Integration +====================== + +In addition to a build step, the CI setup has a basic test stage +to ensure that we don't break functionality of various tools. The +basic idea is to decode various files and compare the output to a +reference. This means that some changes, like renaming registers +or bitfields in the rnndb xml requires updating the reference +output. + +Layout: + - .gitlab-ci/ + + - traces/ - reference devcoredump and cmdstream traces. The trace files should be kept small, and .rd files (which are already binary) should be compressed. + + - reference/ - reference output + + - genoutput.sh - script to generate output from the traces, used both by the CI test job, but it can also be used to update the reference output + +Note on paths: +-------------- + +Gitlab CI uses an install-path of \`pwd\`/install. If you use something +different, then setup a symlink. Once that is done, to update reference +decodes (ie. to account for register .xml changes) run: + + ./src/freedreno/.gitlab-ci/genoutput.sh --update + +TODO +---- +- Maybe we could filter out some differences, like a new definition of a previously unknown register? +- It would be nice to add a test for afuc.. we probably cannot add a "real" fw file to this tree, but maybe could either fetch it from the linux-firmware git tree, or create our own dummy fw. + diff --git a/src/freedreno/.gitlab-ci/genoutput.sh b/src/freedreno/.gitlab-ci/genoutput.sh new file mode 100755 index 00000000000..7504b861cab --- /dev/null +++ b/src/freedreno/.gitlab-ci/genoutput.sh @@ -0,0 +1,50 @@ +#!/bin/bash + +# This file contains all of the cmdlines used to generate output +# for the test step in the CI pipeline. It can also be used to +# regenerate reference output + +set -x +set -e + +# input/output directories: +base=src/freedreno +traces=$base/.gitlab-ci/traces +output=$base/.gitlab-ci/out + +# use the --update arg to update reference output: +if [ "$1" = "--update" ]; then + output=src/freedreno/.gitlab-ci/reference +fi + +mkdir -p $output + +# binary locations: +cffdump=./install/bin/cffdump +crashdec=./install/bin/crashdec + +# helper to filter out paths that can change depending on +# who is building: +basepath=`dirname $0` +basepath=`dirname $basepath` +basepath=`pwd $basepath` +filter() { + out=$1 + grep -vF "$basepath" > $out +} + +# +# The Tests: +# + +# dump only a single frame, and single tile pass, to keep the +# reference output size managable +$cffdump --frame 0 --once $traces/fd-clouds.rd.gz | filter $output/fd-clouds.log +$cffdump --frame 0 --once $traces/es2gears-a320.rd.gz | filter $output/es2gears-a320.log +$cffdump --frame 1 --once $traces/glxgears-a420.rd.gz | filter $output/glxgears-a420.log + +# test a lua script to ensure we don't break scripting API: +$cffdump --script $base/decode/scripts/parse-submits.lua $traces/shadow.rd.gz | filter $output/shadow.log + +$crashdec -sf $traces/crash.devcore | filter $output/crash.log + diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log new file mode 100644 index 00000000000..34a06da730e --- /dev/null +++ b/src/freedreno/.gitlab-ci/reference/crash.log @@ -0,0 +1,8808 @@ +--- +kernel: 5.8.0-rc1-c630+ +module: msm +time: 1593887022.767858793 +comm: crashit +cmdline: ./crashit IB1 4 5 +revision: 630 (6.3.0.2) +Got gpu_id=630 +rbbm-status: 0x00000000 +ringbuffer: + - id: 0 + iova: 0x0001000000001000 + last-fence: 1 + retired-fence: 0 + rptr: 40 + wptr: 56 + size: 32768 +bos: + - iova: 0x0000000100000000 + size: 4096 +registers: + 00800005 RBBM_STATUS: { GPU_BUSY_IGN_AHB | CP_BUSY | CP_AHB_BUSY_CX_MASTER } + 00000000 0x211: 00000000 + 00000000 0x212: 00000000 + 00000000 RBBM_STATUS3: { 0 } + 8100430e 0x825: 8100430e + 200a0000 VBIF_VERSION: 0x200a0000 + 00000000 VBIF_CLKON: { 0 } + 00000000 0x3002: 00000000 + 00000000 0x3003: 00000000 + 00000000 0x3004: 00000000 + 00000000 0x3005: 00000000 + 00000000 0x3006: 00000000 + 00000000 0x3007: 00000000 + 00000000 0x300c: 00000000 + 00000000 0x300d: 00000000 + 00000000 0x300e: 00000000 + 00000000 0x300f: 00000000 + 00000000 0x3010: 00000000 + 00000000 0x3011: 00000000 + 00000000 0x3012: 00000000 + 00000000 0x3013: 00000000 + 00000000 0x3014: 00000000 + 00000000 0x3018: 00000000 + 00000000 0x3019: 00000000 + 00000000 0x301a: 00000000 + 00000000 0x301b: 00000000 + 0001001f 0x301c: 0001001f + 000000a4 0x301d: 000000a4 + 00000000 0x301e: 00000000 + 00000000 0x301f: 00000000 + 00000000 0x3020: 00000000 + 00000000 0x3021: 00000000 + 00000000 0x3022: 00000000 + 00000000 0x3023: 00000000 + 00000000 0x3024: 00000000 + 00000000 0x3025: 00000000 + 00000000 0x3026: 00000000 + 00000000 0x3027: 00000000 + 00000000 0x3028: 00000000 + 00000000 0x3029: 00000000 + 00000009 VBIF_GATE_OFF_WRREQ_EN: 0x9 + 00000000 0x302b: 00000000 + 103f3f20 0x302c: 103f3f20 + 00000004 0x302d: 00000004 + 10202020 0x3030: 10202020 + 00000004 0x3031: 00000004 + 00003f3f 0x3034: 00003f3f + 00002020 0x3035: 00002020 + 00000707 0x3036: 00000707 + 00000030 0x303c: 00000030 + 00000000 0x303d: 00000000 + 00043210 0x3040: 00043210 + 00000000 0x3042: 00000000 + 00000003 0x3049: 00000003 + 00022222 0x3058: 00022222 + 00000000 0x305a: 00000000 + 00000000 0x305b: 00000000 + 0000001f 0x305c: 0000001f + 00000000 0x305d: 00000000 + 0000001f 0x305e: 0000001f + 001f001f 0x305f: 001f001f + 00000000 0x3060: 00000000 + 00000000 0x3061: 00000000 + 00000000 0x3064: 00000000 + 00000000 0x3065: 00000000 + 00000000 0x3066: 00000000 + 00000000 0x3067: 00000000 + 00000000 0x3068: 00000000 + 00000000 0x306c: 00000000 + 00000000 0x306d: 00000000 + 00000000 VBIF_XIN_HALT_CTRL0: 0 + 001f0000 VBIF_XIN_HALT_CTRL1: 0x1f0000 + 00000000 0x3082: 00000000 + 00000030 0x3083: 00000030 + 00000000 VBIF_TEST_BUS_OUT_CTRL: 0 + 00000000 VBIF_TEST_BUS1_CTRL0: 0 + 00000000 VBIF_TEST_BUS1_CTRL1: { DATA_SEL = 0 } + 00000000 VBIF_TEST_BUS2_CTRL0: 0 + 00000000 VBIF_TEST_BUS2_CTRL1: { DATA_SEL = 0 } + 00000000 0x308b: 00000000 + 00000000 VBIF_TEST_BUS_OUT: 0 + 00000000 0x3090: 00000000 + 00000000 0x3091: 00000000 + 00000000 0x3092: 00000000 + 00000000 0x3093: 00000000 + 00000000 0x3094: 00000000 + 00000000 0x3098: 00000000 + 00000000 0x309c: 00000000 + 00000000 0x30c0: 00000000 + 00000000 0x30c8: 00000000 + 00000000 VBIF_PERF_CNT_SEL0: 0 + 00000000 VBIF_PERF_CNT_LOW0: 0 + 00000000 VBIF_PERF_CNT_HIGH0: 0 + 00000000 VBIF_PERF_PWR_CNT_EN0: 0 + 00000000 0x3108: 00000000 + 00000000 VBIF_PERF_PWR_CNT_LOW0: 0 + 00000000 VBIF_PERF_PWR_CNT_HIGH0: 0 + 00000000 0x3120: 00000000 + 00000000 0x3124: 00000000 + 00000000 0x3125: 00000000 + 00000000 0x3129: 00000000 + 00000000 0x3131: 00000000 + 00000000 0x3154: 00000000 + 00011111 0x3156: 00011111 + 00022222 0x3158: 00022222 + 00033333 0x315a: 00033333 + 00000000 0x315c: 00000000 + 00011111 0x315e: 00011111 + 00022222 0x3160: 00022222 + 00033333 0x3162: 00033333 + 00000000 0x340c: 00000000 + 00000000 0x3410: 00000000 + 00000000 0x3800: 00000000 + 00000001 0x3801: 00000001 + 00010003 0: 00010003 + d6f00006 0x1: d6f00006 + 02402892 0x2: 02402892 + 00000003 RBBM_VBIF_CLIENT_QOS_CNTL: 0x3 + 00000000 0x12: 00000000 + 00000000 0x18: 00000000 + 00000000 0x19: 00000000 + 00000030 0x1a: 00000030 + 00000030 0x1b: 00000030 + 00000000 0x1e: 00000000 + 401fffff RBBM_INTERFACE_HANG_INT_CNTL: 0x401fffff + 00000000 0x20: 00000000 + 00000000 0x21: 00000000 + 00000000 0x22: 00000000 + 00000000 0x23: 00000000 + 00000000 0x24: 00000000 + 00000000 0x25: 00000000 + 00000000 0x26: 00000000 + 00000000 0x27: 00000000 + 00000000 0x28: 00000000 + 00000000 0x29: 00000000 + 00000000 0x2a: 00000000 + 00000000 0x2b: 00000000 + 00000000 0x2c: 00000000 + 00000000 0x2d: 00000000 + 00000000 0x2e: 00000000 + 00000000 0x2f: 00000000 + 00000000 0x30: 00000000 + 00000000 0x31: 00000000 + 00000000 0x32: 00000000 + 03d0e242 RBBM_INT_0_MASK: 0x3d0e242 + 00000000 0x39: 00000000 + 00000010 0x3a: 00000010 + 00000000 0x3b: 00000000 + 00000000 0x3c: 00000000 + 00000000 RBBM_SP_HYST_CNT: 0 + 00000000 RBBM_RAC_THRESHOLD_CNT: 0 + 00000000 0x47: 00000000 + 00000000 0x56: 00000000 + 00000000 0xad: 00000000 + 8aa8aa02 RBBM_CLOCK_CNTL: 0x8aa8aa02 + 22222222 RBBM_CLOCK_CNTL_SP0: 0x22222222 + 22222222 RBBM_CLOCK_CNTL_SP1: 0x22222222 + 22222222 RBBM_CLOCK_CNTL_SP2: 0x22222222 + 22222222 RBBM_CLOCK_CNTL_SP3: 0x22222222 + 02022220 RBBM_CLOCK_CNTL2_SP0: 0x2022220 + 02022220 RBBM_CLOCK_CNTL2_SP1: 0x2022220 + 02022220 RBBM_CLOCK_CNTL2_SP2: 0x2022220 + 02022220 RBBM_CLOCK_CNTL2_SP3: 0x2022220 + 00000080 RBBM_CLOCK_DELAY_SP0: 0x80 + 00000080 RBBM_CLOCK_DELAY_SP1: 0x80 + 00000080 RBBM_CLOCK_DELAY_SP2: 0x80 + 00000080 RBBM_CLOCK_DELAY_SP3: 0x80 + 0000f3cf RBBM_CLOCK_HYST_SP0: 0xf3cf + 0000f3cf RBBM_CLOCK_HYST_SP1: 0xf3cf + 0000f3cf RBBM_CLOCK_HYST_SP2: 0xf3cf + 0000f3cf RBBM_CLOCK_HYST_SP3: 0xf3cf + 02222222 RBBM_CLOCK_CNTL_TP0: 0x2222222 + 02222222 RBBM_CLOCK_CNTL_TP1: 0x2222222 + 02222222 RBBM_CLOCK_CNTL_TP2: 0x2222222 + 02222222 RBBM_CLOCK_CNTL_TP3: 0x2222222 + 22222222 RBBM_CLOCK_CNTL2_TP0: 0x22222222 + 22222222 RBBM_CLOCK_CNTL2_TP1: 0x22222222 + 22222222 RBBM_CLOCK_CNTL2_TP2: 0x22222222 + 22222222 RBBM_CLOCK_CNTL2_TP3: 0x22222222 + 22222222 RBBM_CLOCK_CNTL3_TP0: 0x22222222 + 22222222 RBBM_CLOCK_CNTL3_TP1: 0x22222222 + 22222222 RBBM_CLOCK_CNTL3_TP2: 0x22222222 + 22222222 RBBM_CLOCK_CNTL3_TP3: 0x22222222 + 00022222 RBBM_CLOCK_CNTL4_TP0: 0x22222 + 00022222 RBBM_CLOCK_CNTL4_TP1: 0x22222 + 00022222 RBBM_CLOCK_CNTL4_TP2: 0x22222 + 00022222 RBBM_CLOCK_CNTL4_TP3: 0x22222 + 11111111 RBBM_CLOCK_DELAY_TP0: 0x11111111 + 11111111 RBBM_CLOCK_DELAY_TP1: 0x11111111 + 11111111 RBBM_CLOCK_DELAY_TP2: 0x11111111 + 11111111 RBBM_CLOCK_DELAY_TP3: 0x11111111 + 11111111 RBBM_CLOCK_DELAY2_TP0: 0x11111111 + 11111111 RBBM_CLOCK_DELAY2_TP1: 0x11111111 + 11111111 RBBM_CLOCK_DELAY2_TP2: 0x11111111 + 11111111 RBBM_CLOCK_DELAY2_TP3: 0x11111111 + 11111111 RBBM_CLOCK_DELAY3_TP0: 0x11111111 + 11111111 RBBM_CLOCK_DELAY3_TP1: 0x11111111 + 11111111 RBBM_CLOCK_DELAY3_TP2: 0x11111111 + 11111111 RBBM_CLOCK_DELAY3_TP3: 0x11111111 + 00011111 RBBM_CLOCK_DELAY4_TP0: 0x11111 + 00011111 RBBM_CLOCK_DELAY4_TP1: 0x11111 + 00011111 RBBM_CLOCK_DELAY4_TP2: 0x11111 + 00011111 RBBM_CLOCK_DELAY4_TP3: 0x11111 + 77777777 RBBM_CLOCK_HYST_TP0: 0x77777777 + 77777777 RBBM_CLOCK_HYST_TP1: 0x77777777 + 77777777 RBBM_CLOCK_HYST_TP2: 0x77777777 + 77777777 RBBM_CLOCK_HYST_TP3: 0x77777777 + 77777777 RBBM_CLOCK_HYST2_TP0: 0x77777777 + 77777777 RBBM_CLOCK_HYST2_TP1: 0x77777777 + 77777777 RBBM_CLOCK_HYST2_TP2: 0x77777777 + 77777777 RBBM_CLOCK_HYST2_TP3: 0x77777777 + 77777777 RBBM_CLOCK_HYST3_TP0: 0x77777777 + 77777777 RBBM_CLOCK_HYST3_TP1: 0x77777777 + 77777777 RBBM_CLOCK_HYST3_TP2: 0x77777777 + 77777777 RBBM_CLOCK_HYST3_TP3: 0x77777777 + 00077777 RBBM_CLOCK_HYST4_TP0: 0x77777 + 00077777 RBBM_CLOCK_HYST4_TP1: 0x77777 + 00077777 RBBM_CLOCK_HYST4_TP2: 0x77777 + 00077777 RBBM_CLOCK_HYST4_TP3: 0x77777 + 22222222 RBBM_CLOCK_CNTL_RB0: 0x22222222 + 22222222 RBBM_CLOCK_CNTL_RB1: 0x22222222 + 22222222 RBBM_CLOCK_CNTL_RB2: 0x22222222 + 22222222 RBBM_CLOCK_CNTL_RB3: 0x22222222 + 00002222 RBBM_CLOCK_CNTL2_RB0: 0x2222 + 00002222 RBBM_CLOCK_CNTL2_RB1: 0x2222 + 00002222 RBBM_CLOCK_CNTL2_RB2: 0x2222 + 00002222 RBBM_CLOCK_CNTL2_RB3: 0x2222 + 00002220 RBBM_CLOCK_CNTL_CCU0: 0x2220 + 00002220 RBBM_CLOCK_CNTL_CCU1: 0x2220 + 00002220 RBBM_CLOCK_CNTL_CCU2: 0x2220 + 00002220 RBBM_CLOCK_CNTL_CCU3: 0x2220 + 00000f00 RBBM_CLOCK_HYST_RB_CCU0: 0xf00 + 00000f00 RBBM_CLOCK_HYST_RB_CCU1: 0xf00 + 00000f00 RBBM_CLOCK_HYST_RB_CCU2: 0xf00 + 00000f00 RBBM_CLOCK_HYST_RB_CCU3: 0xf00 + 05022022 RBBM_CLOCK_CNTL_RAC: 0x5022022 + 00005555 RBBM_CLOCK_CNTL2_RAC: 0x5555 + 00000011 RBBM_CLOCK_DELAY_RAC: 0x11 + 00445044 RBBM_CLOCK_HYST_RAC: 0x445044 + 04222222 RBBM_CLOCK_CNTL_TSE_RAS_RBBM: 0x4222222 + 00004000 RBBM_CLOCK_DELAY_TSE_RAS_RBBM: 0x4000 + 00000000 RBBM_CLOCK_HYST_TSE_RAS_RBBM: 0 + 22222222 RBBM_CLOCK_CNTL_UCHE: 0x22222222 + 22222222 RBBM_CLOCK_CNTL2_UCHE: 0x22222222 + 22222222 RBBM_CLOCK_CNTL3_UCHE: 0x22222222 + 00222222 RBBM_CLOCK_CNTL4_UCHE: 0x222222 + 00000002 RBBM_CLOCK_DELAY_UCHE: 0x2 + 00000004 RBBM_CLOCK_HYST_UCHE: 0x4 + 00002222 RBBM_CLOCK_MODE_VFD: 0x2222 + 00002222 RBBM_CLOCK_DELAY_VFD: 0x2222 + 00000000 RBBM_CLOCK_HYST_VFD: 0 + 00222222 RBBM_CLOCK_MODE_GPC: 0x222222 + 00000200 RBBM_CLOCK_DELAY_GPC: 0x200 + 04104004 RBBM_CLOCK_HYST_GPC: 0x4104004 + 00000002 RBBM_CLOCK_DELAY_HLSQ_2: 0x2 + 00000222 RBBM_CLOCK_CNTL_GMU_GX: 0x222 + 00000111 RBBM_CLOCK_DELAY_GMU_GX: 0x111 + 00000555 RBBM_CLOCK_HYST_GMU_GX: 0x555 + 00002222 RBBM_CLOCK_MODE_HLSQ: 0x2222 + 00000000 RBBM_CLOCK_DELAY_HLSQ: 0 + 00000000 RBBM_CLOCK_HYST_HLSQ: 0 + 00000001 0x200: 00000001 + 00000000 RBBM_INT_0_STATUS: { 0 } + 00000000 0x202: 00000000 + 00000000 0x203: 00000000 + 00000000 0x204: 00000000 + 00000000 0x205: 00000000 + ff330005 0x206: ff330005 + 00080082 0x207: 00080082 + 00080082 0x208: 00080082 + 00080082 0x209: 00080082 + 00080082 0x20a: 00080082 + 00000000 0x20b: 00000000 + 40000000 0x20c: 40000000 + 00000000 0x20d: 00000000 + 00000000 0x218: 00000000 + 00ce7c18 0x219: 00ce7c18 + 00000000 0x21a: 00000000 + 1fff401f 0x21b: 1fff401f + 00000000 0x21c: 00000000 + 73ff40f0 0x21d: 73ff40f0 + 00000000 0x21e: 00000000 + ffffffe3 0x21f: ffffffe3 + 00000000 0x220: 00000000 + 73ff407f 0x221: 73ff407f + 00000000 0x222: 00000000 + ffffffe3 0x223: ffffffe3 + 00000000 0x224: 00000000 + ecdb807f 0x225: ecdb807f + 00000000 0x226: 00000000 + bb36f3f6 0x227: bb36f3f6 + 00000000 0x228: 00000000 + 00001cfd 0x229: 00001cfd + 00000000 0x22a: 00000000 + 00000000 0x22b: 00000000 + 00000000 0x22c: 00000000 + 00000000 0x22d: 00000000 + 00000000 0x22e: 00000000 + 00000000 0x22f: 00000000 + 00000000 0x230: 00000000 + 00000000 0x231: 00000000 + 00000000 0x232: 00000000 + 00000000 0x233: 00000000 + 00000000 0x234: 00000000 + 00000000 0x235: 00000000 + 00000000 0x236: 00000000 + 00000000 0x237: 00000000 + 00000000 0x238: 00000000 + 00000000 0x239: 00000000 + 00000000 0x23a: 00000000 + 00000000 0x23b: 00000000 + 00000000 0x23c: 00000000 + 00000000 0x23d: 00000000 + 1a357e31 RBBM_PERFCTR_CP_0_LO: 0x1a357e31 + 80405044 RBBM_PERFCTR_CP_0_HI: 0x80405044 + 0731fe39 RBBM_PERFCTR_CP_1_LO: 0x731fe39 + 00011001 RBBM_PERFCTR_CP_1_HI: 0x11001 + 07337e41 RBBM_PERFCTR_CP_2_LO: 0x7337e41 + 85001004 RBBM_PERFCTR_CP_2_HI: 0x85001004 + 0b317e49 RBBM_PERFCTR_CP_3_LO: 0xb317e49 + 40000000 RBBM_PERFCTR_CP_3_HI: 0x40000000 + 07317e95 RBBM_PERFCTR_CP_4_LO: 0x7317e95 + 00800008 RBBM_PERFCTR_CP_4_HI: 0x800008 + 07317e59 RBBM_PERFCTR_CP_5_LO: 0x7317e59 + 04000000 RBBM_PERFCTR_CP_5_HI: 0x4000000 + 8771808b RBBM_PERFCTR_CP_6_LO: 0x8771808b + 00009000 RBBM_PERFCTR_CP_6_HI: 0x9000 + 0b31826b RBBM_PERFCTR_CP_7_LO: 0xb31826b + 00000000 RBBM_PERFCTR_CP_7_HI: 0 + 07b28675 RBBM_PERFCTR_CP_8_LO: 0x7b28675 + 00020080 RBBM_PERFCTR_CP_8_HI: 0x20080 + 0731be99 RBBM_PERFCTR_CP_9_LO: 0x731be99 + 00000000 RBBM_PERFCTR_CP_9_HI: 0 + 17317e83 RBBM_PERFCTR_CP_10_LO: 0x17317e83 + 008c0004 RBBM_PERFCTR_CP_10_HI: 0x8c0004 + 0bd182c9 RBBM_PERFCTR_CP_11_LO: 0xbd182c9 + 00800000 RBBM_PERFCTR_CP_11_HI: 0x800000 + 07318491 RBBM_PERFCTR_CP_12_LO: 0x7318491 + 00000000 RBBM_PERFCTR_CP_12_HI: 0 + 17317ed9 RBBM_PERFCTR_CP_13_LO: 0x17317ed9 + 00000020 RBBM_PERFCTR_CP_13_HI: 0x20 + 073180a3 RBBM_PERFCTR_RBBM_0_LO: 0x73180a3 + 00010044 RBBM_PERFCTR_RBBM_0_HI: 0x10044 + 07317eab RBBM_PERFCTR_RBBM_1_LO: 0x7317eab + 01008000 RBBM_PERFCTR_RBBM_1_HI: 0x1008000 + 4731a6b3 RBBM_PERFCTR_RBBM_2_LO: 0x4731a6b3 + 00000000 RBBM_PERFCTR_RBBM_2_HI: 0 + 0731febb RBBM_PERFCTR_RBBM_3_LO: 0x731febb + 00000000 RBBM_PERFCTR_RBBM_3_HI: 0 + 010011b6 RBBM_PERFCTR_PC_0_LO: 0x10011b6 + 00000080 RBBM_PERFCTR_PC_0_HI: 0x80 + 00000f96 RBBM_PERFCTR_PC_1_LO: 0xf96 + 50000000 RBBM_PERFCTR_PC_1_HI: 0x50000000 + 40041f96 RBBM_PERFCTR_PC_2_LO: 0x40041f96 + 20040800 RBBM_PERFCTR_PC_2_HI: 0x20040800 + 00000f96 RBBM_PERFCTR_PC_3_LO: 0xf96 + 01008004 RBBM_PERFCTR_PC_3_HI: 0x1008004 + 00021016 RBBM_PERFCTR_PC_4_LO: 0x21016 + 00000008 RBBM_PERFCTR_PC_4_HI: 0x8 + 00211096 RBBM_PERFCTR_PC_5_LO: 0x211096 + 04010000 RBBM_PERFCTR_PC_5_HI: 0x4010000 + 00300fb6 RBBM_PERFCTR_PC_6_LO: 0x300fb6 + 10001006 RBBM_PERFCTR_PC_6_HI: 0x10001006 + 00000f9a RBBM_PERFCTR_PC_7_LO: 0xf9a + 00200000 RBBM_PERFCTR_PC_7_HI: 0x200000 + 04020b81 RBBM_PERFCTR_VFD_0_LO: 0x4020b81 + 28046008 RBBM_PERFCTR_VFD_0_HI: 0x28046008 + 0020037d RBBM_PERFCTR_VFD_1_LO: 0x20037d + 00052000 RBBM_PERFCTR_VFD_1_HI: 0x52000 + 000003bd RBBM_PERFCTR_VFD_2_LO: 0x3bd + 00040000 RBBM_PERFCTR_VFD_2_HI: 0x40000 + 0800037d RBBM_PERFCTR_VFD_3_LO: 0x800037d + 00000000 RBBM_PERFCTR_VFD_3_HI: 0 + 0050469f RBBM_PERFCTR_VFD_4_LO: 0x50469f + 10000020 RBBM_PERFCTR_VFD_4_HI: 0x10000020 + 0000037d RBBM_PERFCTR_VFD_5_LO: 0x37d + 00000000 RBBM_PERFCTR_VFD_5_HI: 0 + 0000039f RBBM_PERFCTR_VFD_6_LO: 0x39f + 00000000 RBBM_PERFCTR_VFD_6_HI: 0 + 0000037e RBBM_PERFCTR_VFD_7_LO: 0x37e + 04804000 RBBM_PERFCTR_VFD_7_HI: 0x4804000 + 000011f4 RBBM_PERFCTR_HLSQ_0_LO: 0x11f4 + 40000140 RBBM_PERFCTR_HLSQ_0_HI: 0x40000140 + 000411f4 RBBM_PERFCTR_HLSQ_1_LO: 0x411f4 + 04020040 RBBM_PERFCTR_HLSQ_1_HI: 0x4020040 + 200092f4 RBBM_PERFCTR_HLSQ_2_LO: 0x200092f4 + 40800001 RBBM_PERFCTR_HLSQ_2_HI: 0x40800001 + 000019f4 RBBM_PERFCTR_HLSQ_3_LO: 0x19f4 + 00000000 RBBM_PERFCTR_HLSQ_3_HI: 0 + 00285216 RBBM_PERFCTR_HLSQ_4_LO: 0x285216 + 04009420 RBBM_PERFCTR_HLSQ_4_HI: 0x4009420 + 040031f4 RBBM_PERFCTR_HLSQ_5_LO: 0x40031f4 + 00000000 RBBM_PERFCTR_HLSQ_5_HI: 0 + 02402cb6 RBBM_PERFCTR_VPC_0_LO: 0x2402cb6 + 05000080 RBBM_PERFCTR_VPC_0_HI: 0x5000080 + 000005d6 RBBM_PERFCTR_VPC_1_LO: 0x5d6 + 00820000 RBBM_PERFCTR_VPC_1_HI: 0x820000 + 000004fa RBBM_PERFCTR_VPC_2_LO: 0x4fa + 00000000 RBBM_PERFCTR_VPC_2_HI: 0 + 00000cb6 RBBM_PERFCTR_VPC_3_LO: 0xcb6 + 40006000 RBBM_PERFCTR_VPC_3_HI: 0x40006000 + 0c1004b6 RBBM_PERFCTR_VPC_4_LO: 0xc1004b6 + 00000800 RBBM_PERFCTR_VPC_4_HI: 0x800 + 040204ba RBBM_PERFCTR_VPC_5_LO: 0x40204ba + 00000004 RBBM_PERFCTR_VPC_5_HI: 0x4 + 00000f36 RBBM_PERFCTR_CCU_0_LO: 0xf36 + 00000104 RBBM_PERFCTR_CCU_0_HI: 0x104 + 09000aa6 RBBM_PERFCTR_CCU_1_LO: 0x9000aa6 + 00000060 RBBM_PERFCTR_CCU_1_HI: 0x60 + 00010aca RBBM_PERFCTR_CCU_2_LO: 0x10aca + 01000400 RBBM_PERFCTR_CCU_2_HI: 0x1000400 + 00000ac8 RBBM_PERFCTR_CCU_3_LO: 0xac8 + 00004000 RBBM_PERFCTR_CCU_3_HI: 0x4000 + 80000aa6 RBBM_PERFCTR_CCU_4_LO: 0x80000aa6 + 04850000 RBBM_PERFCTR_CCU_4_HI: 0x4850000 + 00480168 RBBM_PERFCTR_TSE_0_LO: 0x480168 + 00000820 RBBM_PERFCTR_TSE_0_HI: 0x820 + 2021016c RBBM_PERFCTR_TSE_1_LO: 0x2021016c + 00880000 RBBM_PERFCTR_TSE_1_HI: 0x880000 + 00000968 RBBM_PERFCTR_TSE_2_LO: 0x968 + 00002000 RBBM_PERFCTR_TSE_2_HI: 0x2000 + 80102568 RBBM_PERFCTR_TSE_3_LO: 0x80102568 + 08004200 RBBM_PERFCTR_TSE_3_HI: 0x8004200 + 000000fb RBBM_PERFCTR_RAS_0_LO: 0xfb + 00004000 RBBM_PERFCTR_RAS_0_HI: 0x4000 + 020002ec RBBM_PERFCTR_RAS_1_LO: 0x20002ec + 10010004 RBBM_PERFCTR_RAS_1_HI: 0x10010004 + 001010eb RBBM_PERFCTR_RAS_2_LO: 0x1010eb + 20008010 RBBM_PERFCTR_RAS_2_HI: 0x20008010 + 4000016b RBBM_PERFCTR_RAS_3_LO: 0x4000016b + 01801000 RBBM_PERFCTR_RAS_3_HI: 0x1801000 + 040003fb RBBM_PERFCTR_UCHE_0_LO: 0x40003fb + 00000400 RBBM_PERFCTR_UCHE_0_HI: 0x400 + 00000a0c RBBM_PERFCTR_UCHE_1_LO: 0xa0c + 00007010 RBBM_PERFCTR_UCHE_1_HI: 0x7010 + 000021ff RBBM_PERFCTR_UCHE_2_LO: 0x21ff + 00000000 RBBM_PERFCTR_UCHE_2_HI: 0 + 0400021b RBBM_PERFCTR_UCHE_3_LO: 0x400021b + 00000020 RBBM_PERFCTR_UCHE_3_HI: 0x20 + 00108dfb RBBM_PERFCTR_UCHE_4_LO: 0x108dfb + 20040000 RBBM_PERFCTR_UCHE_4_HI: 0x20040000 + 105082fb RBBM_PERFCTR_UCHE_5_LO: 0x105082fb + 04010110 RBBM_PERFCTR_UCHE_5_HI: 0x4010110 + 000202fb RBBM_PERFCTR_UCHE_6_LO: 0x202fb + 00000810 RBBM_PERFCTR_UCHE_6_HI: 0x810 + 00c007fb RBBM_PERFCTR_UCHE_7_LO: 0xc007fb + 01000800 RBBM_PERFCTR_UCHE_7_HI: 0x1000800 + 480001fb RBBM_PERFCTR_UCHE_8_LO: 0x480001fb + 04000000 RBBM_PERFCTR_UCHE_8_HI: 0x4000000 + 000012fb RBBM_PERFCTR_UCHE_9_LO: 0x12fb + 00820428 RBBM_PERFCTR_UCHE_9_HI: 0x820428 + 0010021b RBBM_PERFCTR_UCHE_10_LO: 0x10021b + 08000000 RBBM_PERFCTR_UCHE_10_HI: 0x8000000 + 100001fb RBBM_PERFCTR_UCHE_11_LO: 0x100001fb + 08001044 RBBM_PERFCTR_UCHE_11_HI: 0x8001044 + 480803c0 RBBM_PERFCTR_TP_0_LO: 0x480803c0 + 404b0000 RBBM_PERFCTR_TP_0_HI: 0x404b0000 + 00002bd0 RBBM_PERFCTR_TP_1_LO: 0x2bd0 + 30000130 RBBM_PERFCTR_TP_1_HI: 0x30000130 + 000003c0 RBBM_PERFCTR_TP_2_LO: 0x3c0 + 00000080 RBBM_PERFCTR_TP_2_HI: 0x80 + 30200400 RBBM_PERFCTR_TP_3_LO: 0x30200400 + 80002080 RBBM_PERFCTR_TP_3_HI: 0x80002080 + 000003c0 RBBM_PERFCTR_TP_4_LO: 0x3c0 + 00a00000 RBBM_PERFCTR_TP_4_HI: 0xa00000 + 048003c0 RBBM_PERFCTR_TP_5_LO: 0x48003c0 + 42000900 RBBM_PERFCTR_TP_5_HI: 0x42000900 + 200003c0 RBBM_PERFCTR_TP_6_LO: 0x200003c0 + 00000000 RBBM_PERFCTR_TP_6_HI: 0 + 030003e1 RBBM_PERFCTR_TP_7_LO: 0x30003e1 + c01c0000 RBBM_PERFCTR_TP_7_HI: 0xc01c0000 + 020005c4 RBBM_PERFCTR_TP_8_LO: 0x20005c4 + 00000000 RBBM_PERFCTR_TP_8_HI: 0 + 0a0005c0 RBBM_PERFCTR_TP_9_LO: 0xa0005c0 + 10008188 RBBM_PERFCTR_TP_9_HI: 0x10008188 + 002813c4 RBBM_PERFCTR_TP_10_LO: 0x2813c4 + 00000200 RBBM_PERFCTR_TP_10_HI: 0x200 + 000007c0 RBBM_PERFCTR_TP_11_LO: 0x7c0 + 00000802 RBBM_PERFCTR_TP_11_HI: 0x802 + 028415c0 RBBM_PERFCTR_SP_0_LO: 0x28415c0 + 00121000 RBBM_PERFCTR_SP_0_HI: 0x121000 + 000411bc RBBM_PERFCTR_SP_1_LO: 0x411bc + 00010020 RBBM_PERFCTR_SP_1_HI: 0x10020 + 400631b8 RBBM_PERFCTR_SP_2_LO: 0x400631b8 + 00000800 RBBM_PERFCTR_SP_2_HI: 0x800 + 000811c8 RBBM_PERFCTR_SP_3_LO: 0x811c8 + 00010040 RBBM_PERFCTR_SP_3_HI: 0x10040 + 000011f8 RBBM_PERFCTR_SP_4_LO: 0x11f8 + 18000000 RBBM_PERFCTR_SP_4_HI: 0x18000000 + 002051c0 RBBM_PERFCTR_SP_5_LO: 0x2051c0 + 00800106 RBBM_PERFCTR_SP_5_HI: 0x800106 + 004011b8 RBBM_PERFCTR_SP_6_LO: 0x4011b8 + 40400000 RBBM_PERFCTR_SP_6_HI: 0x40400000 + 200031b8 RBBM_PERFCTR_SP_7_LO: 0x200031b8 + 41040100 RBBM_PERFCTR_SP_7_HI: 0x41040100 + 001011bc RBBM_PERFCTR_SP_8_LO: 0x1011bc + 00000000 RBBM_PERFCTR_SP_8_HI: 0 + 204011bc RBBM_PERFCTR_SP_9_LO: 0x204011bc + 00000001 RBBM_PERFCTR_SP_9_HI: 0x1 + 040011b8 RBBM_PERFCTR_SP_10_LO: 0x40011b8 + 02000000 RBBM_PERFCTR_SP_10_HI: 0x2000000 + 340012b8 RBBM_PERFCTR_SP_11_LO: 0x340012b8 + 004000c0 RBBM_PERFCTR_SP_11_HI: 0x4000c0 + c00015b8 RBBM_PERFCTR_SP_12_LO: 0xc00015b8 + 00800040 RBBM_PERFCTR_SP_12_HI: 0x800040 + 003041b9 RBBM_PERFCTR_SP_13_LO: 0x3041b9 + 00000000 RBBM_PERFCTR_SP_13_HI: 0 + 000019bc RBBM_PERFCTR_SP_14_LO: 0x19bc + 00080000 RBBM_PERFCTR_SP_14_HI: 0x80000 + 400051b9 RBBM_PERFCTR_SP_15_LO: 0x400051b9 + 10000900 RBBM_PERFCTR_SP_15_HI: 0x10000900 + 002011b8 RBBM_PERFCTR_SP_16_LO: 0x2011b8 + 00000000 RBBM_PERFCTR_SP_16_HI: 0 + 000092c0 RBBM_PERFCTR_SP_17_LO: 0x92c0 + 00000020 RBBM_PERFCTR_SP_17_HI: 0x20 + 000012b8 RBBM_PERFCTR_SP_18_LO: 0x12b8 + 00900020 RBBM_PERFCTR_SP_18_HI: 0x900020 + 000811c0 RBBM_PERFCTR_SP_19_LO: 0x811c0 + 129001a0 RBBM_PERFCTR_SP_19_HI: 0x129001a0 + 000011b8 RBBM_PERFCTR_SP_20_LO: 0x11b8 + 80000002 RBBM_PERFCTR_SP_20_HI: 0x80000002 + 800011b8 RBBM_PERFCTR_SP_21_LO: 0x800011b8 + 08000000 RBBM_PERFCTR_SP_21_HI: 0x8000000 + 000011b8 RBBM_PERFCTR_SP_22_LO: 0x11b8 + 2000a000 RBBM_PERFCTR_SP_22_HI: 0x2000a000 + 044011c0 RBBM_PERFCTR_SP_23_LO: 0x44011c0 + 84090000 RBBM_PERFCTR_SP_23_HI: 0x84090000 + 00104984 RBBM_PERFCTR_RB_0_LO: 0x104984 + 40000000 RBBM_PERFCTR_RB_0_HI: 0x40000000 + 00040b04 RBBM_PERFCTR_RB_1_LO: 0x40b04 + 00200470 RBBM_PERFCTR_RB_1_HI: 0x200470 + 40000984 RBBM_PERFCTR_RB_2_LO: 0x40000984 + 00820400 RBBM_PERFCTR_RB_2_HI: 0x820400 + 00000986 RBBM_PERFCTR_RB_3_LO: 0x986 + 10000000 RBBM_PERFCTR_RB_3_HI: 0x10000000 + 00001d84 RBBM_PERFCTR_RB_4_LO: 0x1d84 + 00000801 RBBM_PERFCTR_RB_4_HI: 0x801 + 01040b04 RBBM_PERFCTR_RB_5_LO: 0x1040b04 + 08002000 RBBM_PERFCTR_RB_5_HI: 0x8002000 + 00000984 RBBM_PERFCTR_RB_6_LO: 0x984 + 00000000 RBBM_PERFCTR_RB_6_HI: 0 + 0000198c RBBM_PERFCTR_RB_7_LO: 0x198c + 0000000c RBBM_PERFCTR_RB_7_HI: 0xc + 20000233 RBBM_PERFCTR_VSC_0_LO: 0x20000233 + 20000000 RBBM_PERFCTR_VSC_0_HI: 0x20000000 + 00000333 RBBM_PERFCTR_VSC_1_LO: 0x333 + 30d00100 RBBM_PERFCTR_VSC_1_HI: 0x30d00100 + 00000355 RBBM_PERFCTR_LRZ_0_LO: 0x355 + 00080004 RBBM_PERFCTR_LRZ_0_HI: 0x80004 + 10000357 RBBM_PERFCTR_LRZ_1_LO: 0x10000357 + 000005a0 RBBM_PERFCTR_LRZ_1_HI: 0x5a0 + 00000353 RBBM_PERFCTR_LRZ_2_LO: 0x353 + 00000100 RBBM_PERFCTR_LRZ_2_HI: 0x100 + 04004357 RBBM_PERFCTR_LRZ_3_LO: 0x4004357 + 050c0000 RBBM_PERFCTR_LRZ_3_HI: 0x50c0000 + 00000010 RBBM_PERFCTR_CMP_0_LO: 0x10 + 08000000 RBBM_PERFCTR_CMP_0_HI: 0x8000000 + 05000204 RBBM_PERFCTR_CMP_1_LO: 0x5000204 + 40000220 RBBM_PERFCTR_CMP_1_HI: 0x40000220 + 00000000 RBBM_PERFCTR_CMP_2_LO: 0 + 00000400 RBBM_PERFCTR_CMP_2_HI: 0x400 + 00200000 RBBM_PERFCTR_CMP_3_LO: 0x200000 + 11014000 RBBM_PERFCTR_CMP_3_HI: 0x11014000 + 00000001 RBBM_PERFCTR_CNTL: 0x1 + 00000000 RBBM_PERFCTR_LOAD_VALUE_LO: 0 + 00000000 RBBM_PERFCTR_LOAD_VALUE_HI: 0 + 00000000 RBBM_PERFCTR_RBBM_SEL_0: 0 + 00000000 RBBM_PERFCTR_RBBM_SEL_1: 0 + 00000000 RBBM_PERFCTR_RBBM_SEL_2: 0 + 00000000 RBBM_PERFCTR_RBBM_SEL_3: 0 + 002f7fff RBBM_PERFCTR_GPU_BUSY_MASKED: 0x2f7fff + 00000000 0x50f: 00000000 + 00000000 0x511: 00000000 + 00000000 RBBM_ISDB_CNT: 0 + 80108000 RBBM_PRIMCTR_0_LO: 0x80108000 + 10044400 RBBM_PRIMCTR_0_HI: 0x10044400 + 48004008 RBBM_PRIMCTR_1_LO: 0x48004008 + 00010000 RBBM_PRIMCTR_1_HI: 0x10000 + 04100000 RBBM_PRIMCTR_2_LO: 0x4100000 + 401a3089 RBBM_PRIMCTR_2_HI: 0x401a3089 + 08240112 RBBM_PRIMCTR_3_LO: 0x8240112 + 01000408 RBBM_PRIMCTR_3_HI: 0x1000408 + 00005020 RBBM_PRIMCTR_4_LO: 0x5020 + 00024000 RBBM_PRIMCTR_4_HI: 0x24000 + 10001000 RBBM_PRIMCTR_5_LO: 0x10001000 + 80400000 RBBM_PRIMCTR_5_HI: 0x80400000 + 0006000a RBBM_PRIMCTR_6_LO: 0x6000a + 00040002 RBBM_PRIMCTR_6_HI: 0x40002 + 10008100 RBBM_PRIMCTR_7_LO: 0x10008100 + 24000000 RBBM_PRIMCTR_7_HI: 0x24000000 + 24420000 RBBM_PRIMCTR_8_LO: 0x24420000 + 10800000 RBBM_PRIMCTR_8_HI: 0x10800000 + 21030200 RBBM_PRIMCTR_9_LO: 0x21030200 + 0c000020 RBBM_PRIMCTR_9_HI: 0xc000020 + 80820000 RBBM_PRIMCTR_10_LO: 0x80820000 + 40000800 RBBM_PRIMCTR_10_HI: 0x40000800 + 00001000 CP_RB_BASE: 0x1000 + 00010000 CP_RB_BASE_HI: 0x10000 + 0000020c CP_RB_CNTL: 0x20c + 00000000 0x803: 00000000 + 00000000 CP_RB_RPTR_ADDR_LO: 0 + 00010000 CP_RB_RPTR_ADDR_HI: 0x10000 + 00000038 CP_RB_RPTR: 0x38 + 00000038 CP_RB_WPTR: 0x38 + 00000001 CP_SQE_CNTL: 0x1 + 00000000 0x810: 00000000 + 00000000 0x811: 00000000 + 00000004 CP_CP2GMU_STATUS: { 0x4 } + 80000000 0x813: 80000000 + 00000000 0x820: 00000000 + 00000000 CP_HW_FAULT: 0 + 00000000 CP_INTERRUPT_STATUS: 0 + 00000000 CP_PROTECT_STATUS: 0 + 00000707 0x826: 00000707 + 00000001 0x827: 00000001 + 00009000 CP_SQE_INSTR_BASE_LO: 0x9000 + 00010000 CP_SQE_INSTR_BASE_HI: 0x10000 + 00000000 0x832: 00000000 + 00000000 0x833: 00000000 + 00000000 CP_MISC_CNTL: 0 + 00000000 CP_CHICKEN_DBG: 0 + 00000001 CP_ADDR_MODE_CNTL: ADDR_64B + 00000000 CP_DBG_ECO_CNTL: 0 + 00000003 CP_PROTECT_CNTL: 0x3 + 01440600 CP_PROTECT[0].REG: { BASE_ADDR = 0x600 | MASK_LEN = 0x51 } + 8008ae50 CP_PROTECT[0x1].REG: { BASE_ADDR = 0xae50 | MASK_LEN = 0x2 | READ } + 804c9624 CP_PROTECT[0x2].REG: { BASE_ADDR = 0x9624 | MASK_LEN = 0x13 | READ } + 80208630 CP_PROTECT[0x3].REG: { BASE_ADDR = 0x8630 | MASK_LEN = 0x8 | READ } + 80049e70 CP_PROTECT[0x4].REG: { BASE_ADDR = 0x9e70 | MASK_LEN = 0x1 | READ } + 861c9e78 CP_PROTECT[0x5].REG: { BASE_ADDR = 0x9e78 | MASK_LEN = 0x187 | READ } + a040f000 CP_PROTECT[0x6].REG: { BASE_ADDR = 0xf000 | MASK_LEN = 0x810 | READ } + 000cfc00 CP_PROTECT[0x7].REG: { BASE_ADDR = 0xfc00 | MASK_LEN = 0x3 } + 8000050e CP_PROTECT[0x8].REG: { BASE_ADDR = 0x50e | MASK_LEN = 0 | READ } + 0000050f CP_PROTECT[0x9].REG: { BASE_ADDR = 0x50f | MASK_LEN = 0 } + 80000510 CP_PROTECT[0xa].REG: { BASE_ADDR = 0x510 | MASK_LEN = 0 | READ } + 13e40000 CP_PROTECT[0xb].REG: { BASE_ADDR = 0 | MASK_LEN = 0x4f9 } + 00280501 CP_PROTECT[0xc].REG: { BASE_ADDR = 0x501 | MASK_LEN = 0xa } + 01100511 CP_PROTECT[0xd].REG: { BASE_ADDR = 0x511 | MASK_LEN = 0x44 } + 80380e00 CP_PROTECT[0xe].REG: { BASE_ADDR = 0xe00 | MASK_LEN = 0xe | READ } + 80008e00 CP_PROTECT[0xf].REG: { BASE_ADDR = 0x8e00 | MASK_LEN = 0 | READ } + 803c8e50 CP_PROTECT[0x10].REG: { BASE_ADDR = 0x8e50 | MASK_LEN = 0xf | READ } + 8000be02 CP_PROTECT[0x11].REG: { BASE_ADDR = 0xbe02 | MASK_LEN = 0 | READ } + c7ccbe20 CP_PROTECT[0x12].REG: { BASE_ADDR = 0xbe20 | MASK_LEN = 0x11f3 | READ } + 82080800 CP_PROTECT[0x13].REG: { BASE_ADDR = 0x800 | MASK_LEN = 0x82 | READ } + 802008a0 CP_PROTECT[0x14].REG: { BASE_ADDR = 0x8a0 | MASK_LEN = 0x8 | READ } + 806408ab CP_PROTECT[0x15].REG: { BASE_ADDR = 0x8ab | MASK_LEN = 0x19 | READ } + 81340900 CP_PROTECT[0x16].REG: { BASE_ADDR = 0x900 | MASK_LEN = 0x4d | READ } + 81d8098d CP_PROTECT[0x17].REG: { BASE_ADDR = 0x98d | MASK_LEN = 0x76 | READ } + 00100980 CP_PROTECT[0x18].REG: { BASE_ADDR = 0x980 | MASK_LEN = 0x4 } + 8000a630 CP_PROTECT[0x19].REG: { BASE_ADDR = 0xa630 | MASK_LEN = 0 | READ } + 00000000 CP_PROTECT[0x1a].REG: { BASE_ADDR = 0 | MASK_LEN = 0 } + 00000000 CP_PROTECT[0x1b].REG: { BASE_ADDR = 0 | MASK_LEN = 0 } + 00000000 CP_PROTECT[0x1c].REG: { BASE_ADDR = 0 | MASK_LEN = 0 } + 00000000 CP_PROTECT[0x1d].REG: { BASE_ADDR = 0 | MASK_LEN = 0 } + 00000000 CP_PROTECT[0x1e].REG: { BASE_ADDR = 0 | MASK_LEN = 0 } + 00000000 CP_PROTECT[0x1f].REG: { BASE_ADDR = 0 | MASK_LEN = 0 } + 00000000 0x880: 00000000 + 00000000 0x881: 00000000 + 00000000 0x882: 00000000 + 00000000 CP_SCRATCH[0].REG: 0 + 00000000 CP_SCRATCH[0x1].REG: 0 + 00000000 CP_SCRATCH[0x2].REG: 0 + 00000000 CP_SCRATCH[0x3].REG: 0 + 00000000 CP_SCRATCH[0x4].REG: 0 + 00000000 CP_SCRATCH[0x5].REG: 0 + 00000000 CP_SCRATCH[0x6].REG: 0 + 00000002 CP_SCRATCH[0x7].REG: 2 + 00000000 CP_CONTEXT_SWITCH_CNTL: 0 + 00000000 CP_CONTEXT_SWITCH_SMMU_INFO_LO: 0 + 00000000 CP_CONTEXT_SWITCH_SMMU_INFO_HI: 0 + 00000000 CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO: 0 + 00000000 CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI: 0 + 00000000 CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO: 0 + 00000000 CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI: 0 + 00000000 CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO: 0 + 00000000 CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI: 0 + 00000000 0x8a9: 00000000 + 00000000 0x8aa: 00000000 + 00000000 0x8ab: 00000000 + 00000000 0x8c0: 00000000 + 8040362c CP_ROQ_THRESHOLDS_1: { RB_LO = 0xb0 | RB_HI = 0xd8 | IB1_START = 0x100 | IB2_START = 0x200 } + 010000c0 CP_ROQ_THRESHOLDS_2: { SDS_START = 0x300 | ROQ_SIZE = 0x400 } + 00000080 CP_MEM_POOL_SIZE: 0x80 + 00000000 0x8c4: 00000000 + 00000000 CP_PERFCTR_CP_SEL_0: 0 + 00000000 CP_PERFCTR_CP_SEL_1: 0 + 00000000 CP_PERFCTR_CP_SEL_2: 0 + 00000000 CP_PERFCTR_CP_SEL_3: 0 + 00000000 CP_PERFCTR_CP_SEL_4: 0 + 00000000 CP_PERFCTR_CP_SEL_5: 0 + 00000000 CP_PERFCTR_CP_SEL_6: 0 + 00000000 CP_PERFCTR_CP_SEL_7: 0 + 00000000 CP_PERFCTR_CP_SEL_8: 0 + 00000000 CP_PERFCTR_CP_SEL_9: 0 + 00000000 CP_PERFCTR_CP_SEL_10: 0 + 00000000 CP_PERFCTR_CP_SEL_11: 0 + 00000000 CP_PERFCTR_CP_SEL_12: 0 + 00000000 CP_PERFCTR_CP_SEL_13: 0 + 00000000 0x8f0: 00000000 + 00000000 0x8f1: 00000000 + 00000000 0x8f2: 00000000 + 00000000 0x8f3: 00000000 + 00011000 CP_CRASH_SCRIPT_BASE_LO: 0x11000 + 00010000 CP_CRASH_SCRIPT_BASE_HI: 0x10000 + 00000001 CP_CRASH_DUMP_CNTL: 0x1 + 00000001 CP_CRASH_DUMP_STATUS: 0x1 + 00000033 CP_SQE_STAT_ADDR: 0x33 + 00000000 CP_SQE_STAT_DATA: 0 + 00000000 CP_DRAW_STATE_ADDR: 0 + 00000000 CP_DRAW_STATE_DATA: 0 + 00000000 CP_ROQ_DBG_ADDR: 0 + 70c80008 CP_ROQ_DBG_DATA: 0x70c80008 + 00002060 CP_MEM_POOL_DBG_ADDR: 0x2060 + 00000007 CP_MEM_POOL_DBG_DATA: 0x7 + 00006000 CP_SQE_UCODE_DBG_ADDR: 0x6000 + 00000000 CP_SQE_UCODE_DBG_DATA: 0 + 00000000 CP_IB1_BASE: 0 + 00000001 CP_IB1_BASE_HI: 0x1 + 00000000 CP_IB1_REM_SIZE: 0 + 00000000 CP_IB2_BASE: 0 + 00000000 CP_IB2_BASE_HI: 0 + 00000000 CP_IB2_REM_SIZE: 0 + 00000000 CP_SDS_BASE: 0 + 00000000 CP_SDS_BASE_HI: 0 + 00000000 0x930: 00000000 + 0000c600 CP_BIN_SIZE_ADDRESS: 0xc600 + 00010000 CP_BIN_SIZE_ADDRESS_HI: 0x10000 + 00000000 0x933: 00000000 + 00000000 CP_BIN_DATA_ADDR: 0 + 00000000 CP_BIN_DATA_ADDR_HI: 0 + 00000000 0x936: 00000000 + 00800000 0x937: 00800000 + 00000000 0x938: 00000000 + 00400031 0x939: 00400031 + 010c0107 0x93a: 010c0107 + 02000200 0x93b: 02000200 + 03000300 0x93c: 03000300 + 00b000b0 0x93d: 00b000b0 + 00d800d8 0x93e: 00d800d8 + 0000007f 0x942: 0000007f + 0000000c 0x943: 0000000c + 00000000 0x944: 00000000 + 00000000 0x945: 00000000 + 00000000 0x946: 00000000 + 00000000 0x947: 00000000 + 000f0004 0x948: 000f0004 + 00060002 CP_CSQ_IB1_STAT: { REM = 0x6 | 0x2 } + 00000000 CP_CSQ_IB2_STAT: { REM = 0 } + 00000000 0x94b: 00000000 + 00000000 0x94c: 00000000 + 00000000 0x94d: 00000000 + 00305efe CP_ALWAYS_ON_COUNTER_LO: 0x305efe + 00000000 CP_ALWAYS_ON_COUNTER_HI: 0 + 00225162 0x982: 00225162 + 00000000 0x983: 00000000 + 00000000 0x984: 00000000 + 00000001 CP_AHB_CNTL: 0x1 + 00000000 0x98e: 00000000 + 00000000 0x98f: 00000000 + 00000000 0x990: 00000000 + 00000000 0x991: 00000000 + 00000000 0x992: 00000000 + 00000000 0x993: 00000000 + 00000000 0x994: 00000000 + 00000000 0x995: 00000000 + 00000000 0x996: 00000000 + 00000000 0x998: 00000000 + 00000000 0x999: 00000000 + 00000000 0x99a: 00000000 + 00000000 0x99b: 00000000 + 00000000 0x99c: 00000000 + 00000000 0x99d: 00000000 + 00000000 0x99e: 00000000 + 00000000 0x9a0: 00000000 + 00000000 0x9a1: 00000000 + 00000000 0x9a2: 00000000 + 00000000 0x9a3: 00000000 + 00000000 0x9a4: 00000000 + 00000000 0x9a5: 00000000 + 00000000 0x9a6: 00000000 + 300026a0 0x9a8: 300026a0 + 02029804 0x9a9: 02029804 + 02027800 0x9aa: 02027800 + 0202b808 0x9ab: 0202b808 + 02024c40 0x9ac: 02024c40 + 02021804 0x9ad: 02021804 + 02023820 0x9ae: 02023820 + 00000000 0x9b0: 00000000 + 00000000 0x9b1: 00000000 + 42497500 0x9c2: 42497500 + 023c13c1 0x9c3: 023c13c1 + 02383383 0x9c4: 02383383 + 023a13a1 0x9c5: 023a13a1 + 023b13b1 0x9c6: 023b13b1 + 02393393 0x9c7: 02393393 + 01365365 0x9c8: 01365365 + 00000000 CP_APERTURE_CNTL_HOST: 0 + 00000000 0xa01: 00000000 + 00000000 0xa02: 00000000 + 00000000 CP_APERTURE_CNTL_CD: 0 + 00000000 0xc00: 00000000 + 00000001 VSC_ADDR_MODE_CNTL: ADDR_64B + 00000101 VSC_BIN_SIZE: { WIDTH = 32 | HEIGHT = 16 } + 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0 + 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0 + 00000000 VSC_BIN_COUNT: { NX = 0 | NY = 0 } + 00000000 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x1].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x2].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x3].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x4].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x5].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x6].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x7].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x8].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x9].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0xa].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0xb].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0xc].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0xd].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0xe].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0xf].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x10].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x11].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x12].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x13].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x14].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x15].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x16].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x17].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x18].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x19].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x1a].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x1b].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x1c].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x1d].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x1e].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x1f].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PRIM_STRM_ADDRESS_LO: 0 + 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0 + 00000000 VSC_PRIM_STRM_PITCH: 0 + 00000000 VSC_PRIM_STRM_LIMIT: 0 + 00000000 VSC_DRAW_STRM_ADDRESS_LO: 0 + 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0 + 00000000 VSC_DRAW_STRM_PITCH: 0 + 00000000 VSC_DRAW_STRM_LIMIT: 0 + 00000000 VSC_STATE[0].REG: 0 + 00000000 VSC_STATE[0x1].REG: 0 + 00000000 VSC_STATE[0x2].REG: 0 + 00000000 VSC_STATE[0x3].REG: 0 + 00000000 VSC_STATE[0x4].REG: 0 + 00000000 VSC_STATE[0x5].REG: 0 + 00000000 VSC_STATE[0x6].REG: 0 + 00000000 VSC_STATE[0x7].REG: 0 + 00000000 VSC_STATE[0x8].REG: 0 + 00000000 VSC_STATE[0x9].REG: 0 + 00000000 VSC_STATE[0xa].REG: 0 + 00000000 VSC_STATE[0xb].REG: 0 + 00000000 VSC_STATE[0xc].REG: 0 + 00000000 VSC_STATE[0xd].REG: 0 + 00000000 VSC_STATE[0xe].REG: 0 + 00000000 VSC_STATE[0xf].REG: 0 + 00000000 VSC_STATE[0x10].REG: 0 + 00000000 VSC_STATE[0x11].REG: 0 + 00000000 VSC_STATE[0x12].REG: 0 + 00000000 VSC_STATE[0x13].REG: 0 + 00000000 VSC_STATE[0x14].REG: 0 + 00000000 VSC_STATE[0x15].REG: 0 + 00000000 VSC_STATE[0x16].REG: 0 + 00000000 VSC_STATE[0x17].REG: 0 + 00000000 VSC_STATE[0x18].REG: 0 + 00000000 VSC_STATE[0x19].REG: 0 + 00000000 VSC_STATE[0x1a].REG: 0 + 00000000 VSC_STATE[0x1b].REG: 0 + 00000000 VSC_STATE[0x1c].REG: 0 + 00000000 VSC_STATE[0x1d].REG: 0 + 00000000 VSC_STATE[0x1e].REG: 0 + 00000000 VSC_STATE[0x1f].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x1].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x2].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x3].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x4].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x5].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x6].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x7].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x8].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x9].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0xa].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0xb].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0xc].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0xd].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0xe].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0xf].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x10].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x11].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x12].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x13].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x14].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x15].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x16].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x17].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x18].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x19].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x1a].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x1b].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x1c].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x1d].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x1e].REG: 0 + 00000000 VSC_PRIM_STRM_SIZE[0x1f].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x1].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x2].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x3].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x4].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x5].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x6].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x7].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x8].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x9].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0xa].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0xb].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0xc].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0xd].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0xe].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0xf].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x10].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x11].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x12].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x13].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x14].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x15].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x16].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x17].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x18].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x19].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x1a].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x1b].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x1c].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x1d].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x1e].REG: 0 + 00000000 VSC_DRAW_STRM_SIZE[0x1f].REG: 0 + 00000000 0xc98: 00000000 + 00000000 0xc99: 00000000 + 00000000 0xc9a: 00000000 + 00000000 0xc9b: 00000000 + 00000000 0xc9c: 00000000 + 00000000 0xc9d: 00000000 + 00000000 0xc9e: 00000000 + 00000000 0xc9f: 00000000 + 00000000 0xca0: 00000000 + 00000000 0xca1: 00000000 + 00000000 0xca2: 00000000 + 00000000 0xca3: 00000000 + 00000000 0xca4: 00000000 + 00000000 0xca5: 00000000 + 00000000 0xca6: 00000000 + 00000000 0xca7: 00000000 + 00000000 0xca8: 00000000 + 00000000 0xca9: 00000000 + 00000000 0xcaa: 00000000 + 00000000 0xcab: 00000000 + 00000000 0xcac: 00000000 + 00000000 0xcad: 00000000 + 00000000 0xcae: 00000000 + 00000000 0xcaf: 00000000 + 00000000 0xcb0: 00000000 + 00000000 0xcb1: 00000000 + 00000000 0xcb2: 00000000 + 00000000 0xcb3: 00000000 + 00000000 0xcb4: 00000000 + 00000000 0xcb5: 00000000 + 00000000 0xcb6: 00000000 + 00000000 0xcb7: 00000000 + 00000000 0xcb8: 00000000 + 00000000 0xcb9: 00000000 + 00000000 0xcba: 00000000 + 00000000 0xcbb: 00000000 + 00000000 0xcbc: 00000000 + 00000000 0xcbd: 00000000 + 00000000 0xcbe: 00000000 + 00000000 0xcbf: 00000000 + 00000000 0xcc0: 00000000 + 00000000 0xcc1: 00000000 + 00000000 0xcc2: 00000000 + 00000000 0xcc3: 00000000 + 00000000 0xcc4: 00000000 + 00000000 0xcc5: 00000000 + 00000000 0xcc6: 00000000 + 00000000 0xcc7: 00000000 + 00000000 0xcc8: 00000000 + 00000000 0xcc9: 00000000 + 00000000 0xcca: 00000000 + 00000000 0xccb: 00000000 + 00000000 0xccc: 00000000 + 00000000 0xccd: 00000000 + 00000000 0xcce: 00000000 + 00000000 0xccf: 00000000 + 00000000 0xcd0: 00000000 + 00000000 0xcd1: 00000000 + 00000000 0xcd2: 00000000 + 00000000 0xcd3: 00000000 + 00000000 0xcd4: 00000000 + 00000000 0xcd5: 00000000 + 00000000 0xcd6: 00000000 + 00000000 0xcd7: 00000000 + 00000000 VSC_PERFCTR_VSC_SEL_0: 0 + 00000000 VSC_PERFCTR_VSC_SEL_1: 0 + 00000001 UCHE_ADDR_MODE_CNTL: ADDR_64B + 00400000 UCHE_MODE_CNTL: 0x400000 + 00000000 0xe02: 00000000 + 00000000 0xe03: 00000000 + 00000000 0xe04: 00000000 + ffffffc0 UCHE_WRITE_RANGE_MAX_LO: 0xffffffc0 + 0001ffff UCHE_WRITE_RANGE_MAX_HI: 0x1ffff + fffff000 UCHE_WRITE_THRU_BASE_LO: 0xfffff000 + 0001ffff UCHE_WRITE_THRU_BASE_HI: 0x1ffff + fffff000 UCHE_TRAP_BASE_LO: 0xfffff000 + 0001ffff UCHE_TRAP_BASE_HI: 0x1ffff + 00100000 UCHE_GMEM_RANGE_MIN_LO: 0x100000 + 00000000 UCHE_GMEM_RANGE_MIN_HI: 0 + 001ff000 UCHE_GMEM_RANGE_MAX_LO: 0x1ff000 + 00000000 UCHE_GMEM_RANGE_MAX_HI: 0 + 00000000 0xe10: 00000000 + 00000000 0xe11: 00000000 + 00000000 UCHE_UNKNOWN_0E12: 0 + 00000000 0xe13: 00000000 + 00000004 UCHE_CACHE_WAYS: 0x4 + 00000804 UCHE_FILTER_CNTL: 0x804 + 00000001 UCHE_CLIENT_PF: { PERFSEL = 0x1 } + 00000000 UCHE_PERFCTR_UCHE_SEL_0: 0 + 00000000 UCHE_PERFCTR_UCHE_SEL_1: 0 + 00000000 UCHE_PERFCTR_UCHE_SEL_2: 0 + 00000000 UCHE_PERFCTR_UCHE_SEL_3: 0 + 00000000 UCHE_PERFCTR_UCHE_SEL_4: 0 + 00000000 UCHE_PERFCTR_UCHE_SEL_5: 0 + 00000000 UCHE_PERFCTR_UCHE_SEL_6: 0 + 00000000 UCHE_PERFCTR_UCHE_SEL_7: 0 + 00000000 UCHE_PERFCTR_UCHE_SEL_8: 0 + 00000000 UCHE_PERFCTR_UCHE_SEL_9: 0 + 00000000 UCHE_PERFCTR_UCHE_SEL_10: 0 + 00000000 UCHE_PERFCTR_UCHE_SEL_11: 0 + 00000000 0xe28: 00000000 + 00000000 0xe29: 00000000 + 00000000 0xe2a: 00000000 + 00000000 0xe2b: 00000000 + 00000000 0xe30: 00000000 + 00000000 0xe31: 00000000 + 00000000 0xe32: 00000000 + 00000000 0xe38: 00000000 + 00000000 0xe39: 00000000 + 00000000 GRAS_UNKNOWN_8600: 0 + 00000001 GRAS_ADDR_MODE_CNTL: ADDR_64B + 00000000 GRAS_PERFCTR_TSE_SEL_0: 0 + 00000000 GRAS_PERFCTR_TSE_SEL_1: 0 + 00000000 GRAS_PERFCTR_TSE_SEL_2: 0 + 00000000 GRAS_PERFCTR_TSE_SEL_3: 0 + 00000000 GRAS_PERFCTR_RAS_SEL_0: 0 + 00000000 GRAS_PERFCTR_RAS_SEL_1: 0 + 00000000 GRAS_PERFCTR_RAS_SEL_2: 0 + 00000000 GRAS_PERFCTR_RAS_SEL_3: 0 + 00000000 GRAS_PERFCTR_LRZ_SEL_0: 0 + 00000000 GRAS_PERFCTR_LRZ_SEL_1: 0 + 00000000 GRAS_PERFCTR_LRZ_SEL_2: 0 + 00000000 GRAS_PERFCTR_LRZ_SEL_3: 0 + 00000000 0x8620: 00000000 + 00000000 0x8628: 00000000 + 00000000 0x8629: 00000000 + 00000000 0x862a: 00000000 + 00000000 0x862b: 00000000 + 00000000 0x8630: 00000000 + 3fff3fff 0x8631: 3fff3fff + 00000000 0x8632: 00000000 + 00000000 0x8633: 00000000 + 00000000 0x8634: 00000000 + 00000000 0x8635: 00000000 + 00000000 0x8636: 00000000 + 00000000 0x8637: 00000000 + 00000000 VPC_UNKNOWN_9600: 0 + 00000001 VPC_ADDR_MODE_CNTL: ADDR_64B + 00000000 VPC_UNKNOWN_9602: FALSE + 00000000 VPC_UNKNOWN_9603: 0 + 00000000 VPC_PERFCTR_VPC_SEL_0: 0 + 00000000 0x9624: 00000000 + 00000000 0x9625: 00000000 + 00000000 0x9626: 00000000 + 00000000 0x9627: 00000000 + 00000000 0x9628: 00000000 + 00000000 0x9629: 00000000 + 00000000 0x962a: 00000000 + 00000000 0x962b: 00000000 + 00000000 0x962c: 00000000 + 00000000 0x962d: 00000000 + 00000000 0x962e: 00000000 + 00000000 0x962f: 00000000 + 00000000 0x9630: 00000000 + 00000000 0x9631: 00000000 + 00000000 0x9632: 00000000 + 00000000 0x9633: 00000000 + 00000000 0x9634: 00000000 + 00000000 0x9635: 00000000 + 00000000 0x9636: 00000000 + 00000000 0x9637: 00000000 + 00180000 PC_DBG_ECO_CNTL: 0x180000 + 00000001 PC_ADDR_MODE_CNTL: ADDR_64B + 00000000 0x9e03: 00000000 + 00000000 0x9e04: 00000000 + 00000000 0x9e05: 00000000 + 00000000 0x9e06: 00000000 + 00000000 0x9e07: 00000000 + 00000000 PC_TESSFACTOR_ADDR_LO: 0 + 00000000 PC_TESSFACTOR_ADDR_HI: 0 + 00000001 0x9e0a: 00000001 + 00004080 0x9e0b: 00004080 + 00000000 0x9e0c: 00000000 + 00000003 0x9e0d: 00000003 + 00000000 0x9e0e: 00000000 + 00010000 PC_VSTREAM_CONTROL: { VSC_SIZE = 1 | VSC_N = 0 } + 00000000 PC_BIN_PRIM_STRM: 0 + 00000000 PC_BIN_PRIM_STRM+0x1: 0 + 00000000 PC_BIN_DRAW_STRM: 0 + 00000000 PC_BIN_DRAW_STRM+0x1: 0 + 00000000 0x9e16: 00000000 + 00000000 0x9e19: 00000000 + 00000000 0x9e1c: 00000000 + 00000000 0x9e20: 00000000 + 00000000 0x9e21: 00000000 + 00000000 0x9e22: 00000000 + 00000000 0x9e23: 00000000 + 00000000 0x9e30: 00000000 + 00000000 0x9e31: 00000000 + 00000000 PC_PERFCTR_PC_SEL_0: 0 + 00000000 0x9e70: 00000000 + 00000000 0x9e71: 00000000 + 00000000 PC_UNKNOWN_9E72: 0 + 00000002 0x9e78: 00000002 + 00000000 0x9e79: 00000000 + 00000000 0x9e80: 00000000 + 00000000 0x9e81: 00000000 + 00000000 0x9e82: 00000000 + 00000000 0x9e83: 00000000 + 00000000 0x9e84: 00000000 + 00000000 0x9e85: 00000000 + 00000000 0x9e86: 00000000 + 00000000 0x9e87: 00000000 + 00000000 0x9e88: 00000000 + 00000000 0x9e89: 00000000 + 00000000 0x9e8a: 00000000 + 00000000 0x9e8b: 00000000 + 00000000 0x9e8c: 00000000 + 00000000 0x9e8d: 00000000 + 00000021 0x9e8e: 00000021 + 00000044 0x9e8f: 00000044 + 00000000 0x9e90: 00000000 + 00000000 0x9e91: 00000000 + 00000000 0x9e92: 00000000 + 00000000 0x9e93: 00000000 + 00000000 0x9e94: 00000000 + 00000000 0x9e95: 00000000 + 00000000 0x9e96: 00000000 + 00000000 0x9e97: 00000000 + 00000000 0x9e98: 00000000 + 00000000 0x9e99: 00000000 + 00000000 0x9e9a: 00000000 + 00000000 0x9e9b: 00000000 + 00000000 0x9e9c: 00000000 + 00000000 0x9e9d: 00000000 + 00000000 0x9e9e: 00000000 + 00000000 0x9e9f: 00000000 + 00000000 0x9ea0: 00000000 + 00000000 0x9ea1: 00000000 + 00000000 0x9ea2: 00000000 + 00000000 0x9ea3: 00000000 + 00000000 0x9ea4: 00000000 + 00000000 0x9ea5: 00000000 + 00000000 0x9ea6: 00000000 + 00000000 0x9ea7: 00000000 + 00000000 0x9ea8: 00000000 + 00000000 0x9ea9: 00000000 + 00000000 0x9eaa: 00000000 + 00000000 0x9eab: 00000000 + 00000000 0x9eac: 00000000 + 00000000 0x9ead: 00000000 + 00000000 0x9eae: 00000000 + 00000001 0x9eaf: 00000001 + 00000000 0x9eb0: 00000000 + 00000000 0x9eb1: 00000000 + 00000000 0x9eb2: 00000000 + 00000000 0x9eb3: 00000000 + 00000000 0x9eb4: 00000000 + 00000000 0x9eb5: 00000000 + 00000000 0x9eb6: 00000000 + 00000000 0x9eb7: 00000000 + 00000000 0x9eb8: 00000000 + 00000000 0x9eb9: 00000000 + 00000000 0x9eba: 00000000 + 00000000 0x9ebb: 00000000 + 00000000 0x9ebc: 00000000 + 00000000 0x9ebd: 00000000 + 00000000 0x9ebe: 00000000 + 00000001 0x9ebf: 00000001 + 00000000 0x9ec0: 00000000 + 00000000 0x9ec1: 00000000 + 00000000 0x9ec2: 00000000 + 00000000 0x9ec3: 00000000 + 00000000 0x9ec4: 00000000 + 00000000 0x9ec5: 00000000 + 00000000 0x9ec6: 00000000 + 00000000 0x9ec7: 00000000 + 00000000 0x9ec8: 00000000 + 00000000 0x9ec9: 00000000 + 00000000 0x9eca: 00000000 + 00000000 0x9ecb: 00000000 + 00000000 0x9ecc: 00000000 + 00000000 0x9ecd: 00000000 + 00000000 0x9ece: 00000000 + 00000000 0x9ecf: 00000000 + 00000000 0x9ed0: 00000000 + 00000000 0x9ed1: 00000000 + 00000000 0x9ed2: 00000000 + 00000000 0x9ed3: 00000000 + 00000000 0x9ed4: 00000000 + 00000000 0x9ed5: 00000000 + 00000000 0x9ed6: 00000000 + 00000000 0x9ed7: 00000000 + 00000000 0x9ed8: 00000000 + 00000000 0x9ed9: 00000000 + 00000000 0x9eda: 00000000 + 00000000 0x9edb: 00000000 + 00000000 0x9edc: 00000000 + 00000000 0x9edd: 00000000 + 00000000 0x9ede: 00000000 + 00000000 0x9edf: 00000000 + 00000000 0x9ee0: 00000000 + 00000000 0x9ee1: 00000000 + 00000000 0x9ee2: 00000000 + 00000000 0x9ee3: 00000000 + 00000000 0x9ee4: 00000000 + 00000000 0x9ee5: 00000000 + 00000000 0x9ee6: 00000000 + 00000000 0x9ee7: 00000000 + 00000000 0x9ee8: 00000000 + 00000000 0x9ee9: 00000000 + 00000000 0x9eea: 00000000 + 00000000 0x9eeb: 00000000 + 00000000 0x9eec: 00000000 + 00000000 0x9eed: 00000000 + 00000000 0x9eee: 00000000 + 00000000 0x9eef: 00000000 + 00000000 0x9ef0: 00000000 + 00000000 0x9ef1: 00000000 + 00000000 0x9ef2: 00000000 + 00000000 0x9ef3: 00000000 + 00000000 0x9ef4: 00000000 + 00000000 0x9ef5: 00000000 + 00000000 0x9ef6: 00000000 + 00000000 0x9ef7: 00000000 + 00000000 0x9ef8: 00000000 + 00000000 0x9ef9: 00000000 + 00000000 0x9efa: 00000000 + 00000000 0x9efb: 00000000 + 00000000 0x9efc: 00000000 + 00000000 0x9efd: 00000000 + 00000000 0x9efe: 00000000 + 00000000 0x9eff: 00000000 + 00000000 0x9f00: 00000000 + 00000000 0x9f01: 00000000 + 00000000 0x9f02: 00000000 + 00000000 0x9f03: 00000000 + 00000000 0x9f04: 00000000 + 00000000 0x9f05: 00000000 + 00000000 0x9f06: 00000000 + 00000000 0x9f07: 00000000 + 00000000 0x9f08: 00000000 + 00000000 0x9f09: 00000000 + 00000000 0x9f0a: 00000000 + 00000000 0x9f0b: 00000000 + 00000000 0x9f0c: 00000000 + 00000000 0x9f0d: 00000000 + 00000000 0x9f0e: 00000000 + 00000000 0x9f0f: 00000000 + 00000000 0x9f10: 00000000 + 00000000 0x9f11: 00000000 + 00000000 0x9f12: 00000000 + 00000000 0x9f13: 00000000 + 00000000 0x9f14: 00000000 + 00000000 0x9f15: 00000000 + 00000000 0x9f16: 00000000 + 00000000 0x9f17: 00000000 + 00000000 0x9f18: 00000000 + 00000000 0x9f19: 00000000 + 00000000 0x9f1a: 00000000 + 00000000 0x9f1b: 00000000 + 00000000 0x9f1c: 00000000 + 00000000 0x9f1d: 00000000 + 00000000 0x9f1e: 00000000 + 00000000 0x9f1f: 00000000 + 00000000 0x9f20: 00000000 + 00000000 0x9f21: 00000000 + 00000000 0x9f22: 00000000 + 00000000 0x9f23: 00000000 + 00000000 0x9f24: 00000000 + 00000000 0x9f25: 00000000 + 00000000 0x9f26: 00000000 + 00000000 0x9f27: 00000000 + 00000000 0x9f28: 00000000 + 00000000 0x9f29: 00000000 + 00000000 0x9f2a: 00000000 + 00000000 0x9f2b: 00000000 + 00000000 0x9f2c: 00000000 + 00000000 0x9f2d: 00000000 + 00000000 0x9f2e: 00000000 + 00000000 0x9f2f: 00000000 + 00000000 0x9f30: 00000000 + 00000000 0x9f31: 00000000 + 00000000 0x9f32: 00000000 + 00000000 0x9f33: 00000000 + 00000000 0x9f34: 00000000 + 00000000 0x9f35: 00000000 + 00000000 0x9f36: 00000000 + 00000000 0x9f37: 00000000 + 00000000 0x9f38: 00000000 + 00000000 0x9f39: 00000000 + 00000000 0x9f3a: 00000000 + 00000000 0x9f3b: 00000000 + 00000000 0x9f3c: 00000000 + 00000000 0x9f3d: 00000000 + 00000000 0x9f3e: 00000000 + 00000011 0x9f3f: 00000011 + 00002625 0x9f40: 00002625 + 000020a5 0x9f41: 000020a5 + 00002306 0x9f42: 00002306 + 000020a6 0x9f43: 000020a6 + 00002327 0x9f44: 00002327 + 000020a7 0x9f45: 000020a7 + 00002084 0x9f46: 00002084 + 000020a4 0x9f47: 000020a4 + 00000036 0x9f48: 00000036 + 00000000 0x9f49: 00000000 + 00000000 0x9f4a: 00000000 + 00000000 0x9f4b: 00000000 + 00000000 0x9f4c: 00000000 + 00000000 0x9f4d: 00000000 + 00000000 0x9f4e: 00000000 + 00000000 0x9f4f: 00000000 + 00000000 0x9f50: 00000000 + 00000000 0x9f51: 00000000 + 00000000 0x9f52: 00000000 + 00000000 0x9f53: 00000000 + 00000000 0x9f54: 00000000 + 00000000 0x9f55: 00000000 + 00000000 0x9f56: 00000000 + 00000000 0x9f57: 00000000 + 00000000 0x9f58: 00000000 + 00000000 0x9f59: 00000000 + 00000000 0x9f5a: 00000000 + 00000000 0x9f5b: 00000000 + 00000000 0x9f5c: 00000000 + 00000000 0x9f5d: 00000000 + 00000000 0x9f5e: 00000000 + 00000000 0x9f5f: 00000000 + 00000000 0x9f60: 00000000 + 00000000 0x9f61: 00000000 + 00000000 0x9f62: 00000000 + 00000000 0x9f63: 00000000 + 00000000 0x9f64: 00000000 + 00000000 0x9f65: 00000000 + 00000000 0x9f66: 00000000 + 00000000 0x9f67: 00000000 + 00000000 0x9f68: 00000000 + 00000000 0x9f69: 00000000 + 00000000 0x9f6a: 00000000 + 00000000 0x9f6b: 00000000 + 00000000 0x9f6c: 00000000 + 00000000 0x9f6d: 00000000 + 00000000 0x9f6e: 00000000 + 00000000 0x9f6f: 00000000 + 00000000 0x9f70: 00000000 + 00000000 0x9f71: 00000000 + 00000000 0x9f72: 00000000 + 00000000 0x9f73: 00000000 + 00000000 0x9f74: 00000000 + 00000000 0x9f75: 00000000 + 00000000 0x9f76: 00000000 + 00000000 0x9f77: 00000000 + 00000000 0x9f78: 00000000 + 00000000 0x9f79: 00000000 + 00000000 0x9f7a: 00000000 + 00000000 0x9f7b: 00000000 + 00000000 0x9f7c: 00000000 + 00000000 0x9f7d: 00000000 + 00000000 0x9f7e: 00000000 + 00000000 0x9f7f: 00000000 + 00000000 0x9f80: 00000000 + 00000000 0x9f81: 00000000 + 00000000 0x9f82: 00000000 + 00000000 0x9f83: 00000000 + 00000000 0x9f84: 00000000 + 00000000 0x9f85: 00000000 + 00000000 0x9f86: 00000000 + 00000000 0x9f87: 00000000 + 00000000 0x9f88: 00000000 + 00000000 0x9f89: 00000000 + 00000000 0x9f8a: 00000000 + 00000000 0x9f8b: 00000000 + 00000000 0x9f8c: 00000000 + 00000000 0x9f8d: 00000000 + 00000000 0x9f8e: 00000000 + 00000000 0x9f8f: 00000000 + 00000000 0x9f90: 00000000 + 00000000 0x9f91: 00000000 + 00000000 0x9f92: 00000000 + 00000000 0x9f93: 00000000 + 00000000 0x9f94: 00000000 + 00000000 0x9f95: 00000000 + 00000000 0x9f96: 00000000 + 00000000 0x9f97: 00000000 + 00000000 0x9f98: 00000000 + 00000000 0x9f99: 00000000 + 00000000 0x9f9a: 00000000 + 00000000 0x9f9b: 00000000 + 00000000 0x9f9c: 00000000 + 00000000 0x9f9d: 00000000 + 00000000 0x9f9e: 00000000 + 00000000 0x9f9f: 00000000 + 00000000 0x9fa0: 00000000 + 00000000 0x9fa1: 00000000 + 00000000 0x9fa2: 00000000 + 00000000 0x9fa3: 00000000 + 00000000 0x9fa4: 00000000 + 00000000 0x9fa5: 00000000 + 00000000 0x9fa6: 00000000 + 00000000 0x9fa7: 00000000 + 00000000 0x9fa8: 00000000 + 00000000 0x9fa9: 00000000 + 00000000 0x9faa: 00000000 + 00000000 0x9fab: 00000000 + 00000000 0x9fac: 00000000 + 00000000 0x9fad: 00000000 + 00000000 0x9fae: 00000000 + 00000000 0x9faf: 00000000 + 00000000 0x9fb0: 00000000 + 00000000 0x9fb1: 00000000 + 00000000 0x9fb2: 00000000 + 00000000 0x9fb3: 00000000 + 00000000 0x9fb4: 00000000 + 00000000 0x9fb5: 00000000 + 00000000 0x9fb6: 00000000 + 00000000 0x9fb7: 00000000 + 00000000 0x9fb8: 00000000 + 00000000 0x9fb9: 00000000 + 00000000 0x9fba: 00000000 + 00000000 0x9fbb: 00000000 + 00000000 0x9fbc: 00000000 + 00000000 0x9fbd: 00000000 + 00000000 0x9fbe: 00000000 + 00000000 0x9fbf: 00000000 + 00000000 0x9fc0: 00000000 + 00000000 0x9fc1: 00000000 + 00000000 0x9fc2: 00000000 + 00000000 0x9fc3: 00000000 + 00000000 0x9fc4: 00000000 + 00000000 0x9fc5: 00000000 + 00000000 0x9fc6: 00000000 + 00000000 0x9fc7: 00000000 + 00000000 0x9fc8: 00000000 + 00000000 0x9fc9: 00000000 + 00000000 0x9fca: 00000000 + 00000000 0x9fcb: 00000000 + 00000000 0x9fcc: 00000000 + 00000000 0x9fcd: 00000000 + 00000000 0x9fce: 00000000 + 00000000 0x9fcf: 00000000 + 00000000 0x9fd0: 00000000 + 00000000 0x9fd1: 00000000 + 00000000 0x9fd2: 00000000 + 00000000 0x9fd3: 00000000 + 00000000 0x9fd4: 00000000 + 00000000 0x9fd5: 00000000 + 00000000 0x9fd6: 00000000 + 00000000 0x9fd7: 00000000 + 00000000 0x9fd8: 00000000 + 00000000 0x9fd9: 00000000 + 00000000 0x9fda: 00000000 + 00000000 0x9fdb: 00000000 + 00000000 0x9fdc: 00000000 + 00000000 0x9fdd: 00000000 + 00000000 0x9fde: 00000000 + 00000000 0x9fdf: 00000000 + 00000000 0x9fe0: 00000000 + 00000000 0x9fe1: 00000000 + 00000000 0x9fe2: 00000000 + 00000000 0x9fe3: 00000000 + 00000000 0x9fe4: 00000000 + 00000000 0x9fe5: 00000000 + 00000000 0x9fe6: 00000000 + 00000000 0x9fe7: 00000000 + 00000000 0x9fe8: 00000000 + 00000000 0x9fe9: 00000000 + 00000000 0x9fea: 00000000 + 00000000 0x9feb: 00000000 + 00000000 0x9fec: 00000000 + 00000000 0x9fed: 00000000 + 00000000 0x9fee: 00000000 + 00000000 0x9fef: 00000000 + 00000000 0x9ff0: 00000000 + 00000000 0x9ff1: 00000000 + 00000000 0x9ff2: 00000000 + 00000000 0x9ff3: 00000000 + 00000000 0x9ff4: 00000000 + 00000000 0x9ff5: 00000000 + 00000000 0x9ff6: 00000000 + 00000000 0x9ff7: 00000000 + 00000000 0x9ff8: 00000000 + 00000000 0x9ff9: 00000000 + 00000000 0x9ffa: 00000000 + 00000000 0x9ffb: 00000000 + 00000000 0x9ffc: 00000000 + 00000000 0x9ffd: 00000000 + 00000000 0x9ffe: 00000000 + 00000000 0x9fff: 00000000 + 00000000 0xa600: 00000000 + 00000001 VFD_ADDR_MODE_CNTL: ADDR_64B + 00000000 0xa603: 00000000 + 00000000 0xa60a: 00000000 + 00000000 VFD_PERFCTR_VFD_SEL_0: 0 + 00000000 VFD_PERFCTR_VFD_SEL_1: 0 + 00000000 VFD_PERFCTR_VFD_SEL_2: 0 + 00000000 VFD_PERFCTR_VFD_SEL_3: 0 + 00000000 VFD_PERFCTR_VFD_SEL_4: 0 + 00000000 VFD_PERFCTR_VFD_SEL_5: 0 + 00000000 VFD_PERFCTR_VFD_SEL_6: 0 + 00000000 VFD_PERFCTR_VFD_SEL_7: 0 + 00000000 0xa630: 00000000 + 00100000 RB_UNKNOWN_8E04: 0x100000 + 00000001 RB_ADDR_MODE_CNTL: ADDR_64B + 00000000 RB_CCU_CNTL: { OFFSET = 0 } + 00000004 RB_NC_MODE_CNTL: { LOWER_BIT = 2 | UPPER_BIT = 0 } + 00000000 RB_PERFCTR_RB_SEL_0: 0 + 00000000 RB_PERFCTR_RB_SEL_1: 0 + 00000000 RB_PERFCTR_RB_SEL_2: 0 + 00000000 RB_PERFCTR_RB_SEL_3: 0 + 00000000 RB_PERFCTR_RB_SEL_4: 0 + 00000000 RB_PERFCTR_RB_SEL_5: 0 + 00000000 RB_PERFCTR_RB_SEL_6: 0 + 00000000 RB_PERFCTR_RB_SEL_7: 0 + 00000000 RB_PERFCTR_CCU_SEL_0: 0 + 00000000 RB_PERFCTR_CCU_SEL_1: 0 + 00000000 RB_PERFCTR_CCU_SEL_2: 0 + 00000000 RB_PERFCTR_CCU_SEL_3: 0 + 00000000 RB_PERFCTR_CCU_SEL_4: 0 + 00000000 0x8e20: 00000000 + 00000000 0x8e21: 00000000 + 00000000 0x8e22: 00000000 + 00000000 0x8e23: 00000000 + 00000000 0x8e24: 00000000 + 00000000 0x8e25: 00000000 + 00000000 RB_UNKNOWN_8E28: 0 + 00000000 RB_PERFCTR_CMP_SEL_0: 0 + 00000000 RB_PERFCTR_CMP_SEL_1: 0 + 00000000 RB_PERFCTR_CMP_SEL_2: 0 + 00000000 RB_PERFCTR_CMP_SEL_3: 0 + 00000000 RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE: FALSE + 0006d000 RB_UNKNOWN_8E51: 0x6d000 + 00000000 0x8e52: 00000000 + 00000000 RB_UNKNOWN_8E01: 0 + 00000300 0x8e0c: 00000300 + 00000000 RB_RB_SUB_BLOCK_SEL_CNTL_HOST: 0 + 00000000 0x8e3c: 00000000 + 00000009 RB_RB_SUB_BLOCK_SEL_CNTL_CD: 0x9 + 00000009 0x8e3e: 00000009 + 00000000 0x8e40: 00000000 + 00000000 0x8e41: 00000000 + 00000000 0x8e42: 00000000 + 00000000 0x8e43: 00000000 + 00000000 0x8e53: 00000000 + 00000000 0x8e54: 00000000 + 00000000 0x8e55: 00000000 + 00000000 0x8e56: 00000000 + 00000000 0x8e5b: 00000000 + 00000000 0x8e5c: 00000000 + 00000000 0x8e5d: 00000000 + 00000000 0x8e5e: 00000000 + 00000000 0x8e5f: 00000000 + 00000000 0x8e70: 00000000 + 00000000 0x8e71: 00000000 + 00000000 0x8e72: 00000000 + 00000000 0x8e73: 00000000 + 00000000 0x8e74: 00000000 + 00000000 0x8e75: 00000000 + 00000000 0x8e76: 00000000 + 00000000 0x8e77: 00000000 + 00000000 HLSQ_UNKNOWN_BE00: 0 + 00000001 HLSQ_UNKNOWN_BE01: 0x1 + 00000004 HLSQ_UNKNOWN_BE04: 0x4 + 00000000 HLSQ_ADDR_MODE_CNTL: ADDR_32B + deadbeef 0xbe08: deadbeef + deadbeef 0xbe09: deadbeef + 00000000 HLSQ_PERFCTR_HLSQ_SEL_0: 0 + 00000000 HLSQ_PERFCTR_HLSQ_SEL_1: 0 + 00000000 HLSQ_PERFCTR_HLSQ_SEL_2: 0 + 00000000 HLSQ_PERFCTR_HLSQ_SEL_3: 0 + 00000000 HLSQ_PERFCTR_HLSQ_SEL_4: 0 + 00000000 HLSQ_PERFCTR_HLSQ_SEL_5: 0 + 00000000 0xbe20: 00000000 + 00000000 0xbe21: 00000000 + 00000000 0xbe22: 00000000 + 00000000 0xbe23: 00000000 + 00000000 SP_UNKNOWN_AE00: 0 + 00000001 SP_ADDR_MODE_CNTL: ADDR_64B + deadbeef SP_NC_MODE_CNTL: 0xdeadbeef + deadbeef SP_UNKNOWN_AE03: 0xdeadbeef + 00000004 SP_UNKNOWN_AE04: 0x4 + deadbeef 0xae0c: deadbeef + deadbeef SP_UNKNOWN_AE0F: 0xdeadbeef + 00000000 SP_PERFCTR_SP_SEL_0: 0 + 00000000 SP_PERFCTR_SP_SEL_1: 0 + 00000000 SP_PERFCTR_SP_SEL_2: 0 + 00000000 SP_PERFCTR_SP_SEL_3: 0 + 00000000 SP_PERFCTR_SP_SEL_4: 0 + 00000000 SP_PERFCTR_SP_SEL_5: 0 + 00000000 SP_PERFCTR_SP_SEL_6: 0 + 00000000 SP_PERFCTR_SP_SEL_7: 0 + 00000000 SP_PERFCTR_SP_SEL_8: 0 + 00000000 SP_PERFCTR_SP_SEL_9: 0 + 00000000 SP_PERFCTR_SP_SEL_10: 0 + 00000000 SP_PERFCTR_SP_SEL_11: 0 + deadbeef SP_PERFCTR_SP_SEL_12: 0xdeadbeef + deadbeef SP_PERFCTR_SP_SEL_13: 0xdeadbeef + deadbeef SP_PERFCTR_SP_SEL_14: 0xdeadbeef + deadbeef SP_PERFCTR_SP_SEL_15: 0xdeadbeef + 00000000 SP_PERFCTR_SP_SEL_16: 0 + 00000000 SP_PERFCTR_SP_SEL_17: 0 + 00000000 SP_PERFCTR_SP_SEL_18: 0 + 00000000 SP_PERFCTR_SP_SEL_19: 0 + deadbeef SP_PERFCTR_SP_SEL_20: 0xdeadbeef + deadbeef SP_PERFCTR_SP_SEL_21: 0xdeadbeef + deadbeef SP_PERFCTR_SP_SEL_22: 0xdeadbeef + deadbeef SP_PERFCTR_SP_SEL_23: 0xdeadbeef + deadbeef 0xae28: deadbeef + deadbeef 0xae29: deadbeef + deadbeef 0xae2a: deadbeef + deadbeef 0xae2b: deadbeef + deadbeef 0xae30: deadbeef + deadbeef 0xae31: deadbeef + deadbeef 0xae32: deadbeef + deadbeef 0xae35: deadbeef + deadbeef 0xae3a: deadbeef + deadbeef 0xae3b: deadbeef + deadbeef 0xae3c: deadbeef + deadbeef 0xae3d: deadbeef + deadbeef 0xae3e: deadbeef + deadbeef 0xae3f: deadbeef + deadbeef 0xae50: deadbeef + deadbeef 0xae51: deadbeef + deadbeef 0xae52: deadbeef + 00000000 SP_UNKNOWN_B600: 0 + 00000001 TPL1_ADDR_MODE_CNTL: ADDR_64B + 00000004 TPL1_NC_MODE_CNTL: 0x4 + 00000000 SP_UNKNOWN_B605: 0 + 00000000 TPL1_PERFCTR_TP_SEL_0: 0 + 00000000 TPL1_PERFCTR_TP_SEL_1: 0 + 00000000 TPL1_PERFCTR_TP_SEL_2: 0 + 00000000 TPL1_PERFCTR_TP_SEL_3: 0 + 00000000 TPL1_PERFCTR_TP_SEL_4: 0 + 00000000 TPL1_PERFCTR_TP_SEL_5: 0 + 00000000 TPL1_PERFCTR_TP_SEL_6: 0 + 00000000 TPL1_PERFCTR_TP_SEL_7: 0 + 00000000 TPL1_PERFCTR_TP_SEL_8: 0 + 00000000 TPL1_PERFCTR_TP_SEL_9: 0 + 00000000 TPL1_PERFCTR_TP_SEL_10: 0 + 00000000 TPL1_PERFCTR_TP_SEL_11: 0 + 00000000 0xb620: 00000000 + 00000000 0xb621: 00000000 + 00000000 0xb622: 00000000 + 00000000 0xb623: 00000000 +got rb_base=1000000001000 +IB1: 100000000, 6 +IB2: 0, 0 +found ring! +got cmdszdw=27 + opcode: CP_REG_TO_MEM (3e) (4 dwords) + { REG = 0x1f888 | CNT = 2 | 64B } + { DEST = 0x38 } + { DEST_HI = 0x10000 } + gpuaddr:0001000000000038 +0000000000000000: 0000: 703e8003 4009f888 00000038 00010000 + opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = PC_CCU_INVALIDATE_DEPTH } + event PC_CCU_INVALIDATE_DEPTH +0000000000000000: 0000: 70460001 00000018 + opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = PC_CCU_INVALIDATE_COLOR } + event PC_CCU_INVALIDATE_COLOR +0000000000000000: 0000: 70460001 00000019 + opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = RM6_BYPASS | MARKER = RM6_BYPASS } +0000000100000000: 0000: 70e50001 00000001 + opcode: CP_NOP (10) (1 dwords) +0000000100000008: 0000: 70108000 + opcode: CP_NOP (10) (1 dwords) +000000010000000c: 0000: 70108000 + opcode: CP_NOP (10) (1 dwords) +0000000100000010: 0000: 70108000 + opcode: CP_NOP (10) (1 dwords) +0000000100000014: 0000: 70108000 +bad type! deadd00d + opcode: CP_NOP (10) (1 dwords) +0000000100000020: 0000: 70108000 + opcode: CP_NOP (10) (1 dwords) +0000000100000024: 0000: 70108000 + opcode: CP_NOP (10) (1 dwords) +0000000100000028: 0000: 70108000 + opcode: CP_NOP (10) (1 dwords) +000000010000002c: 0000: 70108000 +0000000000000000: 0000: 70bf8003 00000000 00000001 0000000c + opcode: CP_REG_TO_MEM (3e) (4 dwords) + { REG = 0x400 | CNT = 2 | 64B } + { DEST = 0x30 } + { DEST_HI = 0x10000 } + gpuaddr:0001000000000030 +0000000000000000: 0000: 703e8003 40080400 00000030 00010000 + opcode: CP_REG_TO_MEM (3e) (4 dwords) + { REG = 0x1f888 | CNT = 2 | 64B } + { DEST = 0x40 } + { DEST_HI = 0x10000 } + gpuaddr:0001000000000040 +0000000000000000: 0000: 703e8003 4009f888 00000040 00010000 + opcode: CP_EVENT_WRITE (46) (5 dwords) + { EVENT = CACHE_FLUSH_TS | IRQ } + { ADDR_0_LO = 0x4 } + { ADDR_0_HI = 0x10000 } + { 3 = 0x1 } + event (null) +0000000000000000: 0000: 70460004 80000004 00000004 00010000 00000001 +registers-gmu: + 00000001 GMU_ICACHE_CONFIG: 0x1 + 00000001 GMU_DCACHE_CONFIG: 0x1 + 00000000 0x4c02: 00000000 + 00000000 0x4c03: 00000000 + 00000000 0x4c04: 00000000 + 00000000 0x4c05: 00000000 + 00000000 0x4c06: 00000000 + 00000000 0x4c07: 00000000 + 00000000 0x4c10: 00000000 + 00000000 0x4c11: 00000000 + 00000000 0x4c12: 00000000 + 00000004 0x4d00: 00000004 + 00000000 0x4d07: 00000000 + 00000000 0x4d08: 00000000 + 00000000 0x4d09: 00000000 + 00000000 0x4d0a: 00000000 + 00000000 GMU_CM3_SYSRESET: 0 + 00000002 GMU_CM3_BOOT_CONFIG: 0x2 + 00000000 0x5002: 00000000 + ffffffff 0x5003: ffffffff + ffffffff 0x5004: ffffffff + 0003c07f 0x5007: 0003c07f + 00000000 0x5008: 00000000 + 00001404 0x500b: 00001404 + 00000000 0x500c: 00000000 + 0003bfe0 0x500f: 0003bfe0 + 00000000 0x5010: 00000000 + 00000000 0x5011: 00000000 + 00000000 0x5012: 00000000 + 00000003 0x5013: 00000003 + 00000000 0x5014: 00000000 + 001f0003 0x5015: 001f0003 + 00927c00 0x5016: 00927c00 + 01b77400 0x5017: 01b77400 + 00000000 0x5018: 00000000 + 00000000 0x5019: 00000000 + 00000001 GMU_CM3_FW_BUSY: 0x1 + 00000000 0x501b: 00000000 + babeface GMU_CM3_FW_INIT_RESULT: 0xbabeface + 00000000 0x5024: 00000000 + 00000000 0x5025: 00000000 + 00000000 0x5026: 00000000 + 80ffffff 0x5027: 80ffffff + 00000000 0x5028: 00000000 + 00000000 0x5029: 00000000 + 00000000 0x502a: 00000000 + 00004052 GMU_CM3_CFG: 0x4052 + 01000148 0x502e: 01000148 + 00000000 0x502f: 00000000 + 0002a000 0x5030: 0002a000 + 00000001 GMU_CX_GMU_POWER_COUNTER_ENABLE: 0x1 + 00000020 GMU_CX_GMU_POWER_COUNTER_SELECT_0: 0x20 + 00000000 GMU_CX_GMU_POWER_COUNTER_SELECT_1: 0 + 00000000 0x5043: 00000000 + 0014da28 GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L: 0x14da28 + 00000000 GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H: 0 + 002239e6 GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L: 0x2239e6 + 00000000 GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H: 0 + 002239f8 GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L: 0x2239f8 + 00000000 GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H: 0 + 00223a0a GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L: 0x223a0a + 00000000 GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H: 0 + 00223a1d GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L: 0x223a1d + 00000000 GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H: 0 + 00223a2f GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L: 0x223a2f + 00000000 GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H: 0 + 00000000 0x5050: 00000000 + 00000000 0x5051: 00000000 + 00000000 0x5052: 00000000 + 00000000 0x5053: 00000000 + 00000000 0x5087: 00000000 + 0022e30b GMU_ALWAYS_ON_COUNTER_L: 0x22e30b + 00000000 GMU_ALWAYS_ON_COUNTER_H: 0 + 00000000 0x50a0: 00000000 + 00000000 0x50a1: 00000000 + 00000000 0x50a2: 00000000 + 00000000 0x50a4: 00000000 + 00000000 0x50a5: 00000000 + 00000000 0x50a6: 00000000 + 00000000 0x50a7: 00000000 + 00000000 0x50a8: 00000000 + 00000000 0x50a9: 00000000 + 00000000 0x50aa: 00000000 + 00000000 0x50ab: 00000000 + 00000000 0x50ac: 00000000 + 00000000 0x50ad: 00000000 + 00000000 0x50ae: 00000000 + 00000000 0x50af: 00000000 + 09c40400 GMU_PWR_COL_INTER_FRAME_CTRL: { NUM_PASS_SKIPS = 0x1 | MIN_PASS_LENGTH = 0x2710 } + 000a2710 GMU_PWR_COL_INTER_FRAME_HYST: 0xa2710 + 000a2710 GMU_PWR_COL_SPTPRAC_HYST: 0xa2710 + 00000001 GMU_GMU_PWR_COL_KEEPALIVE: 0x1 + 00000028 GMU_SPTPRAC_PWR_CLK_STATUS: { SPTPRAC_GDSC_POWER_ON | GMU_UP_POWER_STATE } + 000001f0 GMU_GPU_NAP_CTRL: { SID = 0x1f } + 00000f11 GMU_RPMH_CTRL: { RPMH_INTERFACE_ENABLE | LLC_VOTE_ENABLE | DDR_VOTE_ENABLE | MX_VOTE_ENABLE | CX_VOTE_ENABLE | GFX_VOTE_ENABLE } + 00000000 GMU_RPMH_HYST_CTRL: 0 + 00000000 0x50ea: 00000000 + 00000000 0x50eb: 00000000 + 00000000 GPU_GMU_CX_GMU_RPMH_POWER_STATE: 0 + 60009000 GPU_GMU_CX_GMU_PWR_COL_CP_MSG: 0x60009000 + 00000000 GPU_GMU_CX_GMU_PWR_COL_CP_RESP: 0 + 001f0000 0x5102: 001f0000 + e8765432 0x5103: e8765432 + 00000000 0x5140: 00000000 + 00000000 0x5142: 00000000 + 00000000 0x5143: 00000000 + 00000000 0x5144: 00000000 + 00000000 0x514c: 00000000 + 00000000 GPU_GMU_CX_GMU_PWR_THRESHOLD: 0 + 00000000 0x514f: 00000000 + 0000ffff 0x5150: 0000ffff + 00000000 0x5151: 00000000 + 00000000 0x5154: 00000000 + 00000000 GMU_LLM_GLM_SLEEP_CTRL: 0 + 00000002 GMU_LLM_GLM_SLEEP_STATUS: 0x2 + 00000000 GMU_ISENSE_CTRL: 0 + 00000008 0x5162: 00000008 + 00000000 0x5164: 00000000 + 00000005 0x5165: 00000005 + 00000001 GMU_HFI_CTRL_STATUS: 0x1 + 00000000 GMU_HFI_VERSION_INFO: 0 + 06030200 GMU_HFI_SFR_ADDR: 0x6030200 + 00000000 GMU_HFI_MMAP_ADDR: 0 + 00000001 GMU_HFI_QTBL_INFO: 0x1 + 60005000 GMU_HFI_QTBL_ADDR: 0x60005000 + 00000001 GMU_HFI_CTRL_INIT: 0x1 + 00000000 GMU_GMU2HOST_INTR_SET: 0 + 00000000 GMU_GMU2HOST_INTR_CLR: 0 + 00000000 GMU_GMU2HOST_INTR_INFO: { 0 } + ff7fffff GMU_GMU2HOST_INTR_MASK: 0xff7fffff + 00000000 GMU_HOST2GMU_INTR_SET: 0 + 00000000 GMU_HOST2GMU_INTR_CLR: 0 + 00000000 GMU_HOST2GMU_INTR_RAW_INFO: 0 + 00000001 GMU_HOST2GMU_INTR_EN_0: 0x1 + 000000fe GMU_HOST2GMU_INTR_EN_1: 0xfe + 00ff0000 GMU_HOST2GMU_INTR_EN_2: 0xff0000 + ff000000 GMU_HOST2GMU_INTR_EN_3: 0xff000000 + 00000000 GMU_HOST2GMU_INTR_INFO_0: 0 + 00000000 GMU_HOST2GMU_INTR_INFO_1: 0 + 00000000 GMU_HOST2GMU_INTR_INFO_2: 0 + 00000000 GMU_HOST2GMU_INTR_INFO_3: 0 + 10010000 0x51c0: 10010000 + babeface 0x51c5: babeface + 00000000 GMU_GENERAL_1: 0 + 00000000 0x51c7: 00000000 + 00000000 0x51c8: 00000000 + 60005018 0x51c9: 60005018 + 60005048 0x51ca: 60005048 + 00000000 0x51cb: 00000000 + 00000001 GMU_GENERAL_7: 0x1 + 00000000 0x51e0: 00000000 + 00000000 0x51e1: 00000000 + 0000000a 0x51e2: 0000000a + 00000000 GMU_BOOT_KMD_LM_HANDSHAKE: 0 + 00000000 0x5200: 00000000 + 00000000 0x5201: 00000000 + 00000000 0x8c8c: 00000000 + 00000000 0x8d01: 00000000 + 00000013 0x8d02: 00000013 + 0000000f 0x8f40: 0000000f + 00000000 0x8f41: 00000000 + 00000000 0x8f42: 00000000 + 00000007 0x8f44: 00000007 + 00000000 0x8f45: 00000000 + 00000001 0x8f46: 00000001 + 00000000 0x8f47: 00000000 + 00010108 0x8f4c: 00010108 + 00050000 0x8f4d: 00050000 + 40000000 0x8f4e: 40000000 + 00000000 0x8f4f: 00000000 + 00000000 0x8f50: 00000000 + 00010108 0x8f51: 00010108 + 0005005c 0x8f52: 0005005c + 40000000 0x8f53: 40000000 + 00000000 0x8f54: 00000000 + 00000000 0x8f55: 00000000 + 00010108 0x8f56: 00010108 + 0005000c 0x8f57: 0005000c + 40000000 0x8f58: 40000000 + 00000000 0x8f59: 00000000 + 00000000 0x8f5a: 00000000 + 00010108 0x8f5b: 00010108 + 00050000 0x8f5c: 00050000 + 00000000 0x8f5d: 00000000 + 00000000 0x8f5e: 00000000 + 00000000 0x8f5f: 00000000 + 00010108 0x8f60: 00010108 + 00050000 0x8f61: 00050000 + 00000000 0x8f62: 00000000 + 00000000 0x8f63: 00000000 + 00000000 0x8f64: 00000000 + 00010108 0x8f65: 00010108 + 00050000 0x8f66: 00050000 + 00000000 0x8f67: 00000000 + 00000000 0x8f68: 00000000 + 00000000 0x8f69: 00000000 + 00010108 0x8f6a: 00010108 + 00050000 0x8f6b: 00050000 + 00000000 0x8f6c: 00000000 + 00000000 0x8f6d: 00000000 + 00000000 0x8f6e: 00000000 + 00010108 0x8f6f: 00010108 + 00050000 0x8f70: 00050000 + 00000000 0x8f71: 00000000 + 00000000 0x8f72: 00000000 + 00000000 0x8f73: 00000000 + 00010108 0x8f74: 00010108 + 00000000 0x8f75: 00000000 + 00000000 0x8f76: 00000000 + 00000000 0x8f77: 00000000 + 00000000 0x8f78: 00000000 + 00010108 0x8f79: 00010108 + 00000000 0x8f7a: 00000000 + 00000000 0x8f7b: 00000000 + 00000000 0x8f7c: 00000000 + 00000000 0x8f7d: 00000000 + 00010108 0x8f7e: 00010108 + 00000000 0x8f7f: 00000000 + 00000000 0x8f80: 00000000 + 00000000 0x8f81: 00000000 + 00000000 0x8f82: 00000000 + 00010108 0x8f83: 00010108 + 00000000 0x8f84: 00000000 + 00000000 0x8f85: 00000000 + 00000000 0x8f86: 00000000 + 00000000 0x8f87: 00000000 + 00000005 0x8fec: 00000005 + 00000000 0x8fed: 00000000 + 00000001 0x8fee: 00000001 + 00000000 0x8fef: 00000000 + 00010108 0x8ff4: 00010108 + 00050034 0x8ff5: 00050034 + 40000000 0x8ff6: 40000000 + 00000000 0x8ff7: 00000000 + 00000000 0x8ff8: 00000000 + 00010108 0x8ff9: 00010108 + 0005007c 0x8ffa: 0005007c + 00000000 0x8ffb: 00000000 + 00000000 0x8ffc: 00000000 + 00000000 0x8ffd: 00000000 + 00010108 0x8ffe: 00010108 + 0005004c 0x8fff: 0005004c + 40000000 0x9000: 40000000 + 00000000 0x9001: 00000000 + 00000000 0x9002: 00000000 + 00010108 0x9003: 00010108 + 00050000 0x9004: 00050000 + 00000000 0x9005: 00000000 + 00000000 0x9006: 00000000 + 00000000 0x9007: 00000000 + 00010108 0x9008: 00010108 + 00050000 0x9009: 00050000 + 00000000 0x900a: 00000000 + 00000000 0x900b: 00000000 + 00000000 0x900c: 00000000 + 00010108 0x900d: 00010108 + 00050000 0x900e: 00050000 + 00000000 0x900f: 00000000 + 00000000 0x9010: 00000000 + 00000000 0x9011: 00000000 + 00010108 0x9012: 00010108 + 00030050 0x9013: 00030050 + 00000000 0x9014: 00000000 + 00000000 0x9015: 00000000 + 00000000 0x9016: 00000000 + 00010108 0x9017: 00010108 + 00030010 0x9018: 00030010 + 00000000 0x9019: 00000000 + 00000000 0x901a: 00000000 + 00000000 0x901b: 00000000 + 00010108 0x901c: 00010108 + 00030000 0x901d: 00030000 + 00000000 0x901e: 00000000 + 00000000 0x901f: 00000000 + 00000000 0x9020: 00000000 + 00010108 0x9021: 00010108 + 00000000 0x9022: 00000000 + 00000000 0x9023: 00000000 + 00000000 0x9024: 00000000 + 00000000 0x9025: 00000000 + 00010108 0x9026: 00010108 + 00000000 0x9027: 00000000 + 00000000 0x9028: 00000000 + 00000000 0x9029: 00000000 + 00000000 0x902a: 00000000 + 00010108 0x902b: 00010108 + 00000000 0x902c: 00000000 + 00000000 0x902d: 00000000 + 00000000 0x902e: 00000000 + 00000000 0x902f: 00000000 + 00000007 0x9094: 00000007 + 00000000 0x9095: 00000000 + 00000001 0x9096: 00000001 + 00000000 0x9097: 00000000 + 00010108 0x909c: 00010108 + 00050000 0x909d: 00050000 + 00000000 0x909e: 00000000 + 00000000 0x909f: 00000000 + 00000000 0x90a0: 00000000 + 00010108 0x90a1: 00010108 + 0005005c 0x90a2: 0005005c + 00000000 0x90a3: 00000000 + 00000000 0x90a4: 00000000 + 00000000 0x90a5: 00000000 + 00010108 0x90a6: 00010108 + 0005000c 0x90a7: 0005000c + 00000000 0x90a8: 00000000 + 00000000 0x90a9: 00000000 + 00000000 0x90aa: 00000000 + 00010108 0x90ab: 00010108 + 00050000 0x90ac: 00050000 + 00000000 0x90ad: 00000000 + 00000000 0x90ae: 00000000 + 00000000 0x90af: 00000000 + 00010108 0x90b0: 00010108 + 00050000 0x90b1: 00050000 + 00000000 0x90b2: 00000000 + 00000000 0x90b3: 00000000 + 00000000 0x90b4: 00000000 + 00010108 0x90b5: 00010108 + 00050000 0x90b6: 00050000 + 00000000 0x90b7: 00000000 + 00000000 0x90b8: 00000000 + 00000000 0x90b9: 00000000 + 00010108 0x90ba: 00010108 + 00050000 0x90bb: 00050000 + 00000000 0x90bc: 00000000 + 00000000 0x90bd: 00000000 + 00000000 0x90be: 00000000 + 00010108 0x90bf: 00010108 + 00050000 0x90c0: 00050000 + 00000000 0x90c1: 00000000 + 00000000 0x90c2: 00000000 + 00000000 0x90c3: 00000000 + 00010108 0x90c4: 00010108 + 00000000 0x90c5: 00000000 + 00000000 0x90c6: 00000000 + 00000000 0x90c7: 00000000 + 00000000 0x90c8: 00000000 + 00010108 0x90c9: 00010108 + 00000000 0x90ca: 00000000 + 00000000 0x90cb: 00000000 + 00000000 0x90cc: 00000000 + 00000000 0x90cd: 00000000 + 00010108 0x90ce: 00010108 + 00000000 0x90cf: 00000000 + 00000000 0x90d0: 00000000 + 00000000 0x90d1: 00000000 + 00000000 0x90d2: 00000000 + 00010108 0x90d3: 00010108 + 00000000 0x90d4: 00000000 + 00000000 0x90d5: 00000000 + 00000000 0x90d6: 00000000 + 00000000 0x90d7: 00000000 + 00000005 0x913c: 00000005 + 01010000 0x913d: 01010000 + 00000001 0x913e: 00000001 + 000000c0 0x913f: 000000c0 + 00010108 0x9144: 00010108 + 00050034 0x9145: 00050034 + 60000001 0x9146: 60000001 + 00000000 0x9147: 00000000 + 00000000 0x9148: 00000000 + 00010108 0x9149: 00010108 + 0005007c 0x914a: 0005007c + 20000001 0x914b: 20000001 + 00000000 0x914c: 00000000 + 00000000 0x914d: 00000000 + 00010108 0x914e: 00010108 + 0005004c 0x914f: 0005004c + 60000001 0x9150: 60000001 + 00000000 0x9151: 00000000 + 00000000 0x9152: 00000000 + 00010108 0x9153: 00010108 + 00050000 0x9154: 00050000 + 00000000 0x9155: 00000000 + 00000000 0x9156: 00000000 + 00000000 0x9157: 00000000 + 00010108 0x9158: 00010108 + 00050000 0x9159: 00050000 + 00000000 0x915a: 00000000 + 00000000 0x915b: 00000000 + 00000000 0x915c: 00000000 + 00010108 0x915d: 00010108 + 00050000 0x915e: 00050000 + 00000000 0x915f: 00000000 + 00000000 0x9160: 00000000 + 00000000 0x9161: 00000000 + 00010108 0x9162: 00010108 + 00030050 0x9163: 00030050 + 00000009 0x9164: 00000009 + 00010101 0x9165: 00010101 + 00000000 0x9166: 00000000 + 00010108 0x9167: 00010108 + 00030010 0x9168: 00030010 + 00000004 0x9169: 00000004 + 00010101 0x916a: 00010101 + 00000000 0x916b: 00000000 + 00010108 0x916c: 00010108 + 00030000 0x916d: 00030000 + 00000004 0x916e: 00000004 + 00000000 0x916f: 00000000 + 00000000 0x9170: 00000000 + 00010108 0x9171: 00010108 + 00000000 0x9172: 00000000 + 00000000 0x9173: 00000000 + 00000000 0x9174: 00000000 + 00000000 0x9175: 00000000 + 00010108 0x9176: 00010108 + 00000000 0x9177: 00000000 + 00000000 0x9178: 00000000 + 00000000 0x9179: 00000000 + 00000000 0x917a: 00000000 + 00010108 0x917b: 00010108 + 00000000 0x917c: 00000000 + 00000000 0x917d: 00000000 + 00000000 0x917e: 00000000 + 00000000 0x917f: 00000000 + 00000000 0x9300: 00000000 + 00000000 0x9301: 00000000 + 00000000 0x9302: 00000000 + 00000000 GMU_AO_INTERRUPT_EN: 0 + 00000000 GMU_AO_HOST_INTERRUPT_CLR: 0 + 00000000 GMU_AO_HOST_INTERRUPT_STATUS: { 0 } + 00000016 GMU_AO_HOST_INTERRUPT_MASK: 0x16 + 00000000 GMU_RSCC_CONTROL_REQ: 0 + 00000000 GMU_RSCC_CONTROL_ACK: 0 + 00000000 GPU_GMU_AO_GMU_CGC_MODE_CNTL: 0 + 00000000 GPU_GMU_AO_GMU_CGC_DELAY_CNTL: 0 + 00000000 GPU_GMU_AO_GMU_CGC_HYST_CNTL: 0 + 71800004 GPU_GMU_AO_GPU_CX_BUSY_STATUS: { GPUBUSYIGNAHB | 0x71000004 } + 00000092 GPU_GMU_AO_GPU_CX_BUSY_STATUS2: 0x92 + ff000000 GPU_GMU_AO_GPU_CX_BUSY_MASK: 0xff000000 + 00000000 0x930f: 00000000 + 00000000 GMU_AO_AHB_FENCE_CTRL: 0 + 802800a0 GMU_AHB_FENCE_RANGE_0: 0x802800a0 + 00000000 GMU_AHB_FENCE_RANGE_1: 0 + 00000000 GMU_AHB_FENCE_STATUS: 0 + 00000000 0x9314: 00000000 + 00000001 GMU_RBBM_INT_UNMASKED_STATUS: 0x1 + 00000000 GMU_AO_SPARE_CNTL: 0 + 00000000 0x9400: 00000000 + d1000005 0x9800: d1000005 + 00000049 0x9801: 00000049 + 00000000 0x9802: 00000000 + 00000007 0x9803: 00000007 + 00004804 0x9804: 00004804 + 20485699 0x9805: 20485699 + 00002067 0x9806: 00002067 + 40000000 0x9807: 40000000 + 00000000 0x9808: 00000000 + 00000000 0x9809: 00000000 + 00000000 0x980a: 00000000 + 00000001 0x980b: 00000001 + 00000007 0x980c: 00000007 + 00000000 0x980d: 00000000 + 0000f555 0x980e: 0000f555 + 00000000 0x980f: 00000000 + 00000000 0x9810: 00000000 + 00000000 0x9811: 00000000 + 00000000 0x9812: 00000000 + 00800004 0x9840: 00800004 + 0000001a 0x9841: 0000001a + 00000000 0x9842: 00000000 + 00000001 0x9843: 00000001 + 00004805 0x9844: 00004805 + 20485699 0x9845: 20485699 + 00002067 0x9846: 00002067 + 40000000 0x9847: 40000000 + 00000000 0x9848: 00000000 + 00000000 0x9849: 00000000 + 00000000 0x984a: 00000000 + 00000000 0x984b: 00000000 + 00000001 0x984c: 00000001 + 00000000 0x984d: 00000000 + 00000aab 0x984e: 00000aab + 00000000 0x984f: 00000000 + 00000000 0x9850: 00000000 + 00000000 0x9851: 00000000 + 00000000 0x9852: 00000000 + 00000000 0x9c00: 00000000 + 00000000 0x9c01: 00000000 + 00000000 0x9c02: 00000000 + f8222800 GPU_CC_GX_GDSCR: 0xf8222800 + 00070400 0x9c04: 00070400 + 00000002 0x9c07: 00000002 + 00000101 0x9c08: 00000101 + 00800000 0x9c09: 00800000 + 00015011 0x9c0a: 00015011 + 00000000 0x9c0b: 00000000 + 00004221 0x9c15: 00004221 + 80000000 0x9c16: 80000000 + 80000000 0x9c17: 80000000 + 00000001 0x9c18: 00000001 + 80000000 0x9c19: 80000000 + 00000000 0x9c1a: 00000000 + f8282000 0x9c1b: f8282000 + 00070400 0x9c1c: 00070400 + 00000001 0x9c1e: 00000001 + 00000000 0x9c1f: 00000000 + 80000000 0x9c20: 80000000 + 80000000 0x9c21: 80000000 + 80000000 0x9c22: 80000000 + 00000000 0x9c23: 00000000 + 00000000 0x9c24: 00000000 + 80000000 0x9c25: 80000000 + 00004ff1 0x9c26: 00004ff1 + 00000001 0x9c27: 00000001 + 00000000 0x9c28: 00000000 + 00000000 0x9c29: 00000000 + 00000000 0x9c2a: 00000000 + 00000000 0x9c2b: 00000000 + 00000000 0x9c2c: 00000000 + 00000000 0x9c2d: 00000000 + 00000001 0x9c3c: 00000001 + 00000000 0x9c3d: 00000000 + 00000001 0x9c3f: 00000001 + 80000000 0x9c40: 80000000 + 00000001 0x9c42: 00000001 + 80000000 0x9c43: 80000000 + 00000000 0x9c44: 00000000 + 00000003 0x9c45: 00000003 + 00000001 0x9c46: 00000001 + 00000000 0x9c47: 00000000 + 00000000 0x9c48: 00000000 + 00000602 0x9c49: 00000602 + 00000000 0x9c58: 00000000 + 00000001 0x9c59: 00000001 + 00000001 0x9c5a: 00000001 + 00000000 0x9d40: 00000000 + 00000000 0x9d41: 00000000 + 003c0000 GPU_CC_GX_DOMAIN_MISC: 0x3c0000 + 00000000 0x9d43: 00000000 + 00000001 0x9d44: 00000001 + 0000003f 0x9d45: 0000003f + 00000000 0x9d46: 00000000 + 0000003f 0x9d47: 0000003f + 00000000 0x9d48: 00000000 + 0000003f 0x9d49: 0000003f + 00000000 0x9d4a: 00000000 + 000001ff 0x9d4b: 000001ff + 000001ff 0x9d4c: 000001ff + 00000000 0x9d4d: 00000000 + 00000001 0x9d4e: 00000001 + 00000000 0x9d4f: 00000000 + 80001fe0 0x9d50: 80001fe0 + 00000000 0x9d51: 00000000 + 00000000 0x9d52: 00000000 + 00000001 0x9d53: 00000001 + 00000000 0x9d54: 00000000 + 00000001 0x9d55: 00000001 + 00000000 0x9d56: 00000000 + 00000003 0x9d57: 00000003 + 00000003 0x9d58: 00000003 + 00000000 0x9d59: 00000000 + 00000000 0x9d5a: 00000000 + 00000000 0x9d5b: 00000000 + 00000000 0x9d5c: 00000000 + 00000000 0x9d5d: 00000000 + 40000001 0x9d5e: 40000001 + 00000000 0xa000: 00000000 + 80000001 0xa001: 80000001 + 00000000 0xa002: 00000000 + 00000000 0xa400: 00000000 + 80000001 0xa401: 80000001 + 00000000 0xa402: 00000000 + 00000000 0xac00: 00000000 + 80000001 0xac01: 80000001 + 00000000 0xac02: 00000000 + 00000000 0xb000: 00000000 + 80000001 0xb001: 80000001 + 00000000 0xb002: 00000000 + 00000000 0xb400: 00000000 + 80000001 0xb401: 80000001 + 00000000 0xb402: 00000000 + 00000000 0xb800: 00000000 + 00000000 0xb801: 00000000 + 00000000 0xb802: 00000000 + 10010000 0xbc00: 10010000 + 00000000 0xbc01: 00000000 + 00000000 0xbc02: 00000000 + 00000000 0xbc03: 00000000 + 00000000 0xbc04: 00000000 + 00000000 0xbc05: 00000000 + 00000000 0xbc06: 00000000 + 00000000 0xbc07: 00000000 + 00000000 0xbc08: 00000000 + 00000000 0xbc09: 00000000 + 00000000 0xbc0a: 00000000 + 00000000 0xbc0b: 00000000 + 02c3da78 0xbc0c: 02c3da78 + 00000000 0xbc0d: 00000000 + 037d2002 0xbc0e: 037d2002 + 00000000 0xbc0f: 00000000 + 00000000 0xbc10: 00000000 + 00000001 0xbc11: 00000001 + 00000000 0xbc12: 00000000 + 00000000 0xbc13: 00000000 + 00000000 0xbc14: 00000000 + 00000000 0xbc15: 00000000 + 00000000 0xbc16: 00000000 + 00000000 0xbc20: 00000000 + 00000000 0xbc21: 00000000 + 00000800 0xbc22: 00000800 + 00000000 0xbc23: 00000000 + 00000000 0xbc24: 00000000 + 00000000 0xbc25: 00000000 + 10010000 0xbc26: 10010000 + 00000000 0xbc27: 00000000 + 00000000 0: 00000000 + 00000000 0x10: 00000000 + 00000000 0x11: 00000000 + 00000000 0x12: 00000000 + 00000000 0x13: 00000000 + 00000000 0x16: 00000000 + 00000000 0x18: 00000000 + 00000000 0x19: 00000000 + 00000000 0x1a: 00000000 + 00000000 0x1b: 00000000 + 00000000 0x1e: 00000000 + 00000000 0x20: 00000000 + 00000000 0x21: 00000000 + 00000000 0x22: 00000000 + 00000000 0x23: 00000000 + 00000000 0x26: 00000000 + 00000000 0x28: 00000000 + 00000000 0x29: 00000000 + 00000000 0x2a: 00000000 + 00000000 0x2b: 00000000 + 00000000 0x2e: 00000000 + 00000000 0x30: 00000000 + 00000000 0x31: 00000000 + 00000000 0x32: 00000000 + 00000000 0x33: 00000000 + 00000000 0x36: 00000000 + 00000000 0x38: 00000000 + 00000000 0x39: 00000000 + 00000000 0x3a: 00000000 + 00000000 0x3b: 00000000 + 00000000 0x3e: 00000000 + 00000000 0x40: 00000000 + 00000000 0x41: 00000000 + 00000000 0x42: 00000000 + 00000000 0x43: 00000000 + 00000000 0x46: 00000000 + 00008ff1 GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL: 0x8ff1 + 00778000 GMU_GX_SPTPRAC_POWER_CONTROL: 0x778000 + 00000020 RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0: 0x20 + 00000044 RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0: 0x44 + 00000044 0x84: 00000044 + 00000000 RSCC_OVERRIDE_START_ADDR: 0 + 00000000 RSCC_SEQ_BUSY_DRV0: 0 + 00000000 0x102: 00000000 + 00000000 0x103: 00000000 + 00000000 0x104: 00000000 + 00000000 0x105: 00000000 + 00000000 0x106: 00000000 + 00000000 0x107: 00000000 + 00000000 0x108: 00000000 + 00000000 0x109: 00000000 + 00000000 0x10a: 00000000 + 00000000 0x10b: 00000000 + 00000000 0x10c: 00000000 + 00000000 0x10d: 00000000 + 00000000 0x10e: 00000000 + 00000000 0x10f: 00000000 + 00000000 0x110: 00000000 + 00000000 0x111: 00000000 + 00000000 0x112: 00000000 + 00000000 0x113: 00000000 + 00000000 0x114: 00000000 + 00000000 0x115: 00000000 + 00000000 0x116: 00000000 + 00000000 0x117: 00000000 + 00000000 0x118: 00000000 + 00000000 0x119: 00000000 + 00000000 0x11a: 00000000 + 00000000 0x11b: 00000000 + 00000000 0x11c: 00000000 + 00000000 0x11d: 00000000 + 00000000 0x11e: 00000000 + 00000000 0x11f: 00000000 + 00000000 0x120: 00000000 + 00000000 0x121: 00000000 + 00000000 0x122: 00000000 + 00000000 0x123: 00000000 + 00000000 0x124: 00000000 + 00000000 0x125: 00000000 + 00000000 0x126: 00000000 + 00000000 0x127: 00000000 + 00000000 0x128: 00000000 + 00000000 0x129: 00000000 + 00000000 0x12a: 00000000 + 00000000 0x12b: 00000000 + 00000000 0x140: 00000000 +indexed-registers: + - regs-name: CP_SEQ_STAT + dwords: 51 + PC: 00c5 + $01: deadd00d $11: 00000000 + $02: 00000001 $12: 00000001 + $03: 00000000 $13: 00000008 + $04: 00000001 $14: 00000000 + $05: 00000000 $15: 00000000 + $06: 00000004 $16: 00000000 + $07: 00000101 $17: 00000000 + $08: 00000001 $18: 00000000 + $09: 00010000 $19: 00000000 + $0a: 000121fd $1a: 00000000 + $0b: 53c06000 $1b: 00000384 + $0c: 00003c45 $1c: 00000000 + $0d: 53c06000 $1d: 70000000 + $0e: 00000002 $1e: 00000000 + $0f: 0000002b $1f: 00000000 + $10: 00000000 $20: 00000000 + ----------------------------------------------- + 204 (0xcc) bytes + 000000: 000000c5 deadd00d 00000001 00000000 |................| + 000010: 00000001 00000000 00000004 00000101 |................| + 000020: 00000001 00010000 000121fd 53c06000 |.........!...`.S| + 000030: 00003c45 53c06000 00000002 0000002b |E<...`.S....+...| + 000040: 00000000 00000000 00000001 00000008 |................| + 000050: 00000000 00000000 00000000 00000000 |................| + 000060: 00000000 00000000 00000000 00000384 |................| + 000070: 00000000 70000000 00000000 00000000 |.......p........| + 000080: 00000000 00000000 00000000 00000000 |................| + 000090: deadd00d 70108000 70108000 00000000 |.......p...p....| + 0000a0: 00000001 00000000 00000000 00000000 |................| + 0000b0: 00000000 00000000 00000000 00000000 |................| + 0000c0: 00000038 00010000 000e166e |8.......n...| + - regs-name: CP_DRAW_STATE + dwords: 256 + - regs-name: CP_UCODE_DBG_DATA + dwords: 24576 + SQE instruction cache: + ----------------------------------------------- + 4096 (0x1000) bytes + 000000: d8000000 981f0806 981f2006 2883003f |......... ..?..(| + 000010: cc86005f 5082001d 28420006 c8410006 |_......P..B(..A.| + 000020: 88040000 b805010a c8a20003 01000000 |................| + 000030: 30420003 c47e000f c476001d c464001e |..B0..~...v...d.| + 000040: c4680023 c47c0024 c47d0025 c47a0026 |#.h.$.|.%.}.&.z.| + 000050: c475002d c469002e c4710033 c4720032 |-.u...i.3.q.2.r.| + 000060: 981e2006 a8030018 a8040019 a802001a |. ..............| + 000070: 2ba50fff 48a50014 63a60008 50c60006 |...+...H...c...P| + 000080: 98663801 98802002 881c0080 a8070018 |.8f.. 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7a497f79 d837ae3b |.....,.\y.Iz;.7.| + 0007c0: 2ef0ab6f 9fa1d197 a4495431 64205a7c |o.......1TI.|Z d| + 0007d0: 97263716 c6402c83 b513f47a 6aa0630a |.7&..,@.z....c.j| + 0007e0: 6d459a37 6f730303 0dbc61ba 0c32efa2 |7.Em..so.a....2.| + 0007f0: 9189b297 959c2ca8 26280fab de3f00e1 |.....,....(&..?.| + Unknown 3: + ----------------------------------------------- + 512 (0x200) bytes + 000000: 00000000 00000000 00000000 00000000 |................| + 000010: 00000000 00000000 00000000 00000000 |................| + 000020: 00000000 00000000 00000000 00000000 |................| + 000030: 00000000 00000000 00000000 00000000 |................| + 000040: 00000000 00000000 00000000 00000000 |................| + 000050: 00000000 00000000 00000000 00000000 |................| + 000060: 00000000 00000000 00000000 00000000 |................| + 000070: 00000000 00000000 00000000 00000000 |................| + 000080: 00000084 00000e80 00000000 00000000 |................| + 000090: 00000000 00000000 00000000 00000000 |................| + 0000a0: 00000000 00000000 00000000 00000000 |................| + 0000b0: 00000000 00000000 00000000 00000000 |................| + 0000c0: 00000000 00000000 00000000 00000000 |................| + 0000d0: 00000000 00000000 00000000 00000000 |................| + 0000e0: 00000000 00000000 00000000 00000000 |................| + 0000f0: 00000000 00000000 00000000 00000000 |................| + 000100: 00000000 00000000 00000000 00000000 |................| + 000110: 00000000 00000000 00000000 00000000 |................| + 000120: 00000000 00000000 00000000 00000000 |................| + 000130: 00000000 00000000 00000000 00000000 |................| + 000140: 00000000 00000000 00000000 00000000 |................| + 000150: 00000000 00000000 00000000 00000000 |................| + 000160: 00000000 00000000 00000000 00000000 |................| + 000170: 00000000 00000000 00000000 00000000 |................| + 000180: 00000000 00000000 00000000 00000000 |................| + 000190: 00000000 00000000 00000000 00000000 |................| + 0001a0: 00000000 00000000 00000000 00000000 |................| + 0001b0: 00000000 00000000 00000000 00000000 |................| + 0001c0: 00000000 00000000 00000000 00000000 |................| + 0001d0: 00000000 00000000 00000000 00000000 |................| + 0001e0: 00000000 00000000 00000000 00000000 |................| + 0001f0: 00000000 00000000 00000000 00000000 |................| + SQE scratch control regs: + 17606c01 0x100: 17606c01 + 00000000 0x101: 00000000 + 00000000 0x102: 00000000 + 00000000 0x103: 00000000 + 00000000 0x104: 00000000 + 00000000 0x105: 00000000 + 00000000 0x106: 00000000 + 20000000 0x107: 20000000 + 00000000 0x108: 00000000 + 00000000 0x109: 00000000 + 00000000 0x10a: 00000000 + 00000000 0x10b: 00000000 + 00000000 0x10c: 00000000 + 00000000 0x10d: 00000000 + 23332200 0x10e: 23332200 + 30664402 0x10f: 30664402 + 00000000 SAVE_REGISTER_SMMU_INFO: 0 + 00000000 SAVE_REGISTER_SMMU_INFO+0x1: 0 + 00000000 SAVE_REGISTER_PRIV_NON_SECURE: 0 + 00000000 SAVE_REGISTER_PRIV_NON_SECURE+0x1: 0 + 00000000 SAVE_REGISTER_PRIV_SECURE: 0 + 00000000 SAVE_REGISTER_PRIV_SECURE+0x1: 0 + 00000000 SAVE_REGISTER_NON_PRIV: 0 + 00000000 SAVE_REGISTER_NON_PRIV+0x1: 0 + 00000000 SAVE_REGISTER_COUNTER: 0 + 00000000 SAVE_REGISTER_COUNTER+0x1: 0 + 00000000 0x11a: 00000000 + 00000000 0x11b: 00000000 + 00000000 0x11c: 00000000 + 00000000 0x11d: 00000000 + 00000000 0x11e: 00000000 + 00000000 0x11f: 00000000 + 00000000 0x120: 00000000 + 00000000 0x121: 00000000 + 00000000 0x122: 00000000 + 00000000 0x123: 00000000 + 00000000 0x124: 00000000 + 00000000 0x125: 00000000 + 00000000 PREEMPTION_INFO: 0 + 00000000 0x127: 00000000 + 00000000 0x128: 00000000 + 00000000 0x129: 00000000 + 00000101 0x12a: 00000101 + 00000004 MODE_BITMASK: 0x4 + 00000000 0x12c: 00000000 + 00000000 0x12d: 00000000 + 00000000 0x12e: 00000000 + 00000000 0x12f: 00000000 + 00000000 0x130: 00000000 + 00000000 0x131: 00000000 + 00000000 0x132: 00000000 + 00000000 0x133: 00000000 + 00000000 0x134: 00000000 + 00000000 0x135: 00000000 + 00000000 0x136: 00000000 + 00000000 0x137: 00000000 + 00000000 0x138: 00000000 + 00000000 0x139: 00000000 + 00000000 0x13a: 00000000 + 00000000 0x13b: 00000000 + 00000000 0x13c: 00000000 + 00000000 0x13d: 00000000 + 00000000 0x13e: 00000000 + 00000000 0x13f: 00000000 + 00000000 0x140: 00000000 + 00000000 0x141: 00000000 + 00000000 0x142: 00000000 + 00000000 0x143: 00000000 + 00000000 0x144: 00000000 + 00000000 0x145: 00000000 + 00000000 0x146: 00000000 + 00000000 0x147: 00000000 + 00000000 0x148: 00000000 + 00000000 0x149: 00000000 + 00000000 0x14a: 00000000 + 00000000 0x14b: 00000000 + 00000000 0x14c: 00000000 + 00000000 0x14d: 00000000 + 00000000 0x14e: 00000000 + 00000000 0x14f: 00000000 + 00000000 0x150: 00000000 + 00000000 0x151: 00000000 + 00000000 0x152: 00000000 + 00000000 0x153: 00000000 + 00000000 0x154: 00000000 + 00000000 0x155: 00000000 + 00000000 0x156: 00000000 + 00000000 0x157: 00000000 + 00000000 0x158: 00000000 + 00000000 0x159: 00000000 + 00000000 0x15a: 00000000 + 00000000 0x15b: 00000000 + 00000000 0x15c: 00000000 + 00000000 0x15d: 00000000 + 00000000 0x15e: 00000000 + 00000000 0x15f: 00000000 + 00000000 0x160: 00000000 + 00000000 0x161: 00000000 + 00000080 0x162: 00000080 + 00000001 0x163: 00000001 + 00000000 0x164: 00000000 + 00000000 0x165: 00000000 + 00000000 0x166: 00000000 + 00000000 0x167: 00000000 + 00000000 0x168: 00000000 + 00000000 0x169: 00000000 + 00000000 0x16a: 00000000 + 00000000 0x16b: 00000000 + 00000000 0x16c: 00000000 + 00000000 0x16d: 00000000 + 00000000 0x16e: 00000000 + 00000000 0x16f: 00000000 + 00000000 SCRATCH_REG0: 0 + 00000000 SCRATCH_REG1: 0 + 00000000 SCRATCH_REG2: 0 + 00000000 SCRATCH_REG3: 0 + 00000000 SCRATCH_REG4: 0 + 00000000 SCRATCH_REG5: 0 + 00000000 SCRATCH_REG6: 0 + 00000000 SCRATCH_REG7: 0 + 00000000 0x178: 00000000 + 00000000 0x179: 00000000 + 00000000 0x17a: 00000000 + 00000000 0x17b: 00000000 + 00000000 0x17c: 00000000 + 00000000 0x17d: 00000000 + 00000000 0x17e: 00000000 + 00000000 0x17f: 00000000 + - regs-name: CP_ROQ + dwords: 1024 + ----------------------------------------------- + 4096 (0x1000) bytes + 000000: 70c80008 0000002f 00000003 20000000 |...p/.......... | + 000010: 00000000 00000000 00000000 00000000 |................| + 000020: 00000000 00000000 00000000 00000000 |................| + 000030: 00000000 70e60001 00000000 00000000 |.......p........| + 000040: 00000000 70e60001 00000000 70df0001 |.......p.......p| + 000050: 00000000 70d30004 53c06000 00000002 |.......p.`.S....| + 000060: 00000000 00000000 70df0001 00000001 |...........p....| + 000070: 703d0004 00000808 00010000 53c06000 |..=p.........`.S| + 000080: 00000002 703e8003 40080400 00000028 |......>p...@(...| + 000090: 00010000 703e8003 4009f888 00000038 |......>p...@8...| + 0000a0: 00010000 70460001 00000018 70460001 |......Fp......Fp| + 0000b0: 00000019 70bf8003 00000000 00000001 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|................| + 0000a0: 00000003 00000003 00000003 00000003 |................| + 0000b0: 00000003 00000003 00000000 00000000 |................| + 0000c0: 00000000 00000000 00000000 00000000 |................| + 0000d0: 00000000 00000000 00000000 00000000 |................| + 0000e0: 00000000 00000000 00000000 00000000 |................| + 0000f0: 00000000 00000000 00000000 00000000 |................| + 000100: 00000000 00000000 00000000 00000000 |................| + 000110: 00000000 00000000 00000000 00000000 |................| + 000120: 00000000 00000000 00000000 00000000 |................| + 000130: 00000000 00000000 00000000 00000000 |................| + 000140: 00000000 00000000 00000000 00000000 |................| + 000150: 00000000 00000000 00000000 00000000 |................| + 000160: 00000007 00000007 00000007 00000007 |................| + 000170: 00000007 00000007 00000007 00000007 |................| + CLUSTER_FE: + + + CLUSTER_SP_VS: + + + CLUSTER_PC_VS: + + + CLUSTER_GRAS: + + + CLUSTER_SP_PS: + + + CLUSTER_PS: + + +shader-blocks: + - type: A6XX_TP0_TMO_DATA + - bank: 0 + size: 512 + - bank: 1 + size: 512 + - bank: 2 + size: 512 + - type: A6XX_TP0_SMO_DATA + - bank: 0 + size: 128 + - bank: 1 + size: 128 + - bank: 2 + size: 128 + - type: A6XX_TP0_MIPMAP_BASE_DATA + - bank: 0 + size: 960 + - bank: 1 + size: 960 + - bank: 2 + size: 960 + - type: A6XX_TP1_TMO_DATA + - bank: 0 + size: 512 + - bank: 1 + size: 512 + - bank: 2 + size: 512 + - type: A6XX_TP1_SMO_DATA + - bank: 0 + size: 128 + - bank: 1 + size: 128 + - bank: 2 + size: 128 + - type: A6XX_TP1_MIPMAP_BASE_DATA + - bank: 0 + size: 960 + - bank: 1 + size: 960 + - bank: 2 + size: 960 + - type: A6XX_SP_INST_DATA + - bank: 0 + size: 2048 + :0:0000:0000[0600e824x_a018c54ax] unknown(0,12) + :7:0001:0001[edc6145bx_11fa09c3x] (ss)(jp)unknown(7,11).g + :2:0002:0002[41440087x_008c504ax] ceil.f hr33.w, (neg)hc18.z + :0:0003:0003[14183488x_d5c04509x] (sy)(ss)(rpt4)cut + :5:0004:0008[a52373bdx_8ff7c071x] samgp0.3d.a.p (s8)(xy)hr47.y, r14.x, s#15, t#71 + :1:0005:0009[39301c43x_1d826d16x] (sy)(ss)(jp)(rpt4)cov.s16f16 (pos_infinity)hr16.w, (r)hc325.z + :3:0006:0014[7f64a39ax_609f35bcx] (sy)(jp)(rpt3)(ul)sad.s16 hr38.z, hc367.x, (neg)hc50.y, (r)hr39.w + :7:0007:0018[f352cfcbx_ecad502bx] (sy)unknown(7,6).g + :4:0008:0019[818209d0x_74021646x] (rpt1)unknown(4,12) hr52.x, (r)hc401.z + :6:0009:0021[c90972c0x_8e905e80x] (jp)stl.s16 l[hr48.x], hr976.x, 142 + :5:0010:0022[a4827242x_46248300x] gather4b.a (s8)(y)hr16.z, hr32.x, s#1, t#35 + :4:0011:0023[82342205x_cd064d21x] (rpt2)(ul)unknown(4,17) r1.y, (neg)c + :5:0012:0026[a923bf8bx_81f95908x] (jp)samb.3d.a.p (u32)(xyzw)r34.w, hr33.x, hr43.x, s#15, t#64 + :1:0013:0027[3dda8123x_a0d91ccdx] (sy)(jp)(rpt1)cov.u8u16 (even)(pos_infinity)hr, 0xa0d91ccd +../src/freedreno/decode/instr-a3xx.h:979: is_cat6_legacy: Assertion `instr->cat6.opc == 0' failed. + ----------------------------------------------- + 8192 (0x2000) bytes + 000000: a018c54a 0600e824 11fa09c3 edc6145b |J...$.......[...| + 000010: 008c504a 41440087 d5c04509 14183488 |JP....DA.E...4..| + 000020: 8ff7c071 a52373bd 1d826d16 39301c43 |q....s#..m..C.09| + 000030: 609f35bc 7f64a39a ecad502b f352cfcb |.5.`..d.+P....R.| + 000040: 74021646 818209d0 8e905e80 c90972c0 |F..t.....^...r..| + 000050: 46248300 a4827242 cd064d21 82342205 |..$FBr..!M..."4.| + 000060: 81f95908 a923bf8b a0d91ccd 3dda8123 |.Y....#.....#..=| + 000070: ff50ce54 c7ec0ca9 4397318f 1649f66e |T.P......1.Cn.I.| + 000080: f8ce238b 2b5a6874 85b579f1 3f56493c |.#..thZ+.y.....~.W...W| + 000100: c9033034 20786084 979c0ee0 0c529814 |40...`x ......R.| + 000110: 32c88944 b4286875 ac30023c 86a22ed5 |D..2uh(.<.0.....| + 000120: f3d9def0 a0fb82bf 85237f6e 63913a2e |........n.#..:.c| + 000130: edef742f 7ab4ef50 6c365676 dca7a11a |/t..P..zvV6l....| + 000140: 30128c72 025a791d 28431b94 9d43a84b |r..0.yZ...C(K.C.| + 000150: cd574282 8ae82250 31301961 402a48ed |.BW.P"..a.01.H*@| + 000160: d9c0cefe fce6ffdf b0739dbf 3e943c68 |..........s.h<.>| + 000170: c3f745cf f67db04d a6abefe4 af64fb6e |.E..M.}.....n.d.| + 000180: 0efc3e5c 1020e460 ef1e1f55 64ba2917 |\>..`. .U....).d| + 000190: 5b419bc1 3ee138ff 222220f8 b3c13b14 |..A[.8.>. "".;..| + 0001a0: fd5df7f2 fcfb13c1 8b0fddfa f33119eb |..]...........1.| + 0001b0: fbfc4e5f f2bfbd3b 6fb28edb fcb5eac7 |_N..;......o....| + 0001c0: 03fcad01 92d8ccf8 ac66ba5e 96c0afcc |........^.f.....| + 0001d0: 047aa351 e2d91251 1452ac65 52595026 |Q.z.Q...e.R.&PYR| + 0001e0: fd2affef fbd7dfef 016e952d f553b9f2 |..*.....-.n...S.| + 0001f0: 6ff3b1b7 4e735ede b7dbf7f7 c28c99a7 |...o.^sN........| + 000200: 058c0428 000a0642 ce01507d 6ec1e58a |(...B...}P.....n| + 000210: 95388c0b 4054b039 06804b52 08c3c5c9 |..8.9.T@RK......| + 000220: be5e26e0 f3c6f25c 839ccb64 db07bf5d |.&^.\...d...]...| + 000230: ff2656ee 0c9bdc22 bff7caba 703b72db |.V&."........r;p| + 000240: 1b787423 f08c24e7 25184a12 90068dca |#tx..$...J.%....| + 000250: 48fa0953 8660848a 0be91c6e aadd060b |S..H..`.n.......| + 000260: e7557eec b9f57b76 ac5431ed f758b5f7 |.~U.v{...1T...X.| + 000270: e2e0f3bf ddca194b 8bbabcb1 86c454a5 |....K........T..| + 000280: 61c92534 19907193 9b0d603d 07a0a640 |4%.a.q..=`..@...| + 000290: 0867489f 445f3ae9 ca68dc70 2b6595ce |.Hg..:_Dp.h...e+| + 0002a0: feef96e9 bbfe7272 bafef328 c76f9c4e |....rr..(...N.o.| + 0002b0: 43e3de0a 2da44d40 33f2cbf6 d652579b |...C@M.-...3.WR.| + 0002c0: 2539eb17 b10c2478 6ff84f58 6c1b12b8 |..9%x$..XO.o...l| + 0002d0: 0b17cb5c 60d978cd 175faaee 74bad9e6 |\....x.`.._....t| + 0002e0: f76afec9 feb755b3 8f64c737 5d767f3d |..j..U..7.d.=.v]| + 0002f0: ebbaeeeb b75756bf 7cf8b178 2cd537fe |.....VW.x..|.7.,| + 000300: 654b2a26 88d4c181 0618f42b 44bc4740 |&*Ke....+...@G.D| + 000310: 48e1acb0 5fc89835 090c12f8 10cb2389 |...H5.._.....#..| + 000320: 42d2e7ef defe60f7 fbf7767a e54e52e4 |...B.`..zv...RN.| + 000330: 4ad23ce6 7e051ba9 9ebfe9de ec67aeff |.<.J...~......g.| + 000340: 23e18542 d8404017 4ae49af7 9c8925a1 |B..#.@@....J.%..| + 000350: 571689d4 828a91cb 363febb9 fb824d4b |...W......?6KM..| + 000360: b3feb7dd bef5333c 92ced5db e8e2932d |....<3......-...| + 000370: f0bf8beb 99d7d46b 1abe7b5e 97e1ea7f |....k...^{......| + 000380: 11cd2a23 3e04c411 6680e0d5 b01a57e1 |#*.....>...f.W..| + 000390: 92dbf2ac 55d0afe1 d1c47087 b00bd2fc |.......U.p......| + 0003a0: 7cf748b7 c9effcf5 5dd5afe9 91c375c3 |.H.|.......].u..| + 0003b0: f67b8ddd a7f236b5 cabff4bd e8ff9de1 |..{..6..........| + 0003c0: 1482a119 7df11674 85115f26 b4071e36 |....t..}&_..6...| + 0003d0: ff0643c4 d98418c9 32d08fcd 281642ca |.C.........2.B.(| + 0003e0: de0497d0 7d75776f 04ccbefc b778a5db |....owu}......x.| + 0003f0: efdcebe8 f9df3c6f bdf8ffcd 6ffbbdff |....o<.........o| + 000400: 0aa90a26 be02481c 3c629c93 dedb5680 |&....H....b<.V..| + 000410: 4a9c628c da59d484 9d8184c7 9885c704 |.b.J..Y.........| + 000420: c177afef f9d6eeff 72a2c136 eadfcdad |..w.....6..r....| + 000430: bd976c9e 9b9fbdcc ab6433be e1551b57 |.l.......3d.W.U.| + 000440: 8474e835 a5bb67f1 111106d2 c6a74ddf |5.t..g.......M..| + 000450: e18c00f3 101a064f b8784e0d 40881aee |....O....Nx....@| + 000460: dfe7cbf8 d4b572b5 0bcf83ec 6d16af1f |.....r.........m| + 000470: ed1ee961 f9f5a93f fde65fda 45499723 |a...?...._..#.IE| + 000480: c5c10664 552fc17a 14e5391d 8c4311c1 |d...z./U.9....C.| + 000490: 181b7d1a 7bc908a6 849be161 cc07961f |.}.....{a.......| + 0004a0: f9f0fc4e af68fa8f 2af17a11 d907cd91 |N.....h..z.*....| + 0004b0: f9fb5072 fe272ee5 e6e3ff77 f306ffbe |rP....'.w.......| + 0004c0: 634d4c3e 8e90c2c2 1f61ecd2 a28427ae |>LMc......a..'..| + 0004d0: 01f6c1c0 897f04b4 0aa1bb8c c2623ee8 |.............>b.| + 0004e0: 07f7dbb3 717d2277 40acaf91 42b7f75d |....w"}q...@]..B| + 0004f0: acbfc70a fb2108fb f9fd5426 5ffbfefd |......!.&T....._| + 000500: 04e510a1 89a605f0 83c9bc98 dc5c1a7c |............|.\.| + 000510: e5a6e898 07012562 9621e2a1 c83f9ea2 |....b%....!...?.| + 000520: ffdeaf7d cefab3bf e7da322e 60bbe5a1 |}........2.....`| + 000530: bcb77cf1 dbd7baf2 b2d9dd96 7f3cabdd |.|............<.| + 000540: fc6561a0 d0708624 98f72000 3615359c |.ae.$.p.. ...5.6| + 000550: 54a25142 f96ca993 d80c087e 760e29a8 |BQ.T..l.~....).v| + 000560: 3f712110 fdfe37f5 1af7a877 7ebcf5f6 |.!q?.7..w......~| + 000570: d32fef46 6816fb16 cd73a47e d77de0e7 |F./....h~.s...}.| + 000580: a0131093 818bec38 8224d999 9154466d |....8.....$.mFT.| + 000590: c994989b 596da3af 270000b2 f67a3880 |......mY...'.8z.| + 0005a0: fac9377e cc9cd57e 2ef63cb6 2ff2c5f5 |~7..~....<...../| + 0005b0: 9ad5fbe4 badf5234 3fad75ba ffa37fc7 |....4R...u.?....| + 0005c0: 94009a03 44ccb685 902b0080 9e81b1b4 |.......D..+.....| + 0005d0: 4cd24d71 e4771db3 d22790f4 568698a2 |qM.L..w...'....V| + 0005e0: c9ffe4b9 afbbc5a5 4afb22d5 9c5543e5 |.........".J.CU.| + 0005f0: fde2ed56 38e70074 ff9d4e67 2e67f1b1 |V...t..8gN....g.| + 000600: 4a5013b5 02b03fc8 8fab2aa9 330f4265 |..PJ.?...*..eB.3| + 000610: ed96b590 0c71470e ae848354 feee9a11 |.....Gq.T.......| + 000620: d5fcf732 fd3f6d53 f174ef36 2dcfb77e |2...Sm?.6.t.~..-| + 000630: e18cf1ef b9c65e5d c3642500 be42dfd7 |....]^...%d...B.| + 000640: 05ac1829 98c080b4 d489b316 900f06b4 |)...............| + 000650: 47e5dd2f 0c9f53b8 ca11453e 4e413665 |/..G.S..>E..e6AN| + 000660: 3eb8fcf7 8ebc7363 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bank: 1 + size: 2048 + - bank: 2 + size: 2048 + - type: A6XX_SP_LB_0_DATA + - bank: 0 + size: 2048 + - bank: 1 + size: 2048 + - bank: 2 + size: 2048 + - type: A6XX_SP_LB_1_DATA + - bank: 0 + size: 2048 + - bank: 1 + size: 2048 + - bank: 2 + size: 2048 + - type: A6XX_SP_LB_2_DATA + - bank: 0 + size: 2048 + - bank: 1 + size: 2048 + - bank: 2 + size: 2048 + - type: A6XX_SP_LB_3_DATA + - bank: 0 + size: 2048 + - bank: 1 + size: 2048 + - bank: 2 + size: 2048 + - type: A6XX_SP_LB_4_DATA + - bank: 0 + size: 2048 + - bank: 1 + size: 2048 + - bank: 2 + size: 2048 + - type: A6XX_SP_LB_5_DATA + - bank: 0 + size: 512 + - bank: 1 + size: 512 + - bank: 2 + size: 512 + - type: A6XX_SP_CB_BINDLESS_DATA + - bank: 0 + size: 8192 + - bank: 1 + size: 8192 + - bank: 2 + size: 8192 + - type: A6XX_SP_CB_LEGACY_DATA + - bank: 0 + size: 640 + - bank: 1 + size: 640 + - bank: 2 + size: 640 + - type: A6XX_SP_UAV_DATA + - bank: 0 + size: 128 + - bank: 1 + size: 128 + - bank: 2 + size: 128 + - type: A6XX_SP_INST_TAG + - bank: 0 + size: 128 + - bank: 1 + size: 128 + - bank: 2 + size: 128 + - type: A6XX_SP_CB_BINDLESS_TAG + - bank: 0 + size: 128 + - bank: 1 + size: 128 + - bank: 2 + size: 128 + - type: A6XX_SP_TMO_UMO_TAG + - bank: 0 + size: 128 + - bank: 1 + size: 128 + - bank: 2 + size: 128 + - type: A6XX_SP_SMO_TAG + - bank: 0 + size: 128 + - bank: 1 + size: 128 + - bank: 2 + size: 128 + - type: A6XX_SP_STATE_DATA + - bank: 0 + size: 63 + - bank: 1 + size: 63 + - bank: 2 + size: 63 + - type: A6XX_HLSQ_CHUNK_CVS_RAM + - bank: 0 + size: 448 + - bank: 1 + size: 448 + - bank: 2 + size: 448 + - type: A6XX_HLSQ_CHUNK_CPS_RAM + - bank: 0 + size: 640 + - bank: 1 + size: 640 + - bank: 2 + size: 640 + - type: A6XX_HLSQ_CHUNK_CVS_RAM_TAG + - bank: 0 + size: 64 + - bank: 1 + size: 64 + - bank: 2 + size: 64 + - type: A6XX_HLSQ_CHUNK_CPS_RAM_TAG + - bank: 0 + size: 64 + - bank: 1 + size: 64 + - bank: 2 + size: 64 + - type: A6XX_HLSQ_ICB_CVS_CB_BASE_TAG + - bank: 0 + size: 4 + - bank: 1 + size: 4 + - bank: 2 + size: 4 + - type: A6XX_HLSQ_ICB_CPS_CB_BASE_TAG + - bank: 0 + size: 4 + - bank: 1 + size: 4 + - bank: 2 + size: 4 + - type: A6XX_HLSQ_CVS_MISC_RAM + - bank: 0 + size: 448 + - bank: 1 + size: 448 + - bank: 2 + size: 448 + - type: A6XX_HLSQ_CPS_MISC_RAM + - bank: 0 + size: 1408 + - bank: 1 + size: 1408 + - bank: 2 + size: 1408 + - type: A6XX_HLSQ_INST_RAM + - bank: 0 + size: 2048 + :2:0000:0000[40846422x_d81251c5x] (sat)(ul)sign.f r8.z, (neg)hc113.y + :4:0001:0001[938a16e2x_520c369ax] (sy)(ss)(sat)(rpt2)unknown(4,28) hr56.z, -358 + :1:0002:0004[200a00c1x_094864d2x] cov.u16f16 hr, hr308.z + :2:0003:0005[44109084x_4a201507x] (ss)unknown(2,32) (ei)r33.x, c321.w, (neg)r + :4:0004:0006[882fadabx_14a391b1x] (jp)(sat)(rpt1)(ul)rsq hr42.w, (abs)(r)hc108.y + :3:0005:0008[6060f068x_7106601ax] (ss)(ul)mad.u16 r26.x, (neg)hr6.z, (neg)hc48.y, (r)hc65.z + :3:0006:0009[60ed4212x_02900201x] (rpt2)madsh.u16 hr4.z, r128.y, r54.z, r164.x + :0:0007:0012[005b6589x_8a054280x] (eq)(rpt5)bkt #17024 + :3:0008:0018[7cebfff7x_dbae7deex] (sy)(ss)(jp)(sat)(rpt3)(ul)sel.b32 a3.x, (neg)(r)c891.z, (neg)c53.w, (neg)c747.z + :5:0009:0022[aff86b27x_fd7472ffx] (jp)unknown(5,31).o.p.base4 (u8)(xyw)hr9.w, r14.y, a1.x + :0:0010:0023[0ed959d7x_6d7a21a4x] (ss)(jp)(eq)(rpt1)unknown(0,13) + :2:0011:0025[445a8ebex_8d6e703bx] (sat)(rpt2)cmpv.s.gt (ei)r47.z, (neg)(r)59, (abs)(r)c +../src/freedreno/decode/instr-a3xx.h:979: is_cat6_legacy: Assertion `instr->cat6.opc == 0' failed. + ----------------------------------------------- + 8192 (0x2000) bytes + 000000: d81251c5 40846422 520c369a 938a16e2 |.Q.."d.@.6.R....| + 000010: 094864d2 200a00c1 4a201507 44109084 |.dH.... .. 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|......L ......@.| + 001ff0: 00000000 03000000 00000000 00000000 |................| + - bank: 1 + size: 2048 + :0:0000:0000[00000000x_00003002x] nop + :0:0001:0001[00000000x_00000000x] nop + :6:0002:0002[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0003:0003[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0004:0004[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0005:0005[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0006:0006[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0007:0007[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0008:0008[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0009:0009[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0010:0010[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0011:0011[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0012:0012[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0013:0013[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0014:0014[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0015:0015[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0016:0016[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0017:0017[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0018:0018[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0019:0019[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0020:0020[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0021:0021[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0022:0022[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0023:0023[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0024:0024[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0025:0025[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0026:0026[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0027:0027[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0028:0028[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0029:0029[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0030:0030[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0031:0031[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0032:0032[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0033:0033[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0034:0034[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0035:0035[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0036:0036[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0037:0037[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0038:0038[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0039:0039[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0040:0040[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0041:0041[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0042:0042[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0043:0043[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0044:0044[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0045:0045[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0046:0046[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0047:0047[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0048:0048[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0049:0049[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0050:0050[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0051:0051[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0052:0052[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0053:0053[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0054:0054[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0055:0055[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0056:0056[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0057:0057[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0058:0058[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0059:0059[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0060:0060[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0061:0061[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0062:0062[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0063:0063[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0064:0064[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0065:0065[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0066:0066[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0067:0067[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0068:0068[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0069:0069[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0070:0070[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0071:0071[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0072:0072[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0073:0073[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0074:0074[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0075:0075[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0076:0076[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0077:0077[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0078:0078[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0079:0079[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0080:0080[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0081:0081[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0082:0082[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0083:0083[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0084:0084[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0085:0085[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0086:0086[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0087:0087[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0088:0088[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0089:0089[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0090:0090[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0091:0091[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0092:0092[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0093:0093[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0094:0094[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0095:0095[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0096:0096[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0097:0097[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0098:0098[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0099:0099[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0100:0100[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0101:0101[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0102:0102[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0103:0103[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0104:0104[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0105:0105[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0106:0106[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0107:0107[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0108:0108[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0109:0109[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0110:0110[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0111:0111[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0112:0112[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0113:0113[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0114:0114[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0115:0115[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0116:0116[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0117:0117[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0118:0118[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0119:0119[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0120:0120[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0121:0121[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0122:0122[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0123:0123[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0124:0124[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0125:0125[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0126:0126[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0127:0127[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0128:0128[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0129:0129[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0130:0130[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0131:0131[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0132:0132[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0133:0133[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0134:0134[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0135:0135[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0136:0136[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0137:0137[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0138:0138[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0139:0139[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0140:0140[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0141:0141[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0142:0142[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0143:0143[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0144:0144[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0145:0145[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0146:0146[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0147:0147[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0148:0148[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0149:0149[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0150:0150[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0151:0151[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0152:0152[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0153:0153[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0154:0154[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0155:0155[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0156:0156[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0157:0157[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0158:0158[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0159:0159[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0160:0160[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0161:0161[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0162:0162[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0163:0163[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0164:0164[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0165:0165[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0166:0166[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0167:0167[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0168:0168[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0169:0169[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0170:0170[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0171:0171[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0172:0172[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0173:0173[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0174:0174[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0175:0175[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0176:0176[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0177:0177[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0178:0178[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0179:0179[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0180:0180[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0181:0181[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0182:0182[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0183:0183[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0184:0184[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0185:0185[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0186:0186[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0187:0187[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0188:0188[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0189:0189[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0190:0190[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0191:0191[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0192:0192[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0193:0193[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0194:0194[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0195:0195[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0196:0196[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0197:0197[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0198:0198[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0199:0199[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0200:0200[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0201:0201[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0202:0202[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0203:0203[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0204:0204[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0205:0205[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0206:0206[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0207:0207[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0208:0208[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0209:0209[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0210:0210[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0211:0211[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0212:0212[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0213:0213[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0214:0214[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0215:0215[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0216:0216[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0217:0217[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0218:0218[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0219:0219[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0220:0220[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0221:0221[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0222:0222[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0223:0223[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0224:0224[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0225:0225[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0226:0226[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0227:0227[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0228:0228[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0229:0229[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0230:0230[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0231:0231[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0232:0232[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0233:0233[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0234:0234[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0235:0235[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0236:0236[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0237:0237[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0238:0238[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0239:0239[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0240:0240[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0241:0241[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0242:0242[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0243:0243[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0244:0244[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0245:0245[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0246:0246[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0247:0247[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0248:0248[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0249:0249[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0250:0250[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0251:0251[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0252:0252[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0253:0253[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0254:0254[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0255:0255[deadbeefx_deadbeefx] (sy)(jp)atomic.xor.typed.4d.u8.4.l hr59.w, l[r45.z], 222 + :6:0256:0256[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0257:0257[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0258:0258[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0259:0259[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0260:0260[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0261:0261[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0262:0262[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0263:0263[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0264:0264[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0265:0265[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0266:0266[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0267:0267[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0268:0268[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0269:0269[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0270:0270[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0271:0271[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0272:0272[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0273:0273[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0274:0274[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0275:0275[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0276:0276[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0277:0277[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0278:0278[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0279:0279[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0280:0280[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0281:0281[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0282:0282[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0283:0283[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0284:0284[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0285:0285[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0286:0286[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0287:0287[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0288:0288[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0289:0289[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0290:0290[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0291:0291[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0292:0292[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0293:0293[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0294:0294[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0295:0295[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0296:0296[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0297:0297[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0298:0298[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0299:0299[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0300:0300[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0301:0301[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0302:0302[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0303:0303[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0304:0304[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0305:0305[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0306:0306[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0307:0307[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0308:0308[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0309:0309[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0310:0310[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0311:0311[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0312:0312[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0313:0313[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0314:0314[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0315:0315[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0316:0316[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0317:0317[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0318:0318[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0319:0319[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0320:0320[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0321:0321[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0322:0322[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0323:0323[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0324:0324[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0325:0325[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0326:0326[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0327:0327[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0328:0328[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0329:0329[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0330:0330[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0331:0331[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0332:0332[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0333:0333[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0334:0334[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0335:0335[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0336:0336[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0337:0337[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0338:0338[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0339:0339[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0340:0340[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0341:0341[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0342:0342[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0343:0343[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0344:0344[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0345:0345[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0346:0346[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0347:0347[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0348:0348[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0349:0349[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0350:0350[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0351:0351[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0352:0352[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0353:0353[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0354:0354[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0355:0355[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0356:0356[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0357:0357[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0358:0358[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0359:0359[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0360:0360[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0361:0361[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0362:0362[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0363:0363[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0364:0364[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0365:0365[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0366:0366[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0367:0367[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0368:0368[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0369:0369[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0370:0370[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0371:0371[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0372:0372[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0373:0373[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0374:0374[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0375:0375[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0376:0376[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0377:0377[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0378:0378[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0379:0379[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0380:0380[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0381:0381[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0382:0382[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0383:0383[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0384:0384[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0385:0385[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0386:0386[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0387:0387[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0388:0388[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0389:0389[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0390:0390[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0391:0391[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0392:0392[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0393:0393[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0394:0394[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0395:0395[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0396:0396[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0397:0397[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0398:0398[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0399:0399[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0400:0400[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0401:0401[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0402:0402[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0403:0403[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0404:0404[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0405:0405[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0406:0406[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0407:0407[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0408:0408[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0409:0409[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0410:0410[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0411:0411[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0412:0412[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0413:0413[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0414:0414[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0415:0415[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0416:0416[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0417:0417[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0418:0418[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0419:0419[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0420:0420[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0421:0421[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0422:0422[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0423:0423[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0424:0424[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0425:0425[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0426:0426[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0427:0427[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0428:0428[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0429:0429[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0430:0430[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0431:0431[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0432:0432[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0433:0433[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0434:0434[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0435:0435[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0436:0436[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0437:0437[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0438:0438[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0439:0439[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0440:0440[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0441:0441[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0442:0442[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0443:0443[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0444:0444[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0445:0445[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0446:0446[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0447:0447[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0448:0448[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0449:0449[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0450:0450[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0451:0451[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0452:0452[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0453:0453[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0454:0454[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0455:0455[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0456:0456[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0457:0457[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0458:0458[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0459:0459[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0460:0460[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0461:0461[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0462:0462[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0463:0463[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0464:0464[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0465:0465[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0466:0466[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0467:0467[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0468:0468[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0469:0469[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0470:0470[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0471:0471[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0472:0472[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0473:0473[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0474:0474[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0475:0475[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0476:0476[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0477:0477[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0478:0478[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0479:0479[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0480:0480[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0481:0481[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0482:0482[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0483:0483[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0484:0484[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0485:0485[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0486:0486[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0487:0487[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0488:0488[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0489:0489[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0490:0490[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0491:0491[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0492:0492[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0493:0493[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0494:0494[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0495:0495[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0496:0496[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0497:0497[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0498:0498[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0499:0499[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0500:0500[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0501:0501[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0502:0502[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0503:0503[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0504:0504[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0505:0505[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0506:0506[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0507:0507[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0508:0508[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0509:0509[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0510:0510[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :6:0511:0511[deafbeadx_deafbeadx] (sy)(jp)atomic.xor.typed.4d.s8.4.l hr43.y, l[r47.z], 222 + :0:0512:0512[00500240x_00024000x] (rpt2)nop + :0:0513:0515[00402020x_00000000x] nop + :0:0514:0516[00000040x_00001000x] nop + :0:0515:0517[00510401x_00024020x] (eq)(rpt4)nop + :0:0516:0522[00100080x_00000008x] nop + :0:0517:0523[00000044x_00002080x] nop + :0:0518:0524[00001000x_00000000x] (ss)nop + :0:0519:0525[00200000x_00000008x] nop + :0:0520:0526[00000044x_00048110x] nop + :0:0521:0527[00000040x_00508000x] nop + :0:0522:0528[00010200x_00020044x] (eq)(rpt2)nop + :0:0523:0531[00000000x_00201014x] nop + :0:0524:0532[00012100x_00101100x] (eq)(rpt1)nop + :0:0525:0534[00000012x_00005000x] nop + :0:0526:0535[00000010x_00005000x] nop + :0:0527:0536[00040000x_00000020x] nop + :0:0528:0537[00002101x_00082514x] (rpt1)nop + :0:0529:0539[00000000x_00210020x] nop + :0:0530:0540[00440004x_00010002x] nop + :0:0531:0541[00000002x_00000250x] nop + :0:0532:0542[00000040x_00100000x] nop + :0:0533:0543[00000000x_00020014x] nop + :0:0534:0544[000400a0x_00050020x] nop + :0:0535:0545[00100000x_00000000x] nop + :0:0536:0546[00000000x_00044081x] nop + :0:0537:0547[00000000x_00000000x] nop + :0:0538:0548[00200048x_00000100x] nop + :0:0539:0549[00080020x_00000000x] nop + :0:0540:0550[00200002x_00200001x] nop + :0:0541:0551[002000a4x_00000404x] nop + :0:0542:0552[00440246x_00000004x] (rpt2)nop + :0:0543:0555[0008c040x_00442000x] nop + :0:0544:0556[002112a0x_00200000x] (ss)(eq)(rpt2)nop + :0:0545:0559[00000000x_00000000x] nop + :0:0546:0560[00000240x_00400001x] (rpt2)nop + :0:0547:0563[00000000x_00040400x] nop + :0:0548:0564[0000a100x_00104010x] (rpt1)nop + :0:0549:0566[00008480x_00002001x] (rpt4)nop + :0:0550:0571[00000001x_00000040x] nop + :0:0551:0572[00040001x_00040400x] nop + :0:0552:0573[00200000x_00040600x] nop + :0:0553:0574[00000100x_00100000x] (rpt1)nop + :0:0554:0576[00504180x_0020a200x] (rpt1)nop + :0:0555:0578[00000000x_00000000x] nop + :0:0556:0579[00000024x_00004000x] nop + :0:0557:0580[00200000x_00100008x] nop + :0:0558:0581[00010080x_00000000x] (eq)nop + :0:0559:0582[00080000x_00000000x] nop + :0:0560:0583[00084000x_00500400x] nop + :0:0561:0584[00004000x_00008000x] nop + :0:0562:0585[00200000x_00000300x] nop + :0:0563:0586[00000042x_00020001x] nop + :0:0564:0587[00005600x_00400088x] (ss)(rpt6)nop + :0:0565:0594[00000002x_00000000x] nop + :0:0566:0595[0002005ex_00400008x] bkt #8 + :0:0567:0596[00020020x_00200000x] bkt #0 + :0:0568:0597[001e0414x_00055480x] (rpt4)bkt #21632 + :0:0569:0602[00000000x_00000000x] nop + :0:0570:0603[00000442x_00000480x] (rpt4)nop + :0:0571:0608[00000200x_00080000x] (rpt2)nop + :0:0572:0611[00520000x_00600400x] bkt #1024 + :0:0573:0612[00001200x_00000008x] (ss)(rpt2)nop + :0:0574:0615[00400114x_00201000x] (rpt1)nop + :0:0575:0617[00110100x_00100002x] (eq)(rpt1)nop + :0:0576:0619[00404200x_00200683x] (rpt2)nop + :0:0577:0622[00000090x_00000004x] nop + :0:0578:0623[00502000x_00002000x] nop + :0:0579:0624[00000004x_00000020x] nop + :0:0580:0625[00103100x_00600010x] (ss)(rpt1)nop + :0:0581:0627[00000002x_00000010x] nop + :0:0582:0628[00004000x_00021200x] nop + :0:0583:0629[00000000x_00000000x] nop + :0:0584:0630[00201400x_0010220ax] (ss)(rpt4)nop + :0:0585:0635[00000000x_00030000x] nop + :0:0586:0636[00080040x_00400000x] nop + :0:0587:0637[00000080x_00000002x] nop + :0:0588:0638[00000580x_00000400x] (rpt5)nop + :0:0589:0644[00000200x_00000022x] (rpt2)nop + :0:0590:0647[00080000x_00300042x] nop + :0:0591:0648[00008000x_00040200x] nop + :0:0592:0649[00000000x_00040000x] nop + :0:0593:0650[0012008ax_00000010x] bkt #16 + :0:0594:0651[00000100x_00000000x] (rpt1)nop + :0:0595:0653[00010000x_00010018x] (eq)nop + :0:0596:0654[00500011x_00440020x] nop + :0:0597:0655[00100000x_00000000x] nop + :0:0598:0656[00008200x_0004020cx] (rpt2)nop + :0:0599:0659[00000400x_00100010x] (rpt4)nop + :0:0600:0664[00000004x_00118000x] nop + :0:0601:0665[00000002x_00004200x] nop + :0:0602:0666[00026300x_00000210x] (rpt3)bkt #528 + :0:0603:0670[0000a002x_00000040x] nop + :0:0604:0671[00081100x_00004082x] (ss)(rpt1)nop + :0:0605:0673[00000008x_00210000x] nop + :0:0606:0674[00020004x_00020000x] bkt #0 + :0:0607:0675[00020000x_00064108x] bkt #16648 + :0:0608:0676[00000084x_00020000x] nop + :0:0609:0677[00000181x_00000430x] (rpt1)nop + :0:0610:0679[001c8100x_00100002x] (rpt1)nop + :0:0611:0681[00000000x_00200020x] nop + :0:0612:0682[00100081x_00002000x] nop + :0:0613:0683[00000000x_00000008x] nop + :0:0614:0684[00009420x_00000024x] (ss)(rpt4)nop + :0:0615:0689[00000100x_00002010x] (rpt1)nop + :0:0616:0691[00004188x_00000000x] (rpt1)nop + :0:0617:0693[00100000x_00002000x] nop + :0:0618:0694[00120102x_00040000x] (rpt1)bkt #0 + :0:0619:0696[00040002x_00000000x] nop + :0:0620:0697[00224200x_00210201x] (rpt2)bkt #513 + :0:0621:0700[00000200x_00040000x] (rpt2)nop + :0:0622:0703[0000000cx_00000000x] nop + :0:0623:0704[00000000x_00005000x] nop + :0:0624:0705[00082208x_00010200x] (rpt2)nop + :0:0625:0708[00194011x_00000000x] (eq)nop + :0:0626:0709[00012100x_00000502x] (eq)(rpt1)nop + :0:0627:0711[00000240x_00040050x] (rpt2)nop + :0:0628:0714[00080211x_00004180x] (rpt2)nop + :0:0629:0717[00000000x_00001008x] nop + :0:0630:0718[00020490x_002004a0x] (rpt4)bkt #1184 + :0:0631:0723[00210004x_00001080x] (eq)nop + :0:0632:0724[00000000x_00300040x] nop + :0:0633:0725[00008002x_00000020x] nop + :0:0634:0726[00000000x_00041098x] nop + :0:0635:0727[002000a0x_00000000x] nop + :0:0636:0728[00000000x_000c0400x] nop + :0:0637:0729[00000401x_00000402x] (rpt4)nop + :0:0638:0734[00002000x_00200400x] nop + :0:0639:0735[00000101x_00001000x] (rpt1)nop + :0:0640:0737[00500240x_00024000x] (rpt2)nop + :0:0641:0740[00402020x_00000000x] nop + :0:0642:0741[00000040x_00001000x] nop + :0:0643:0742[00510401x_00024020x] (eq)(rpt4)nop + :0:0644:0747[00100080x_00000008x] nop + :0:0645:0748[00000044x_00002080x] nop + :0:0646:0749[00001000x_00000000x] (ss)nop + :0:0647:0750[00200000x_00000008x] nop + :0:0648:0751[00000044x_00048110x] nop + :0:0649:0752[00000040x_00508000x] nop + :0:0650:0753[00010200x_00020044x] (eq)(rpt2)nop + :0:0651:0756[00000000x_00201014x] nop + :0:0652:0757[00012100x_00101100x] (eq)(rpt1)nop + :0:0653:0759[00000012x_00005000x] nop + :0:0654:0760[00000010x_00005000x] nop + :0:0655:0761[00040000x_00000020x] nop + :0:0656:0762[00002101x_00082514x] (rpt1)nop + :0:0657:0764[00000000x_00210020x] nop + :0:0658:0765[00440004x_00010002x] nop + :0:0659:0766[00000002x_00000250x] nop + :0:0660:0767[00000040x_00100000x] nop + :0:0661:0768[00000000x_00020014x] nop + :0:0662:0769[000400a0x_00050020x] nop + :0:0663:0770[00100000x_00000000x] nop + :0:0664:0771[00000000x_00044081x] nop + :0:0665:0772[00000000x_00000000x] nop + :0:0666:0773[00200048x_00000100x] nop + :0:0667:0774[00080020x_00000000x] nop + :0:0668:0775[00200002x_00200001x] nop + :0:0669:0776[002000a4x_00000404x] nop + :0:0670:0777[00440246x_00000004x] (rpt2)nop + :0:0671:0780[0008c040x_00442000x] nop + :0:0672:0781[002112a0x_00200000x] (ss)(eq)(rpt2)nop + :0:0673:0784[00000000x_00000000x] nop + :0:0674:0785[00000240x_00400001x] (rpt2)nop + :0:0675:0788[00000000x_00040400x] nop + :0:0676:0789[0000a100x_00104010x] (rpt1)nop + :0:0677:0791[00008480x_00002001x] (rpt4)nop + :0:0678:0796[00000001x_00000040x] nop + :0:0679:0797[00040001x_00040400x] nop + :0:0680:0798[00200000x_00040600x] nop + :0:0681:0799[00000100x_00100000x] (rpt1)nop + :0:0682:0801[00504180x_0020a200x] (rpt1)nop + :0:0683:0803[00000000x_00000000x] nop + :0:0684:0804[00000024x_00004000x] nop + :0:0685:0805[00200000x_00100008x] nop + :0:0686:0806[00010080x_00000000x] (eq)nop + :0:0687:0807[00080000x_00000000x] nop + :0:0688:0808[00084000x_00500400x] nop + :0:0689:0809[00004000x_00008000x] nop + :0:0690:0810[00200000x_00000300x] nop + :0:0691:0811[00000042x_00020001x] nop + :0:0692:0812[00005600x_00400088x] (ss)(rpt6)nop + :0:0693:0819[00000002x_00000000x] nop + :0:0694:0820[0002005ex_00400008x] bkt #8 + :0:0695:0821[00020020x_00200000x] bkt #0 + :0:0696:0822[001e0414x_00055480x] (rpt4)bkt #21632 + :0:0697:0827[00000000x_00000000x] nop + :0:0698:0828[00000442x_00000480x] (rpt4)nop + :0:0699:0833[00000200x_00080000x] (rpt2)nop + :0:0700:0836[00520000x_00600400x] bkt #1024 + :0:0701:0837[00001200x_00000008x] (ss)(rpt2)nop + :0:0702:0840[00400114x_00201000x] (rpt1)nop + :0:0703:0842[00110100x_00100002x] (eq)(rpt1)nop + :0:0704:0844[00404200x_00200683x] (rpt2)nop + :0:0705:0847[00000090x_00000004x] nop + :0:0706:0848[00502000x_00002000x] nop + :0:0707:0849[00000004x_00000020x] nop + :0:0708:0850[00103100x_00600010x] (ss)(rpt1)nop + :0:0709:0852[00000002x_00000010x] nop + :0:0710:0853[00004000x_00021200x] nop + :0:0711:0854[00000000x_00000000x] nop + :0:0712:0855[00201400x_0010220ax] (ss)(rpt4)nop + :0:0713:0860[00000000x_00030000x] nop + :0:0714:0861[00080040x_00400000x] nop + :0:0715:0862[00000080x_00000002x] nop + :0:0716:0863[00000580x_00000400x] (rpt5)nop + :0:0717:0869[00000200x_00000022x] (rpt2)nop + :0:0718:0872[00080000x_00300042x] nop + :0:0719:0873[00008000x_00040200x] nop + :0:0720:0874[00000000x_00040000x] nop + :0:0721:0875[0012008ax_00000010x] bkt #16 + :0:0722:0876[00000100x_00000000x] (rpt1)nop + :0:0723:0878[00010000x_00010018x] (eq)nop + :0:0724:0879[00500011x_00440020x] nop + :0:0725:0880[00100000x_00000000x] nop + :0:0726:0881[00008200x_0004020cx] (rpt2)nop + :0:0727:0884[00000400x_00100010x] (rpt4)nop + :0:0728:0889[00000004x_00118000x] nop + :0:0729:0890[00000002x_00004200x] nop + :0:0730:0891[00026300x_00000210x] (rpt3)bkt #528 + :0:0731:0895[0000a002x_00000040x] nop + :0:0732:0896[00081100x_00004082x] (ss)(rpt1)nop + :0:0733:0898[00000008x_00210000x] nop + :0:0734:0899[00020004x_00020000x] bkt #0 + :0:0735:0900[00020000x_00064108x] bkt #16648 + :0:0736:0901[00000084x_00020000x] nop + :0:0737:0902[00000181x_00000430x] (rpt1)nop + :0:0738:0904[001c8100x_00100002x] (rpt1)nop + :0:0739:0906[00000000x_00200020x] nop + :0:0740:0907[00100081x_00002000x] nop + :0:0741:0908[00000000x_00000008x] nop + :0:0742:0909[00009420x_00000024x] (ss)(rpt4)nop + :0:0743:0914[00000100x_00002010x] (rpt1)nop + :0:0744:0916[00004188x_00000000x] (rpt1)nop + :0:0745:0918[00100000x_00002000x] nop + :0:0746:0919[00120102x_00040000x] (rpt1)bkt #0 + :0:0747:0921[00040002x_00000000x] nop + :0:0748:0922[00224200x_00210201x] (rpt2)bkt #513 + :0:0749:0925[00000200x_00040000x] (rpt2)nop + :0:0750:0928[0000000cx_00000000x] nop + :0:0751:0929[00000000x_00005000x] nop + :0:0752:0930[00082208x_00010200x] (rpt2)nop + :0:0753:0933[00194011x_00000000x] (eq)nop + :0:0754:0934[00012100x_00000502x] (eq)(rpt1)nop + :0:0755:0936[00000240x_00040050x] (rpt2)nop + :0:0756:0939[00080211x_00004180x] (rpt2)nop + :0:0757:0942[00000000x_00001008x] nop + :0:0758:0943[00020490x_002004a0x] (rpt4)bkt #1184 + :0:0759:0948[00210004x_00001080x] (eq)nop + :0:0760:0949[00000000x_00300040x] nop + :0:0761:0950[00008002x_00000020x] nop + :0:0762:0951[00000000x_00041098x] nop + :0:0763:0952[002000a0x_00000000x] nop + :0:0764:0953[00000000x_000c0400x] nop + :0:0765:0954[00000401x_00000402x] (rpt4)nop + :0:0766:0959[00002000x_00200400x] nop + :0:0767:0960[00000101x_00001000x] (rpt1)nop + :0:0768:0962[00000000x_00000000x] nop + :0:0769:0963[00000000x_00000000x] nop + :0:0770:0964[00000000x_00000000x] nop + :0:0771:0965[00000000x_00000000x] nop + :0:0772:0966[00000000x_00000000x] nop + :0:0773:0967[00000000x_00000000x] nop + :0:0774:0968[00000000x_00000000x] nop + :0:0775:0969[00000000x_00000000x] nop + :0:0776:0970[00000000x_00000000x] nop + :0:0777:0971[00000000x_00000000x] nop + :0:0778:0972[00000000x_00000000x] nop + :0:0779:0973[00000000x_00000000x] nop + :0:0780:0974[00000000x_00000000x] nop + :0:0781:0975[00000000x_00000000x] nop + :0:0782:0976[00000000x_00000000x] nop + :0:0783:0977[00000000x_00000000x] nop + :0:0784:0978[00000000x_00000000x] nop + :0:0785:0979[00000000x_00000000x] nop + :0:0786:0980[00000000x_00000000x] nop + :0:0787:0981[00000000x_00000000x] nop + :0:0788:0982[00000000x_00000000x] nop + :0:0789:0983[00000000x_00000000x] nop + :0:0790:0984[00000000x_00000000x] nop + :0:0791:0985[00000000x_00000000x] nop + :0:0792:0986[00000000x_00000000x] nop + :0:0793:0987[00000000x_00000000x] nop + :0:0794:0988[00000000x_00000000x] nop + :0:0795:0989[00000000x_00000000x] nop + :0:0796:0990[00000000x_00000000x] nop + :0:0797:0991[00000000x_00000000x] nop + :0:0798:0992[00000000x_00000000x] nop + :0:0799:0993[00000000x_00000000x] nop + :0:0800:0994[00000000x_00000000x] nop + :0:0801:0995[00000000x_00000000x] nop + :0:0802:0996[00000000x_00000000x] nop + :0:0803:0997[00000000x_00000000x] nop + :0:0804:0998[00000000x_00000000x] nop + :0:0805:0999[00000000x_00000000x] nop + :0:0806:1000[00000000x_00000000x] nop + :0:0807:1001[00000000x_00000000x] nop + :0:0808:1002[00000000x_00000000x] nop + :0:0809:1003[00000000x_00000000x] nop + :0:0810:1004[00000000x_00000000x] nop + :0:0811:1005[00000000x_00000000x] nop + :0:0812:1006[00000000x_00000000x] nop + :0:0813:1007[00000000x_00000000x] nop + :0:0814:1008[00000000x_00000000x] nop + :0:0815:1009[00000000x_00000000x] nop + :0:0816:1010[00000000x_00000000x] nop + :0:0817:1011[00000000x_00000000x] nop + :0:0818:1012[00000000x_00000000x] nop + :0:0819:1013[00000000x_00000000x] nop + :0:0820:1014[00000000x_00000000x] nop + :0:0821:1015[00000000x_00000000x] nop + :0:0822:1016[00000000x_00000000x] nop + :0:0823:1017[00000000x_00000000x] nop + :0:0824:1018[00000000x_00000000x] nop + :0:0825:1019[00000000x_00000000x] nop + :0:0826:1020[00000000x_00000000x] nop + :0:0827:1021[00000000x_00000000x] nop + :0:0828:1022[00000000x_00000000x] nop + :0:0829:1023[00000000x_00000000x] nop + :0:0830:1024[00000000x_00000000x] nop + :0:0831:1025[00000000x_00000000x] nop + :0:0832:1026[00000000x_00000000x] nop + :0:0833:1027[00000000x_00000000x] nop + :0:0834:1028[00000000x_00000000x] nop + :0:0835:1029[00000000x_00000000x] nop + :0:0836:1030[00000000x_00000000x] nop + :0:0837:1031[00000000x_00000000x] nop + :0:0838:1032[00000000x_00000000x] nop + :0:0839:1033[00000000x_00000000x] nop + :0:0840:1034[00000000x_00000000x] nop + :0:0841:1035[00000000x_00000000x] nop + :0:0842:1036[00000000x_00000000x] nop + :0:0843:1037[00000000x_00000000x] nop + :0:0844:1038[00000000x_00000000x] nop + :0:0845:1039[00000000x_00000000x] nop + :0:0846:1040[00000000x_00000000x] nop + :0:0847:1041[00000000x_00000000x] nop + :0:0848:1042[00000000x_00000000x] nop + :0:0849:1043[00000000x_00000000x] nop + :0:0850:1044[00000000x_00000000x] nop + :0:0851:1045[00000000x_00000000x] nop + :0:0852:1046[00000000x_00000000x] nop + :0:0853:1047[00000000x_00000000x] nop + :0:0854:1048[00000000x_00000000x] nop + :0:0855:1049[00000000x_00000000x] nop + :0:0856:1050[00000000x_00000000x] nop + :0:0857:1051[00000000x_00000000x] nop + :0:0858:1052[00000000x_00000000x] nop + :0:0859:1053[00000000x_00000000x] nop + :0:0860:1054[00000000x_00000000x] nop + :0:0861:1055[00000000x_00000000x] nop + :0:0862:1056[00000000x_00000000x] nop + :0:0863:1057[00000000x_00000000x] nop + :0:0864:1058[00000000x_00000000x] nop + :0:0865:1059[00000000x_00000000x] nop + :0:0866:1060[00000000x_00000000x] nop + :0:0867:1061[00000000x_00000000x] nop + :0:0868:1062[00000000x_00000000x] nop + :0:0869:1063[00000000x_00000000x] nop + :0:0870:1064[00000000x_00000000x] nop + :0:0871:1065[00000000x_00000000x] nop + :0:0872:1066[00000000x_00000000x] nop + :0:0873:1067[00000000x_00000000x] nop + :0:0874:1068[00000000x_00000000x] nop + :0:0875:1069[00000000x_00000000x] nop + :0:0876:1070[00000000x_00000000x] nop + :0:0877:1071[00000000x_00000000x] nop + :0:0878:1072[00000000x_00000000x] nop + :0:0879:1073[00000000x_00000000x] nop + :0:0880:1074[00000000x_00000000x] nop + :0:0881:1075[00000000x_00000000x] nop + :0:0882:1076[00000000x_00000000x] nop + :0:0883:1077[00000000x_00000000x] nop + :0:0884:1078[00000000x_00000000x] nop + :0:0885:1079[00000000x_00000000x] nop + :0:0886:1080[00000000x_00000000x] nop + :0:0887:1081[00000000x_00000000x] nop + :0:0888:1082[00000000x_00000000x] nop + :0:0889:1083[00000000x_00000000x] nop + :0:0890:1084[00000000x_00000000x] nop + :0:0891:1085[00000000x_00000000x] nop + :0:0892:1086[00000000x_00000000x] nop + :0:0893:1087[00000000x_00000000x] nop + :0:0894:1088[00000000x_00000000x] nop + :0:0895:1089[00000000x_00000000x] nop + :0:0896:1090[00000000x_00000000x] nop + :0:0897:1091[00000000x_00000000x] nop + :0:0898:1092[00000000x_00000000x] nop + :0:0899:1093[00000000x_00000000x] nop + :0:0900:1094[00000000x_00000000x] nop + :0:0901:1095[00000000x_00000000x] nop + :0:0902:1096[00000000x_00000000x] nop + :0:0903:1097[00000000x_00000000x] nop + :0:0904:1098[00000000x_00000000x] nop + :0:0905:1099[00000000x_00000000x] nop + :0:0906:1100[00000000x_00000000x] nop + :0:0907:1101[00000000x_00000000x] nop + :0:0908:1102[00000000x_00000000x] nop + :0:0909:1103[00000000x_00000000x] nop + :0:0910:1104[00000000x_00000000x] nop + :0:0911:1105[00000000x_00000000x] nop + :0:0912:1106[00000000x_00000000x] nop + :0:0913:1107[00000000x_00000000x] nop + :0:0914:1108[00000000x_00000000x] nop + :0:0915:1109[00000000x_00000000x] nop + :0:0916:1110[00000000x_00000000x] nop + :0:0917:1111[00000000x_00000000x] nop + :0:0918:1112[00000000x_00000000x] nop + :0:0919:1113[00000000x_00000000x] nop + :0:0920:1114[00000000x_00000000x] nop + :0:0921:1115[00000000x_00000000x] nop + :0:0922:1116[00000000x_00000000x] nop + :0:0923:1117[00000000x_00000000x] nop + :0:0924:1118[00000000x_00000000x] nop + :0:0925:1119[00000000x_00000000x] nop + :0:0926:1120[00000000x_00000000x] nop + :0:0927:1121[00000000x_00000000x] nop + :0:0928:1122[00000000x_00000000x] nop + :0:0929:1123[00000000x_00000000x] nop + :0:0930:1124[00000000x_00000000x] nop + :0:0931:1125[00000000x_00000000x] nop + :0:0932:1126[00000000x_00000000x] nop + :0:0933:1127[00000000x_00000000x] nop + :0:0934:1128[00000000x_00000000x] nop + :0:0935:1129[00000000x_00000000x] nop + :0:0936:1130[00000000x_00000000x] nop + :0:0937:1131[00000000x_00000000x] nop + :0:0938:1132[00000000x_00000000x] nop + :0:0939:1133[00000000x_00000000x] nop + :0:0940:1134[00000000x_00000000x] nop + :0:0941:1135[00000000x_00000000x] nop + :0:0942:1136[00000000x_00000000x] nop + :0:0943:1137[00000000x_00000000x] nop + :0:0944:1138[00000000x_00000000x] nop + :0:0945:1139[00000000x_00000000x] nop + :0:0946:1140[00000000x_00000000x] nop + :0:0947:1141[00000000x_00000000x] nop + :0:0948:1142[00000000x_00000000x] nop + :0:0949:1143[00000000x_00000000x] nop + :0:0950:1144[00000000x_00000000x] nop + :0:0951:1145[00000000x_00000000x] nop + :0:0952:1146[00000000x_00000000x] nop + :0:0953:1147[00000000x_00000000x] nop + :0:0954:1148[00000000x_00000000x] nop + :0:0955:1149[00000000x_00000000x] nop + :0:0956:1150[00000000x_00000000x] nop + :0:0957:1151[00000000x_00000000x] nop + :0:0958:1152[00000000x_00000000x] nop + :0:0959:1153[00000000x_00000000x] nop + :0:0960:1154[00000000x_00000000x] nop + :0:0961:1155[00000000x_00000000x] nop + :0:0962:1156[00000000x_00000000x] nop + :0:0963:1157[00000000x_00000000x] nop + :0:0964:1158[00000000x_00000000x] nop + :0:0965:1159[00000000x_00000000x] nop + :0:0966:1160[00000000x_00000000x] nop + :0:0967:1161[00000000x_00000000x] nop + :0:0968:1162[00000000x_00000000x] nop + :0:0969:1163[00000000x_00000000x] nop + :0:0970:1164[00000000x_00000000x] nop + :0:0971:1165[00000000x_00000000x] nop + :0:0972:1166[00000000x_00000000x] nop + :0:0973:1167[00000000x_00000000x] nop + :0:0974:1168[00000000x_00000000x] nop + :0:0975:1169[00000000x_00000000x] nop + :0:0976:1170[00000000x_00000000x] nop + :0:0977:1171[00000000x_00000000x] nop + :0:0978:1172[00000000x_00000000x] nop + :0:0979:1173[00000000x_00000000x] nop + :0:0980:1174[00000000x_00000000x] nop + :0:0981:1175[00000000x_00000000x] nop + :0:0982:1176[00000000x_00000000x] nop + :0:0983:1177[00000000x_00000000x] nop + :0:0984:1178[00000000x_00000000x] nop + :0:0985:1179[00000000x_00000000x] nop + :0:0986:1180[00000000x_00000000x] nop + :0:0987:1181[00000000x_00000000x] nop + :0:0988:1182[00000000x_00000000x] nop + :0:0989:1183[00000000x_00000000x] nop + :0:0990:1184[00000000x_00000000x] nop + :0:0991:1185[00000000x_00000000x] nop + :0:0992:1186[00000000x_00000000x] nop + :0:0993:1187[00000000x_00000000x] nop + :0:0994:1188[00000000x_00000000x] nop + :0:0995:1189[00000000x_00000000x] nop + :0:0996:1190[00000000x_00000000x] nop + :0:0997:1191[00000000x_00000000x] nop + :0:0998:1192[00000000x_00000000x] nop + :0:0999:1193[00000000x_00000000x] nop + :0:1000:1194[00000000x_00000000x] nop + :0:1001:1195[00000000x_00000000x] nop + :0:1002:1196[00000000x_00000000x] nop + :0:1003:1197[00000000x_00000000x] nop + :0:1004:1198[00000000x_00000000x] nop + :0:1005:1199[00000000x_00000000x] nop + :0:1006:1200[00000000x_00000000x] nop + :0:1007:1201[00000000x_00000000x] nop + :0:1008:1202[00000000x_00000000x] nop + :0:1009:1203[00000000x_00000000x] nop + :0:1010:1204[00000000x_00000000x] nop + :0:1011:1205[00000000x_00000000x] nop + :0:1012:1206[00000000x_00000000x] nop + :0:1013:1207[00000000x_00000000x] nop + :0:1014:1208[00000000x_00000000x] nop + :0:1015:1209[00000000x_00000000x] nop + :0:1016:1210[00000000x_00000000x] nop + :0:1017:1211[00000000x_00000000x] nop + :0:1018:1212[00000000x_00000000x] nop + :0:1019:1213[00000000x_00000000x] nop + :0:1020:1214[00000000x_00000000x] nop + :0:1021:1215[00000000x_00000000x] nop + :0:1022:1216[00000000x_00000000x] nop + :0:1023:1217[00000000x_00000000x] nop + Register Stats: + - used (half): 173 239 (cnt=2, max=173) + - used (full): 182 190 (cnt=2, max=190) + - used (merged): 173 239 364-365 380-381 (cnt=6, max=173) + - input (half): 173 239 (cnt=2, max=173) + - input (full): 182 190 (cnt=2, max=190) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): (cnt=0, max=0) (estimated) + - shaderdb: 1218 instructions, 658 nops, 560 non-nops, (1024 instlen), 44 half, 48 full + - shaderdb: 16 (ss), 510 (sy) + ----------------------------------------------- + 8192 (0x2000) bytes + 000000: 00003002 00000000 00000000 00000000 |.0..............| + 000010: deadbeef deadbeef deadbeef deadbeef |................| + 000020: deadbeef deadbeef deadbeef deadbeef |................| + 000030: deadbeef deadbeef deadbeef deadbeef |................| + 000040: deadbeef deadbeef deadbeef deadbeef |................| + 000050: deadbeef deadbeef deadbeef deadbeef |................| + 000060: deadbeef deadbeef deadbeef deadbeef |................| + 000070: deadbeef deadbeef deadbeef deadbeef |................| + 000080: deadbeef deadbeef deadbeef deadbeef |................| + 000090: deadbeef deadbeef deadbeef deadbeef |................| + 0000a0: deadbeef deadbeef deadbeef deadbeef |................| + 0000b0: deadbeef deadbeef deadbeef deadbeef |................| + 0000c0: deadbeef deadbeef deadbeef deadbeef |................| + 0000d0: deadbeef deadbeef deadbeef deadbeef |................| + 0000e0: deadbeef deadbeef deadbeef deadbeef |................| + 0000f0: deadbeef deadbeef deadbeef deadbeef |................| + 000100: deadbeef deadbeef deadbeef deadbeef |................| + 000110: deadbeef deadbeef deadbeef deadbeef |................| + 000120: deadbeef deadbeef deadbeef deadbeef |................| + 000130: deadbeef deadbeef deadbeef deadbeef |................| + 000140: deadbeef deadbeef deadbeef deadbeef |................| + 000150: deadbeef deadbeef deadbeef deadbeef |................| + 000160: deadbeef deadbeef deadbeef deadbeef |................| + 000170: deadbeef deadbeef deadbeef deadbeef |................| + 000180: deadbeef deadbeef deadbeef deadbeef |................| + 000190: deadbeef deadbeef deadbeef deadbeef |................| + 0001a0: deadbeef deadbeef deadbeef deadbeef |................| + 0001b0: deadbeef deadbeef deadbeef deadbeef |................| + 0001c0: deadbeef deadbeef deadbeef deadbeef |................| + 0001d0: deadbeef deadbeef deadbeef deadbeef |................| + 0001e0: deadbeef deadbeef deadbeef deadbeef |................| + 0001f0: deadbeef deadbeef deadbeef deadbeef |................| + 000200: deadbeef deadbeef deadbeef deadbeef |................| + 000210: deadbeef deadbeef deadbeef deadbeef |................| + 000220: deadbeef deadbeef deadbeef deadbeef |................| + 000230: deadbeef deadbeef deadbeef deadbeef |................| + 000240: deadbeef deadbeef deadbeef deadbeef |................| + 000250: deadbeef deadbeef deadbeef deadbeef |................| + 000260: deadbeef deadbeef deadbeef deadbeef |................| + 000270: deadbeef deadbeef deadbeef deadbeef |................| + 000280: deadbeef deadbeef deadbeef deadbeef |................| + 000290: deadbeef deadbeef deadbeef deadbeef |................| + 0002a0: deadbeef deadbeef deadbeef deadbeef |................| + 0002b0: deadbeef deadbeef deadbeef deadbeef |................| + 0002c0: deadbeef deadbeef deadbeef deadbeef |................| + 0002d0: deadbeef deadbeef deadbeef deadbeef |................| + 0002e0: deadbeef deadbeef deadbeef deadbeef |................| + 0002f0: deadbeef deadbeef deadbeef deadbeef |................| + 000300: deadbeef deadbeef deadbeef deadbeef |................| + 000310: deadbeef deadbeef deadbeef deadbeef |................| + 000320: deadbeef deadbeef deadbeef deadbeef |................| + 000330: deadbeef deadbeef deadbeef deadbeef |................| + 000340: deadbeef deadbeef deadbeef deadbeef |................| + 000350: deadbeef deadbeef deadbeef deadbeef |................| + 000360: deadbeef deadbeef deadbeef deadbeef |................| + 000370: deadbeef deadbeef deadbeef deadbeef |................| + 000380: deadbeef deadbeef deadbeef deadbeef |................| + 000390: deadbeef deadbeef deadbeef deadbeef |................| + 0003a0: deadbeef deadbeef deadbeef deadbeef |................| + 0003b0: deadbeef deadbeef deadbeef deadbeef |................| + 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deadbeef deadbeef |................| + 0004c0: deadbeef deadbeef deadbeef deadbeef |................| + 0004d0: deadbeef deadbeef deadbeef deadbeef |................| + 0004e0: deadbeef deadbeef deadbeef deadbeef |................| + 0004f0: deadbeef deadbeef deadbeef deadbeef |................| + 000500: deadbeef deadbeef deadbeef deadbeef |................| + 000510: deadbeef deadbeef deadbeef deadbeef |................| + 000520: deadbeef deadbeef deadbeef deadbeef |................| + 000530: deadbeef deadbeef deadbeef deadbeef |................| + 000540: deadbeef deadbeef deadbeef deadbeef |................| + 000550: deadbeef deadbeef deadbeef deadbeef |................| + 000560: deadbeef deadbeef deadbeef deadbeef |................| + 000570: deadbeef deadbeef deadbeef deadbeef |................| + 000580: deadbeef deadbeef deadbeef deadbeef |................| + 000590: deadbeef deadbeef deadbeef deadbeef |................| + 0005a0: deadbeef deadbeef deadbeef deadbeef |................| + 0005b0: deadbeef deadbeef deadbeef deadbeef |................| + 0005c0: deadbeef deadbeef deadbeef deadbeef |................| + 0005d0: deadbeef deadbeef deadbeef deadbeef |................| + 0005e0: deadbeef deadbeef deadbeef deadbeef |................| + 0005f0: deadbeef deadbeef deadbeef deadbeef |................| + 000600: deadbeef deadbeef deadbeef deadbeef |................| + 000610: deadbeef deadbeef deadbeef deadbeef |................| + 000620: deadbeef deadbeef deadbeef deadbeef |................| + 000630: deadbeef deadbeef deadbeef deadbeef |................| + 000640: deadbeef deadbeef deadbeef deadbeef |................| + 000650: deadbeef deadbeef deadbeef deadbeef |................| + 000660: deadbeef deadbeef deadbeef deadbeef |................| + 000670: deadbeef deadbeef deadbeef deadbeef |................| + 000680: deadbeef deadbeef deadbeef deadbeef |................| + 000690: deadbeef deadbeef deadbeef deadbeef |................| + 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deadbeef deadbeef |................| + 0007a0: deadbeef deadbeef deadbeef deadbeef |................| + 0007b0: deadbeef deadbeef deadbeef deadbeef |................| + 0007c0: deadbeef deadbeef deadbeef deadbeef |................| + 0007d0: deadbeef deadbeef deadbeef deadbeef |................| + 0007e0: deadbeef deadbeef deadbeef deadbeef |................| + 0007f0: deadbeef deadbeef deadbeef deadbeef |................| + 000800: deafbead deafbead deafbead deafbead |................| + 000810: deafbead deafbead deafbead deafbead |................| + 000820: deafbead deafbead deafbead deafbead |................| + 000830: deafbead deafbead deafbead deafbead |................| + 000840: deafbead deafbead deafbead deafbead |................| + 000850: deafbead deafbead deafbead deafbead |................| + 000860: deafbead deafbead deafbead deafbead |................| + 000870: deafbead deafbead deafbead deafbead |................| + 000880: deafbead deafbead deafbead deafbead |................| + 000890: deafbead deafbead deafbead deafbead |................| + 0008a0: deafbead deafbead deafbead deafbead |................| + 0008b0: deafbead deafbead deafbead deafbead |................| + 0008c0: deafbead deafbead deafbead deafbead |................| + 0008d0: deafbead deafbead deafbead deafbead |................| + 0008e0: deafbead deafbead deafbead deafbead |................| + 0008f0: deafbead deafbead deafbead deafbead |................| + 000900: deafbead deafbead deafbead deafbead |................| + 000910: deafbead deafbead deafbead deafbead |................| + 000920: deafbead deafbead deafbead deafbead |................| + 000930: deafbead deafbead deafbead deafbead |................| + 000940: deafbead deafbead deafbead deafbead |................| + 000950: deafbead deafbead deafbead deafbead |................| + 000960: deafbead deafbead deafbead deafbead |................| + 000970: deafbead deafbead deafbead deafbead |................| + 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|................| + 000b70: deafbead deafbead deafbead deafbead |................| + 000b80: deafbead deafbead deafbead deafbead |................| + 000b90: deafbead deafbead deafbead deafbead |................| + 000ba0: deafbead deafbead deafbead deafbead |................| + 000bb0: deafbead deafbead deafbead deafbead |................| + 000bc0: deafbead deafbead deafbead deafbead |................| + 000bd0: deafbead deafbead deafbead deafbead |................| + 000be0: deafbead deafbead deafbead deafbead |................| + 000bf0: deafbead deafbead deafbead deafbead |................| + 000c00: deafbead deafbead deafbead deafbead |................| + 000c10: deafbead deafbead deafbead deafbead |................| + 000c20: deafbead deafbead deafbead deafbead |................| + 000c30: deafbead deafbead deafbead deafbead |................| + 000c40: deafbead deafbead deafbead deafbead |................| + 000c50: deafbead deafbead deafbead deafbead |................| + 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00100002 001c8100 00200020 00000000 |........ . .....| + 001720: 00002000 00100081 00000008 00000000 |. ..............| + 001730: 00000024 00009420 00002010 00000100 |$... .... ......| + 001740: 00000000 00004188 00002000 00100000 |.....A... ......| + 001750: 00040000 00120102 00000000 00040002 |................| + 001760: 00210201 00224200 00040000 00000200 |..!..B".........| + 001770: 00000000 0000000c 00005000 00000000 |.........P......| + 001780: 00010200 00082208 00000000 00194011 |.....".......@..| + 001790: 00000502 00012100 00040050 00000240 |.....!..P...@...| + 0017a0: 00004180 00080211 00001008 00000000 |.A..............| + 0017b0: 002004a0 00020490 00001080 00210004 |.. ...........!.| + 0017c0: 00300040 00000000 00000020 00008002 |@.0..... .......| + 0017d0: 00041098 00000000 00000000 002000a0 |.............. .| + 0017e0: 000c0400 00000000 00000402 00000401 |................| + 0017f0: 00200400 00002000 00001000 00000101 |.. .. ..........| + 001800: 00000000 00000000 00000000 00000000 |................| + 001810: 00000000 00000000 00000000 00000000 |................| + 001820: 00000000 00000000 00000000 00000000 |................| + 001830: 00000000 00000000 00000000 00000000 |................| + 001840: 00000000 00000000 00000000 00000000 |................| + 001850: 00000000 00000000 00000000 00000000 |................| + 001860: 00000000 00000000 00000000 00000000 |................| + 001870: 00000000 00000000 00000000 00000000 |................| + 001880: 00000000 00000000 00000000 00000000 |................| + 001890: 00000000 00000000 00000000 00000000 |................| + 0018a0: 00000000 00000000 00000000 00000000 |................| + 0018b0: 00000000 00000000 00000000 00000000 |................| + 0018c0: 00000000 00000000 00000000 00000000 |................| + 0018d0: 00000000 00000000 00000000 00000000 |................| + 0018e0: 00000000 00000000 00000000 00000000 |................| + 0018f0: 00000000 00000000 00000000 00000000 |................| + 001900: 00000000 00000000 00000000 00000000 |................| + 001910: 00000000 00000000 00000000 00000000 |................| + 001920: 00000000 00000000 00000000 00000000 |................| + 001930: 00000000 00000000 00000000 00000000 |................| + 001940: 00000000 00000000 00000000 00000000 |................| + 001950: 00000000 00000000 00000000 00000000 |................| + 001960: 00000000 00000000 00000000 00000000 |................| + 001970: 00000000 00000000 00000000 00000000 |................| + 001980: 00000000 00000000 00000000 00000000 |................| + 001990: 00000000 00000000 00000000 00000000 |................| + 0019a0: 00000000 00000000 00000000 00000000 |................| + 0019b0: 00000000 00000000 00000000 00000000 |................| + 0019c0: 00000000 00000000 00000000 00000000 |................| + 0019d0: 00000000 00000000 00000000 00000000 |................| + 0019e0: 00000000 00000000 00000000 00000000 |................| + 0019f0: 00000000 00000000 00000000 00000000 |................| + 001a00: 00000000 00000000 00000000 00000000 |................| + 001a10: 00000000 00000000 00000000 00000000 |................| + 001a20: 00000000 00000000 00000000 00000000 |................| + 001a30: 00000000 00000000 00000000 00000000 |................| + 001a40: 00000000 00000000 00000000 00000000 |................| + 001a50: 00000000 00000000 00000000 00000000 |................| + 001a60: 00000000 00000000 00000000 00000000 |................| + 001a70: 00000000 00000000 00000000 00000000 |................| + 001a80: 00000000 00000000 00000000 00000000 |................| + 001a90: 00000000 00000000 00000000 00000000 |................| + 001aa0: 00000000 00000000 00000000 00000000 |................| + 001ab0: 00000000 00000000 00000000 00000000 |................| + 001ac0: 00000000 00000000 00000000 00000000 |................| + 001ad0: 00000000 00000000 00000000 00000000 |................| + 001ae0: 00000000 00000000 00000000 00000000 |................| + 001af0: 00000000 00000000 00000000 00000000 |................| + 001b00: 00000000 00000000 00000000 00000000 |................| + 001b10: 00000000 00000000 00000000 00000000 |................| + 001b20: 00000000 00000000 00000000 00000000 |................| + 001b30: 00000000 00000000 00000000 00000000 |................| + 001b40: 00000000 00000000 00000000 00000000 |................| + 001b50: 00000000 00000000 00000000 00000000 |................| + 001b60: 00000000 00000000 00000000 00000000 |................| + 001b70: 00000000 00000000 00000000 00000000 |................| + 001b80: 00000000 00000000 00000000 00000000 |................| + 001b90: 00000000 00000000 00000000 00000000 |................| + 001ba0: 00000000 00000000 00000000 00000000 |................| + 001bb0: 00000000 00000000 00000000 00000000 |................| + 001bc0: 00000000 00000000 00000000 00000000 |................| + 001bd0: 00000000 00000000 00000000 00000000 |................| + 001be0: 00000000 00000000 00000000 00000000 |................| + 001bf0: 00000000 00000000 00000000 00000000 |................| + 001c00: 00000000 00000000 00000000 00000000 |................| + 001c10: 00000000 00000000 00000000 00000000 |................| + 001c20: 00000000 00000000 00000000 00000000 |................| + 001c30: 00000000 00000000 00000000 00000000 |................| + 001c40: 00000000 00000000 00000000 00000000 |................| + 001c50: 00000000 00000000 00000000 00000000 |................| + 001c60: 00000000 00000000 00000000 00000000 |................| + 001c70: 00000000 00000000 00000000 00000000 |................| + 001c80: 00000000 00000000 00000000 00000000 |................| + 001c90: 00000000 00000000 00000000 00000000 |................| + 001ca0: 00000000 00000000 00000000 00000000 |................| + 001cb0: 00000000 00000000 00000000 00000000 |................| + 001cc0: 00000000 00000000 00000000 00000000 |................| + 001cd0: 00000000 00000000 00000000 00000000 |................| + 001ce0: 00000000 00000000 00000000 00000000 |................| + 001cf0: 00000000 00000000 00000000 00000000 |................| + 001d00: 00000000 00000000 00000000 00000000 |................| + 001d10: 00000000 00000000 00000000 00000000 |................| + 001d20: 00000000 00000000 00000000 00000000 |................| + 001d30: 00000000 00000000 00000000 00000000 |................| + 001d40: 00000000 00000000 00000000 00000000 |................| + 001d50: 00000000 00000000 00000000 00000000 |................| + 001d60: 00000000 00000000 00000000 00000000 |................| + 001d70: 00000000 00000000 00000000 00000000 |................| + 001d80: 00000000 00000000 00000000 00000000 |................| + 001d90: 00000000 00000000 00000000 00000000 |................| + 001da0: 00000000 00000000 00000000 00000000 |................| + 001db0: 00000000 00000000 00000000 00000000 |................| + 001dc0: 00000000 00000000 00000000 00000000 |................| + 001dd0: 00000000 00000000 00000000 00000000 |................| + 001de0: 00000000 00000000 00000000 00000000 |................| + 001df0: 00000000 00000000 00000000 00000000 |................| + 001e00: 00000000 00000000 00000000 00000000 |................| + 001e10: 00000000 00000000 00000000 00000000 |................| + 001e20: 00000000 00000000 00000000 00000000 |................| + 001e30: 00000000 00000000 00000000 00000000 |................| + 001e40: 00000000 00000000 00000000 00000000 |................| + 001e50: 00000000 00000000 00000000 00000000 |................| + 001e60: 00000000 00000000 00000000 00000000 |................| + 001e70: 00000000 00000000 00000000 00000000 |................| + 001e80: 00000000 00000000 00000000 00000000 |................| + 001e90: 00000000 00000000 00000000 00000000 |................| + 001ea0: 00000000 00000000 00000000 00000000 |................| + 001eb0: 00000000 00000000 00000000 00000000 |................| + 001ec0: 00000000 00000000 00000000 00000000 |................| + 001ed0: 00000000 00000000 00000000 00000000 |................| + 001ee0: 00000000 00000000 00000000 00000000 |................| + 001ef0: 00000000 00000000 00000000 00000000 |................| + 001f00: 00000000 00000000 00000000 00000000 |................| + 001f10: 00000000 00000000 00000000 00000000 |................| + 001f20: 00000000 00000000 00000000 00000000 |................| + 001f30: 00000000 00000000 00000000 00000000 |................| + 001f40: 00000000 00000000 00000000 00000000 |................| + 001f50: 00000000 00000000 00000000 00000000 |................| + 001f60: 00000000 00000000 00000000 00000000 |................| + 001f70: 00000000 00000000 00000000 00000000 |................| + 001f80: 00000000 00000000 00000000 00000000 |................| + 001f90: 00000000 00000000 00000000 00000000 |................| + 001fa0: 00000000 00000000 00000000 00000000 |................| + 001fb0: 00000000 00000000 00000000 00000000 |................| + 001fc0: 00000000 00000000 00000000 00000000 |................| + 001fd0: 00000000 00000000 00000000 00000000 |................| + 001fe0: 00000000 00000000 00000000 00000000 |................| + 001ff0: 00000000 00000000 00000000 00000000 |................| + - bank: 2 + size: 2048 + - type: A6XX_HLSQ_GFX_CVS_CONST_RAM + - bank: 0 + size: 2048 + - bank: 1 + size: 2048 + - bank: 2 + size: 2048 + - type: A6XX_HLSQ_GFX_CPS_CONST_RAM + - bank: 0 + size: 2048 + - bank: 1 + size: 2048 + - bank: 2 + size: 2048 + - type: A6XX_HLSQ_CVS_MISC_RAM_TAG + - bank: 0 + size: 8 + - bank: 1 + size: 8 + - bank: 2 + size: 8 + - type: A6XX_HLSQ_CPS_MISC_RAM_TAG + - bank: 0 + size: 4 + - bank: 1 + size: 4 + - bank: 2 + size: 4 + - type: A6XX_HLSQ_INST_RAM_TAG + - bank: 0 + size: 128 + - bank: 1 + size: 128 + - bank: 2 + size: 128 + - type: A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG + - bank: 0 + size: 12 + - bank: 1 + size: 12 + - bank: 2 + size: 12 + - type: A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG + - bank: 0 + size: 16 + - bank: 1 + size: 16 + - bank: 2 + size: 16 + - type: A6XX_HLSQ_PWR_REST_RAM + - bank: 0 + size: 40 + - bank: 1 + size: 40 + - bank: 2 + size: 40 + - type: A6XX_HLSQ_PWR_REST_TAG + - bank: 0 + size: 20 + - bank: 1 + size: 20 + - bank: 2 + size: 20 + - type: A6XX_HLSQ_DATAPATH_META + - bank: 0 + size: 64 + - bank: 1 + size: 64 + - bank: 2 + size: 64 + - type: A6XX_HLSQ_FRONTEND_META + - bank: 0 + size: 64 + - bank: 1 + size: 64 + - bank: 2 + size: 64 + - type: A6XX_HLSQ_INDIRECT_META + - bank: 0 + size: 64 + - bank: 1 + size: 64 + - bank: 2 + size: 64 +clusters: + - cluster-name: CLUSTER_GRAS + - context: 0 + 00000000 GRAS_CL_CNTL: { 0 } + 00000000 GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } + 00000000 GRAS_DS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } + 00000000 GRAS_GS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } + 00000000 GRAS_MAX_LAYER_INDEX: 0 + 00000000 GRAS_CNTL: { COORD_MASK = 0 } + 00000000 GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 0 | VERT = 0 } + 17ed48d5 GRAS_CL_VPORT[0].XOFFSET: 0.000000 + 1367ce4f GRAS_CL_VPORT[0].XSCALE: 0.000000 + 41486258 GRAS_CL_VPORT[0].YOFFSET: 12.524010 + a77c9dfe GRAS_CL_VPORT[0].YSCALE: -0.000000 + 4e1a2221 GRAS_CL_VPORT[0].ZOFFSET: 646481984.000000 + 25ad942d GRAS_CL_VPORT[0].ZSCALE: 0.000000 + b98dd337 GRAS_CL_VPORT[0x1].XOFFSET: -0.000271 + f3b29a4b GRAS_CL_VPORT[0x1].XSCALE: -28300728576976020658845084811264.000000 + 03c125ba GRAS_CL_VPORT[0x1].YOFFSET: 0.000000 + 9fd9154a GRAS_CL_VPORT[0x1].YSCALE: -0.000000 + 99e9ef18 GRAS_CL_VPORT[0x1].ZOFFSET: -0.000000 + cfa33a37 GRAS_CL_VPORT[0x1].ZSCALE: -5477002752.000000 + c08d010f GRAS_CL_VPORT[0x2].XOFFSET: -4.406379 + ec058c04 GRAS_CL_VPORT[0x2].XSCALE: -645793356413294901616181248.000000 + a095f8f2 GRAS_CL_VPORT[0x2].YOFFSET: -0.000000 + dd963bbd GRAS_CL_VPORT[0x2].YSCALE: -1353181742126596096.000000 + c8e17162 GRAS_CL_VPORT[0x2].ZOFFSET: -461707.062500 + c5f8656e GRAS_CL_VPORT[0x2].ZSCALE: -7948.678711 + 193ca252 GRAS_CL_VPORT[0x3].XOFFSET: 0.000000 + c276e62a GRAS_CL_VPORT[0x3].XSCALE: -61.724770 + 4aae8197 GRAS_CL_VPORT[0x3].YOFFSET: 5718219.500000 + a2a2312c GRAS_CL_VPORT[0x3].YSCALE: -0.000000 + 86a6e32d GRAS_CL_VPORT[0x3].ZOFFSET: -0.000000 + 2be1d796 GRAS_CL_VPORT[0x3].ZSCALE: 0.000000 + d1743060 GRAS_CL_VPORT[0x4].XOFFSET: -65548976128.000000 + 7c3d4406 GRAS_CL_VPORT[0x4].XSCALE: 3930895141940423283868471122294996992.000000 + 562e9a08 GRAS_CL_VPORT[0x4].YOFFSET: 47994145603584.000000 + fa7f4af3 GRAS_CL_VPORT[0x4].YSCALE: -331388962420135558780170972931555328.000000 + 0b2e288f GRAS_CL_VPORT[0x4].ZOFFSET: 0.000000 + 85c75124 GRAS_CL_VPORT[0x4].ZSCALE: -0.000000 + 94887ab4 GRAS_CL_VPORT[0x5].XOFFSET: -0.000000 + 1356de8c GRAS_CL_VPORT[0x5].XSCALE: 0.000000 + 14ff583b GRAS_CL_VPORT[0x5].YOFFSET: 0.000000 + 17ba9c47 GRAS_CL_VPORT[0x5].YSCALE: 0.000000 + c1dfc3da GRAS_CL_VPORT[0x5].ZOFFSET: -27.970631 + 2dc39521 GRAS_CL_VPORT[0x5].ZSCALE: 0.000000 + f1f2da44 GRAS_CL_VPORT[0x6].XOFFSET: -2405095658443594589675439783936.000000 + d68f795b GRAS_CL_VPORT[0x6].XSCALE: -78875690270720.000000 + c929b829 GRAS_CL_VPORT[0x6].YOFFSET: -695170.562500 + b174d59e GRAS_CL_VPORT[0x6].YSCALE: -0.000000 + 20b86447 GRAS_CL_VPORT[0x6].ZOFFSET: 0.000000 + 7cf5f63e GRAS_CL_VPORT[0x6].ZSCALE: 10216856921996855714425547393601634304.000000 + 25f487a0 GRAS_CL_VPORT[0x7].XOFFSET: 0.000000 + ff2b5fb1 GRAS_CL_VPORT[0x7].XSCALE: -227794845467281269236926443122692456448.000000 + 664b93c1 GRAS_CL_VPORT[0x7].YOFFSET: 240341493629255650639872.000000 + 078173fc GRAS_CL_VPORT[0x7].YSCALE: 0.000000 + ad12ea8c GRAS_CL_VPORT[0x7].ZOFFSET: -0.000000 + 6556977c GRAS_CL_VPORT[0x7].ZSCALE: 63336301301930932568064.000000 + 827e4c57 GRAS_CL_VPORT[0x8].XOFFSET: -0.000000 + d1fdee5f GRAS_CL_VPORT[0x8].XSCALE: -136328241152.000000 + 0a990478 GRAS_CL_VPORT[0x8].YOFFSET: 0.000000 + e3a19cf1 GRAS_CL_VPORT[0x8].YSCALE: -5962469232013083672576.000000 + 27db13b2 GRAS_CL_VPORT[0x8].ZOFFSET: 0.000000 + e719d958 GRAS_CL_VPORT[0x8].ZSCALE: -726531356411326028054528.000000 + 69da20dc GRAS_CL_VPORT[0x9].XOFFSET: 32962625335892150604267520.000000 + 890e59b0 GRAS_CL_VPORT[0x9].XSCALE: -0.000000 + 4c0ab84c GRAS_CL_VPORT[0x9].YOFFSET: 36364592.000000 + 587215e3 GRAS_CL_VPORT[0x9].YSCALE: 1064703266652160.000000 + 11e06c70 GRAS_CL_VPORT[0x9].ZOFFSET: 0.000000 + e7b1dbe6 GRAS_CL_VPORT[0x9].ZSCALE: -1679830555333396636106752.000000 + b78bc0aa GRAS_CL_VPORT[0xa].XOFFSET: -0.000017 + ac39bee4 GRAS_CL_VPORT[0xa].XSCALE: -0.000000 + ea76ea04 GRAS_CL_VPORT[0xa].YOFFSET: -74625214792291642198982656.000000 + 10ba9db3 GRAS_CL_VPORT[0xa].YSCALE: 0.000000 + 140034d1 GRAS_CL_VPORT[0xa].ZOFFSET: 0.000000 + d07fe121 GRAS_CL_VPORT[0xa].ZSCALE: -17171776512.000000 + 500ea138 GRAS_CL_VPORT[0xb].XOFFSET: 9571721216.000000 + 9e4f11a4 GRAS_CL_VPORT[0xb].XSCALE: -0.000000 + 8522222a GRAS_CL_VPORT[0xb].YOFFSET: -0.000000 + 31c8f926 GRAS_CL_VPORT[0xb].YSCALE: 0.000000 + c1233a11 GRAS_CL_VPORT[0xb].ZOFFSET: -10.201676 + eff95dd8 GRAS_CL_VPORT[0xb].ZSCALE: -154350435155798764938168631296.000000 + 2034c3cf GRAS_CL_VPORT[0xc].XOFFSET: 0.000000 + 35507804 GRAS_CL_VPORT[0xc].XSCALE: 0.000001 + b840b0d8 GRAS_CL_VPORT[0xc].YOFFSET: -0.000046 + ebf33447 GRAS_CL_VPORT[0xc].YSCALE: -588031693884586688765755392.000000 + 0bd54c04 GRAS_CL_VPORT[0xc].ZOFFSET: 0.000000 + 119b3bf4 GRAS_CL_VPORT[0xc].ZSCALE: 0.000000 + cc01323b GRAS_CL_VPORT[0xd].XOFFSET: -33868012.000000 + cf9fc237 GRAS_CL_VPORT[0xd].XSCALE: -5360610816.000000 + a0a0c6dc GRAS_CL_VPORT[0xd].YOFFSET: -0.000000 + 6578bdca GRAS_CL_VPORT[0xd].YSCALE: 73415492375974923730944.000000 + 1c183c97 GRAS_CL_VPORT[0xd].ZOFFSET: 0.000000 + 77907cd1 GRAS_CL_VPORT[0xd].ZSCALE: 5861111914889323960058734228537344.000000 + 9b76c406 GRAS_CL_VPORT[0xe].XOFFSET: -0.000000 + f59eb4eb GRAS_CL_VPORT[0xe].XSCALE: -402369314450854940480206742224896.000000 + 552bc020 GRAS_CL_VPORT[0xe].YOFFSET: 11802603683840.000000 + 73ce4f77 GRAS_CL_VPORT[0xe].YSCALE: 32691189311773747891142203015168.000000 + 11c1e3ea GRAS_CL_VPORT[0xe].ZOFFSET: 0.000000 + 067875da GRAS_CL_VPORT[0xe].ZSCALE: 0.000000 + de4491a7 GRAS_CL_VPORT[0xf].XOFFSET: -3541071480374689792.000000 + 7cb2fd6e GRAS_CL_VPORT[0xf].XSCALE: 7434952044374398076582578328088608768.000000 + 889d9245 GRAS_CL_VPORT[0xf].YOFFSET: -0.000000 + fc17a576 GRAS_CL_VPORT[0xf].YSCALE: -3149571088586152722879569121442267136.000000 + c2622832 GRAS_CL_VPORT[0xf].ZOFFSET: -56.539253 + 4f4fbf73 GRAS_CL_VPORT[0xf].ZSCALE: 3485430528.000000 + 00000000 GRAS_CL_Z_CLAMP[0].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x1].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x1].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x2].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x2].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x3].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x3].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x4].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x4].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x5].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x5].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x6].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x6].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x7].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x7].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x8].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x8].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x9].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x9].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xa].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xa].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xb].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xb].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xc].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xc].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xd].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xd].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xe].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xe].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xf].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xf].MAX: 0.000000 + 00000010 GRAS_SU_CNTL: { LINEHALFWIDTH = 0.500000 } + 00000000 GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } + 00000000 GRAS_SU_POINT_SIZE: 0.000000 + 00000000 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } + 00000000 GRAS_UNKNOWN_8099: 0 + 00000000 GRAS_UNKNOWN_809A: 0 + 00000000 GRAS_VS_LAYER_CNTL: { 0 } + 00000000 GRAS_GS_LAYER_CNTL: { 0 } + 00000000 GRAS_DS_LAYER_CNTL: { 0 } + 00000002 GRAS_UNKNOWN_80A0: 0x2 + 00000101 GRAS_BIN_CONTROL: { BINW = 32 | BINH = 16 } + 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 GRAS_SAMPLE_CONFIG: { 0 } + 00000000 GRAS_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 GRAS_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 GRAS_UNKNOWN_80AF: FALSE + 8c629e81 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 40577 | Y = 35938 } + fdee19a0 GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 6560 | Y = 65006 } + 8867136c GRAS_SC_SCREEN_SCISSOR[0x1].TL: { X = 4972 | Y = 34919 } + eeec2862 GRAS_SC_SCREEN_SCISSOR[0x1].BR: { X = 10338 | Y = 61164 } + 00988003 GRAS_SC_SCREEN_SCISSOR[0x2].TL: { X = 32771 | Y = 152 } + d3afa781 GRAS_SC_SCREEN_SCISSOR[0x2].BR: { X = 42881 | Y = 54191 } + d3f53b55 GRAS_SC_SCREEN_SCISSOR[0x3].TL: { X = 15189 | Y = 54261 } + a33d5eb3 GRAS_SC_SCREEN_SCISSOR[0x3].BR: { X = 24243 | Y = 41789 } + 23d08b45 GRAS_SC_SCREEN_SCISSOR[0x4].TL: { X = 35653 | Y = 9168 } + 14f61e22 GRAS_SC_SCREEN_SCISSOR[0x4].BR: { X = 7714 | Y = 5366 } + 643c0204 GRAS_SC_SCREEN_SCISSOR[0x5].TL: { X = 516 | Y = 25660 } + a9facb6e GRAS_SC_SCREEN_SCISSOR[0x5].BR: { X = 52078 | Y = 43514 } + d2e1d872 GRAS_SC_SCREEN_SCISSOR[0x6].TL: { X = 55410 | Y = 53985 } + 94cdd4fd GRAS_SC_SCREEN_SCISSOR[0x6].BR: { X = 54525 | Y = 38093 } + de0d1b35 GRAS_SC_SCREEN_SCISSOR[0x7].TL: { X = 6965 | Y = 56845 } + 237c51d7 GRAS_SC_SCREEN_SCISSOR[0x7].BR: { X = 20951 | Y = 9084 } + cbf20742 GRAS_SC_SCREEN_SCISSOR[0x8].TL: { X = 1858 | Y = 52210 } + 352bb4fc GRAS_SC_SCREEN_SCISSOR[0x8].BR: { X = 46332 | Y = 13611 } + a5a59c55 GRAS_SC_SCREEN_SCISSOR[0x9].TL: { X = 40021 | Y = 42405 } + 07da59a6 GRAS_SC_SCREEN_SCISSOR[0x9].BR: { X = 22950 | Y = 2010 } + 8d709172 GRAS_SC_SCREEN_SCISSOR[0xa].TL: { X = 37234 | Y = 36208 } + 848ffffe GRAS_SC_SCREEN_SCISSOR[0xa].BR: { X = 65534 | Y = 33935 } + 8c0b18da GRAS_SC_SCREEN_SCISSOR[0xb].TL: { X = 6362 | Y = 35851 } + e75d13c3 GRAS_SC_SCREEN_SCISSOR[0xb].BR: { X = 5059 | Y = 59229 } + 114252db GRAS_SC_SCREEN_SCISSOR[0xc].TL: { X = 21211 | Y = 4418 } + c427b17e GRAS_SC_SCREEN_SCISSOR[0xc].BR: { X = 45438 | Y = 50215 } + 31c1fc95 GRAS_SC_SCREEN_SCISSOR[0xd].TL: { X = 64661 | Y = 12737 } + ae47e0b7 GRAS_SC_SCREEN_SCISSOR[0xd].BR: { X = 57527 | Y = 44615 } + 13283829 GRAS_SC_SCREEN_SCISSOR[0xe].TL: { X = 14377 | Y = 4904 } + d5eafd7f GRAS_SC_SCREEN_SCISSOR[0xe].BR: { X = 64895 | Y = 54762 } + ac0886f7 GRAS_SC_SCREEN_SCISSOR[0xf].TL: { X = 34551 | Y = 44040 } + 7bedbdb2 GRAS_SC_SCREEN_SCISSOR[0xf].BR: { X = 48562 | Y = 31725 } + c487b444 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 46148 | Y = 50311 } + df46330f GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 13071 | Y = 57158 } + 1b1da288 GRAS_SC_VIEWPORT_SCISSOR[0x1].TL: { X = 41608 | Y = 6941 } + 375f7ebc GRAS_SC_VIEWPORT_SCISSOR[0x1].BR: { X = 32444 | Y = 14175 } + 73ba19e8 GRAS_SC_VIEWPORT_SCISSOR[0x2].TL: { X = 6632 | Y = 29626 } + ef6c9650 GRAS_SC_VIEWPORT_SCISSOR[0x2].BR: { X = 38480 | Y = 61292 } + 22d60948 GRAS_SC_VIEWPORT_SCISSOR[0x3].TL: { X = 2376 | Y = 8918 } + 5c2f6e10 GRAS_SC_VIEWPORT_SCISSOR[0x3].BR: { X = 28176 | Y = 23599 } + 8e231280 GRAS_SC_VIEWPORT_SCISSOR[0x4].TL: { X = 4736 | Y = 36387 } + fa6bbe2a GRAS_SC_VIEWPORT_SCISSOR[0x4].BR: { X = 48682 | Y = 64107 } + 015d816e GRAS_SC_VIEWPORT_SCISSOR[0x5].TL: { X = 33134 | Y = 349 } + 3dfdfa2d GRAS_SC_VIEWPORT_SCISSOR[0x5].BR: { X = 64045 | Y = 15869 } + 3610960b GRAS_SC_VIEWPORT_SCISSOR[0x6].TL: { X = 38411 | Y = 13840 } + 9b769a89 GRAS_SC_VIEWPORT_SCISSOR[0x6].BR: { X = 39561 | Y = 39798 } + a85a55b3 GRAS_SC_VIEWPORT_SCISSOR[0x7].TL: { X = 21939 | Y = 43098 } + ca868126 GRAS_SC_VIEWPORT_SCISSOR[0x7].BR: { X = 33062 | Y = 51846 } + 8d20cea5 GRAS_SC_VIEWPORT_SCISSOR[0x8].TL: { X = 52901 | Y = 36128 } + be4af7fa GRAS_SC_VIEWPORT_SCISSOR[0x8].BR: { X = 63482 | Y = 48714 } + 41588113 GRAS_SC_VIEWPORT_SCISSOR[0x9].TL: { X = 33043 | Y = 16728 } + eb5bb66a GRAS_SC_VIEWPORT_SCISSOR[0x9].BR: { X = 46698 | Y = 60251 } + 40667101 GRAS_SC_VIEWPORT_SCISSOR[0xa].TL: { X = 28929 | Y = 16486 } + 19e09698 GRAS_SC_VIEWPORT_SCISSOR[0xa].BR: { X = 38552 | Y = 6624 } + 88c11d03 GRAS_SC_VIEWPORT_SCISSOR[0xb].TL: { X = 7427 | Y = 35009 } + fad7dbc7 GRAS_SC_VIEWPORT_SCISSOR[0xb].BR: { X = 56263 | Y = 64215 } + 10204eb9 GRAS_SC_VIEWPORT_SCISSOR[0xc].TL: { X = 20153 | Y = 4128 } + 53fcd9da GRAS_SC_VIEWPORT_SCISSOR[0xc].BR: { X = 55770 | Y = 21500 } + 4d592181 GRAS_SC_VIEWPORT_SCISSOR[0xd].TL: { X = 8577 | Y = 19801 } + ed40b570 GRAS_SC_VIEWPORT_SCISSOR[0xd].BR: { X = 46448 | Y = 60736 } + 00745b64 GRAS_SC_VIEWPORT_SCISSOR[0xe].TL: { X = 23396 | Y = 116 } + 27fbffdc GRAS_SC_VIEWPORT_SCISSOR[0xe].BR: { X = 65500 | Y = 10235 } + ac66bcc7 GRAS_SC_VIEWPORT_SCISSOR[0xf].TL: { X = 48327 | Y = 44134 } + 790cdf93 GRAS_SC_VIEWPORT_SCISSOR[0xf].BR: { X = 57235 | Y = 30988 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } + 00000000 GRAS_SC_WINDOW_SCISSOR_BR: { X = 0 | Y = 0 } + 00000000 GRAS_LRZ_CNTL: { 0 } + 00000000 GRAS_UNKNOWN_8101: 0 + 00000000 GRAS_2D_BLIT_INFO: { COLOR_FORMAT = 0 } + 00000000 GRAS_LRZ_BUFFER_BASE_LO: 0 + 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0 + 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0 + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 + 00000000 GRAS_SAMPLE_CNTL: { 0 } + 00000000 GRAS_UNKNOWN_8110: 0 + 00000000 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW } + 00000000 GRAS_2D_SRC_TL_X: 0 + 00000000 GRAS_2D_SRC_BR_X: 0 + 00000000 GRAS_2D_SRC_TL_Y: 0 + 00000000 GRAS_2D_SRC_BR_Y: 0 + 00000000 GRAS_2D_DST_TL: { X = 0 | Y = 0 } + 00000000 GRAS_2D_DST_BR: { X = 0 | Y = 0 } + 00000000 GRAS_2D_UNKNOWN_8407: 0 + 00000000 GRAS_2D_UNKNOWN_8408: 0 + 00000000 GRAS_2D_UNKNOWN_8409: 0 + 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 } + 00000000 GRAS_2D_RESOLVE_CNTL_2: { X = 0 | Y = 0 } + - context: 1 + 00000000 GRAS_CL_CNTL: { 0 } + 00000000 GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } + 00000000 GRAS_DS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } + 00000000 GRAS_GS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } + 00000000 GRAS_MAX_LAYER_INDEX: 0 + 00000000 GRAS_CNTL: { COORD_MASK = 0 } + 00000000 GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 0 | VERT = 0 } + 17ed48d5 GRAS_CL_VPORT[0].XOFFSET: 0.000000 + 1367ce4f GRAS_CL_VPORT[0].XSCALE: 0.000000 + 41486258 GRAS_CL_VPORT[0].YOFFSET: 12.524010 + a77c9dfe GRAS_CL_VPORT[0].YSCALE: -0.000000 + 4e1a2221 GRAS_CL_VPORT[0].ZOFFSET: 646481984.000000 + 25ad942d GRAS_CL_VPORT[0].ZSCALE: 0.000000 + b98dd337 GRAS_CL_VPORT[0x1].XOFFSET: -0.000271 + f3b29a4b GRAS_CL_VPORT[0x1].XSCALE: -28300728576976020658845084811264.000000 + 03c125ba GRAS_CL_VPORT[0x1].YOFFSET: 0.000000 + 9fd9154a GRAS_CL_VPORT[0x1].YSCALE: -0.000000 + 99e9ef18 GRAS_CL_VPORT[0x1].ZOFFSET: -0.000000 + cfa33a37 GRAS_CL_VPORT[0x1].ZSCALE: -5477002752.000000 + c08d010f GRAS_CL_VPORT[0x2].XOFFSET: -4.406379 + ec058c04 GRAS_CL_VPORT[0x2].XSCALE: -645793356413294901616181248.000000 + a095f8f2 GRAS_CL_VPORT[0x2].YOFFSET: -0.000000 + dd963bbd GRAS_CL_VPORT[0x2].YSCALE: -1353181742126596096.000000 + c8e17162 GRAS_CL_VPORT[0x2].ZOFFSET: -461707.062500 + c5f8656e GRAS_CL_VPORT[0x2].ZSCALE: -7948.678711 + 193ca252 GRAS_CL_VPORT[0x3].XOFFSET: 0.000000 + c276e62a GRAS_CL_VPORT[0x3].XSCALE: -61.724770 + 4aae8197 GRAS_CL_VPORT[0x3].YOFFSET: 5718219.500000 + a2a2312c GRAS_CL_VPORT[0x3].YSCALE: -0.000000 + 86a6e32d GRAS_CL_VPORT[0x3].ZOFFSET: -0.000000 + 2be1d796 GRAS_CL_VPORT[0x3].ZSCALE: 0.000000 + d1743060 GRAS_CL_VPORT[0x4].XOFFSET: -65548976128.000000 + 7c3d4406 GRAS_CL_VPORT[0x4].XSCALE: 3930895141940423283868471122294996992.000000 + 562e9a08 GRAS_CL_VPORT[0x4].YOFFSET: 47994145603584.000000 + fa7f4af3 GRAS_CL_VPORT[0x4].YSCALE: -331388962420135558780170972931555328.000000 + 0b2e288f GRAS_CL_VPORT[0x4].ZOFFSET: 0.000000 + 85c75124 GRAS_CL_VPORT[0x4].ZSCALE: -0.000000 + 94887ab4 GRAS_CL_VPORT[0x5].XOFFSET: -0.000000 + 1356de8c GRAS_CL_VPORT[0x5].XSCALE: 0.000000 + 14ff583b GRAS_CL_VPORT[0x5].YOFFSET: 0.000000 + 17ba9c47 GRAS_CL_VPORT[0x5].YSCALE: 0.000000 + c1dfc3da GRAS_CL_VPORT[0x5].ZOFFSET: -27.970631 + 2dc39521 GRAS_CL_VPORT[0x5].ZSCALE: 0.000000 + f1f2da44 GRAS_CL_VPORT[0x6].XOFFSET: -2405095658443594589675439783936.000000 + d68f795b GRAS_CL_VPORT[0x6].XSCALE: -78875690270720.000000 + c929b829 GRAS_CL_VPORT[0x6].YOFFSET: -695170.562500 + b174d59e GRAS_CL_VPORT[0x6].YSCALE: -0.000000 + 20b86447 GRAS_CL_VPORT[0x6].ZOFFSET: 0.000000 + 7cf5f63e GRAS_CL_VPORT[0x6].ZSCALE: 10216856921996855714425547393601634304.000000 + 25f487a0 GRAS_CL_VPORT[0x7].XOFFSET: 0.000000 + ff2b5fb1 GRAS_CL_VPORT[0x7].XSCALE: -227794845467281269236926443122692456448.000000 + 664b93c1 GRAS_CL_VPORT[0x7].YOFFSET: 240341493629255650639872.000000 + 078173fc GRAS_CL_VPORT[0x7].YSCALE: 0.000000 + ad12ea8c GRAS_CL_VPORT[0x7].ZOFFSET: -0.000000 + 6556977c GRAS_CL_VPORT[0x7].ZSCALE: 63336301301930932568064.000000 + 827e4c57 GRAS_CL_VPORT[0x8].XOFFSET: -0.000000 + d1fdee5f GRAS_CL_VPORT[0x8].XSCALE: -136328241152.000000 + 0a990478 GRAS_CL_VPORT[0x8].YOFFSET: 0.000000 + e3a19cf1 GRAS_CL_VPORT[0x8].YSCALE: -5962469232013083672576.000000 + 27db13b2 GRAS_CL_VPORT[0x8].ZOFFSET: 0.000000 + e719d958 GRAS_CL_VPORT[0x8].ZSCALE: -726531356411326028054528.000000 + 69da20dc GRAS_CL_VPORT[0x9].XOFFSET: 32962625335892150604267520.000000 + 890e59b0 GRAS_CL_VPORT[0x9].XSCALE: -0.000000 + 4c0ab84c GRAS_CL_VPORT[0x9].YOFFSET: 36364592.000000 + 587215e3 GRAS_CL_VPORT[0x9].YSCALE: 1064703266652160.000000 + 11e06c70 GRAS_CL_VPORT[0x9].ZOFFSET: 0.000000 + e7b1dbe6 GRAS_CL_VPORT[0x9].ZSCALE: -1679830555333396636106752.000000 + b78bc0aa GRAS_CL_VPORT[0xa].XOFFSET: -0.000017 + ac39bee4 GRAS_CL_VPORT[0xa].XSCALE: -0.000000 + ea76ea04 GRAS_CL_VPORT[0xa].YOFFSET: -74625214792291642198982656.000000 + 10ba9db3 GRAS_CL_VPORT[0xa].YSCALE: 0.000000 + 140034d1 GRAS_CL_VPORT[0xa].ZOFFSET: 0.000000 + d07fe121 GRAS_CL_VPORT[0xa].ZSCALE: -17171776512.000000 + 500ea138 GRAS_CL_VPORT[0xb].XOFFSET: 9571721216.000000 + 9e4f11a4 GRAS_CL_VPORT[0xb].XSCALE: -0.000000 + 8522222a GRAS_CL_VPORT[0xb].YOFFSET: -0.000000 + 31c8f926 GRAS_CL_VPORT[0xb].YSCALE: 0.000000 + c1233a11 GRAS_CL_VPORT[0xb].ZOFFSET: -10.201676 + eff95dd8 GRAS_CL_VPORT[0xb].ZSCALE: -154350435155798764938168631296.000000 + 2034c3cf GRAS_CL_VPORT[0xc].XOFFSET: 0.000000 + 35507804 GRAS_CL_VPORT[0xc].XSCALE: 0.000001 + b840b0d8 GRAS_CL_VPORT[0xc].YOFFSET: -0.000046 + ebf33447 GRAS_CL_VPORT[0xc].YSCALE: -588031693884586688765755392.000000 + 0bd54c04 GRAS_CL_VPORT[0xc].ZOFFSET: 0.000000 + 119b3bf4 GRAS_CL_VPORT[0xc].ZSCALE: 0.000000 + cc01323b GRAS_CL_VPORT[0xd].XOFFSET: -33868012.000000 + cf9fc237 GRAS_CL_VPORT[0xd].XSCALE: -5360610816.000000 + a0a0c6dc GRAS_CL_VPORT[0xd].YOFFSET: -0.000000 + 6578bdca GRAS_CL_VPORT[0xd].YSCALE: 73415492375974923730944.000000 + 1c183c97 GRAS_CL_VPORT[0xd].ZOFFSET: 0.000000 + 77907cd1 GRAS_CL_VPORT[0xd].ZSCALE: 5861111914889323960058734228537344.000000 + 9b76c406 GRAS_CL_VPORT[0xe].XOFFSET: -0.000000 + f59eb4eb GRAS_CL_VPORT[0xe].XSCALE: -402369314450854940480206742224896.000000 + 552bc020 GRAS_CL_VPORT[0xe].YOFFSET: 11802603683840.000000 + 73ce4f77 GRAS_CL_VPORT[0xe].YSCALE: 32691189311773747891142203015168.000000 + 11c1e3ea GRAS_CL_VPORT[0xe].ZOFFSET: 0.000000 + 067875da GRAS_CL_VPORT[0xe].ZSCALE: 0.000000 + de4491a7 GRAS_CL_VPORT[0xf].XOFFSET: -3541071480374689792.000000 + 7cb2fd6e GRAS_CL_VPORT[0xf].XSCALE: 7434952044374398076582578328088608768.000000 + 889d9245 GRAS_CL_VPORT[0xf].YOFFSET: -0.000000 + fc17a576 GRAS_CL_VPORT[0xf].YSCALE: -3149571088586152722879569121442267136.000000 + c2622832 GRAS_CL_VPORT[0xf].ZOFFSET: -56.539253 + 4f4fbf73 GRAS_CL_VPORT[0xf].ZSCALE: 3485430528.000000 + 00000000 GRAS_CL_Z_CLAMP[0].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x1].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x1].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x2].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x2].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x3].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x3].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x4].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x4].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x5].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x5].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x6].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x6].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x7].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x7].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x8].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x8].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x9].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0x9].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xa].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xa].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xb].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xb].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xc].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xc].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xd].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xd].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xe].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xe].MAX: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xf].MIN: 0.000000 + 00000000 GRAS_CL_Z_CLAMP[0xf].MAX: 0.000000 + 00000010 GRAS_SU_CNTL: { LINEHALFWIDTH = 0.500000 } + 00000000 GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } + 00000000 GRAS_SU_POINT_SIZE: 0.000000 + 00000000 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000 + 00000000 GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } + 00000000 GRAS_UNKNOWN_8099: 0 + 00000000 GRAS_UNKNOWN_809A: 0 + 00000000 GRAS_VS_LAYER_CNTL: { 0 } + 00000000 GRAS_GS_LAYER_CNTL: { 0 } + 00000000 GRAS_DS_LAYER_CNTL: { 0 } + 00000002 GRAS_UNKNOWN_80A0: 0x2 + 00000101 GRAS_BIN_CONTROL: { BINW = 32 | BINH = 16 } + 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 GRAS_SAMPLE_CONFIG: { 0 } + 00000000 GRAS_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 GRAS_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 GRAS_UNKNOWN_80AF: FALSE + 8c629e81 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 40577 | Y = 35938 } + fdee19a0 GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 6560 | Y = 65006 } + 8867136c GRAS_SC_SCREEN_SCISSOR[0x1].TL: { X = 4972 | Y = 34919 } + eeec2862 GRAS_SC_SCREEN_SCISSOR[0x1].BR: { X = 10338 | Y = 61164 } + 00988003 GRAS_SC_SCREEN_SCISSOR[0x2].TL: { X = 32771 | Y = 152 } + d3afa781 GRAS_SC_SCREEN_SCISSOR[0x2].BR: { X = 42881 | Y = 54191 } + d3f53b55 GRAS_SC_SCREEN_SCISSOR[0x3].TL: { X = 15189 | Y = 54261 } + a33d5eb3 GRAS_SC_SCREEN_SCISSOR[0x3].BR: { X = 24243 | Y = 41789 } + 23d08b45 GRAS_SC_SCREEN_SCISSOR[0x4].TL: { X = 35653 | Y = 9168 } + 14f61e22 GRAS_SC_SCREEN_SCISSOR[0x4].BR: { X = 7714 | Y = 5366 } + 643c0204 GRAS_SC_SCREEN_SCISSOR[0x5].TL: { X = 516 | Y = 25660 } + a9facb6e GRAS_SC_SCREEN_SCISSOR[0x5].BR: { X = 52078 | Y = 43514 } + d2e1d872 GRAS_SC_SCREEN_SCISSOR[0x6].TL: { X = 55410 | Y = 53985 } + 94cdd4fd GRAS_SC_SCREEN_SCISSOR[0x6].BR: { X = 54525 | Y = 38093 } + de0d1b35 GRAS_SC_SCREEN_SCISSOR[0x7].TL: { X = 6965 | Y = 56845 } + 237c51d7 GRAS_SC_SCREEN_SCISSOR[0x7].BR: { X = 20951 | Y = 9084 } + cbf20742 GRAS_SC_SCREEN_SCISSOR[0x8].TL: { X = 1858 | Y = 52210 } + 352bb4fc GRAS_SC_SCREEN_SCISSOR[0x8].BR: { X = 46332 | Y = 13611 } + a5a59c55 GRAS_SC_SCREEN_SCISSOR[0x9].TL: { X = 40021 | Y = 42405 } + 07da59a6 GRAS_SC_SCREEN_SCISSOR[0x9].BR: { X = 22950 | Y = 2010 } + 8d709172 GRAS_SC_SCREEN_SCISSOR[0xa].TL: { X = 37234 | Y = 36208 } + 848ffffe GRAS_SC_SCREEN_SCISSOR[0xa].BR: { X = 65534 | Y = 33935 } + 8c0b18da GRAS_SC_SCREEN_SCISSOR[0xb].TL: { X = 6362 | Y = 35851 } + e75d13c3 GRAS_SC_SCREEN_SCISSOR[0xb].BR: { X = 5059 | Y = 59229 } + 114252db GRAS_SC_SCREEN_SCISSOR[0xc].TL: { X = 21211 | Y = 4418 } + c427b17e GRAS_SC_SCREEN_SCISSOR[0xc].BR: { X = 45438 | Y = 50215 } + 31c1fc95 GRAS_SC_SCREEN_SCISSOR[0xd].TL: { X = 64661 | Y = 12737 } + ae47e0b7 GRAS_SC_SCREEN_SCISSOR[0xd].BR: { X = 57527 | Y = 44615 } + 13283829 GRAS_SC_SCREEN_SCISSOR[0xe].TL: { X = 14377 | Y = 4904 } + d5eafd7f GRAS_SC_SCREEN_SCISSOR[0xe].BR: { X = 64895 | Y = 54762 } + ac0886f7 GRAS_SC_SCREEN_SCISSOR[0xf].TL: { X = 34551 | Y = 44040 } + 7bedbdb2 GRAS_SC_SCREEN_SCISSOR[0xf].BR: { X = 48562 | Y = 31725 } + c487b444 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 46148 | Y = 50311 } + df46330f GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 13071 | Y = 57158 } + 1b1da288 GRAS_SC_VIEWPORT_SCISSOR[0x1].TL: { X = 41608 | Y = 6941 } + 375f7ebc GRAS_SC_VIEWPORT_SCISSOR[0x1].BR: { X = 32444 | Y = 14175 } + 73ba19e8 GRAS_SC_VIEWPORT_SCISSOR[0x2].TL: { X = 6632 | Y = 29626 } + ef6c9650 GRAS_SC_VIEWPORT_SCISSOR[0x2].BR: { X = 38480 | Y = 61292 } + 22d60948 GRAS_SC_VIEWPORT_SCISSOR[0x3].TL: { X = 2376 | Y = 8918 } + 5c2f6e10 GRAS_SC_VIEWPORT_SCISSOR[0x3].BR: { X = 28176 | Y = 23599 } + 8e231280 GRAS_SC_VIEWPORT_SCISSOR[0x4].TL: { X = 4736 | Y = 36387 } + fa6bbe2a GRAS_SC_VIEWPORT_SCISSOR[0x4].BR: { X = 48682 | Y = 64107 } + 015d816e GRAS_SC_VIEWPORT_SCISSOR[0x5].TL: { X = 33134 | Y = 349 } + 3dfdfa2d GRAS_SC_VIEWPORT_SCISSOR[0x5].BR: { X = 64045 | Y = 15869 } + 3610960b GRAS_SC_VIEWPORT_SCISSOR[0x6].TL: { X = 38411 | Y = 13840 } + 9b769a89 GRAS_SC_VIEWPORT_SCISSOR[0x6].BR: { X = 39561 | Y = 39798 } + a85a55b3 GRAS_SC_VIEWPORT_SCISSOR[0x7].TL: { X = 21939 | Y = 43098 } + ca868126 GRAS_SC_VIEWPORT_SCISSOR[0x7].BR: { X = 33062 | Y = 51846 } + 8d20cea5 GRAS_SC_VIEWPORT_SCISSOR[0x8].TL: { X = 52901 | Y = 36128 } + be4af7fa GRAS_SC_VIEWPORT_SCISSOR[0x8].BR: { X = 63482 | Y = 48714 } + 41588113 GRAS_SC_VIEWPORT_SCISSOR[0x9].TL: { X = 33043 | Y = 16728 } + eb5bb66a GRAS_SC_VIEWPORT_SCISSOR[0x9].BR: { X = 46698 | Y = 60251 } + 40667101 GRAS_SC_VIEWPORT_SCISSOR[0xa].TL: { X = 28929 | Y = 16486 } + 19e09698 GRAS_SC_VIEWPORT_SCISSOR[0xa].BR: { X = 38552 | Y = 6624 } + 88c11d03 GRAS_SC_VIEWPORT_SCISSOR[0xb].TL: { X = 7427 | Y = 35009 } + fad7dbc7 GRAS_SC_VIEWPORT_SCISSOR[0xb].BR: { X = 56263 | Y = 64215 } + 10204eb9 GRAS_SC_VIEWPORT_SCISSOR[0xc].TL: { X = 20153 | Y = 4128 } + 53fcd9da GRAS_SC_VIEWPORT_SCISSOR[0xc].BR: { X = 55770 | Y = 21500 } + 4d592181 GRAS_SC_VIEWPORT_SCISSOR[0xd].TL: { X = 8577 | Y = 19801 } + ed40b570 GRAS_SC_VIEWPORT_SCISSOR[0xd].BR: { X = 46448 | Y = 60736 } + 00745b64 GRAS_SC_VIEWPORT_SCISSOR[0xe].TL: { X = 23396 | Y = 116 } + 27fbffdc GRAS_SC_VIEWPORT_SCISSOR[0xe].BR: { X = 65500 | Y = 10235 } + ac66bcc7 GRAS_SC_VIEWPORT_SCISSOR[0xf].TL: { X = 48327 | Y = 44134 } + 790cdf93 GRAS_SC_VIEWPORT_SCISSOR[0xf].BR: { X = 57235 | Y = 30988 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } + 00000000 GRAS_SC_WINDOW_SCISSOR_BR: { X = 0 | Y = 0 } + 00000000 GRAS_LRZ_CNTL: { 0 } + 00000000 GRAS_UNKNOWN_8101: 0 + 00000000 GRAS_2D_BLIT_INFO: { COLOR_FORMAT = 0 } + 00000000 GRAS_LRZ_BUFFER_BASE_LO: 0 + 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0 + 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0 + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 + 00000000 GRAS_SAMPLE_CNTL: { 0 } + 00000000 GRAS_UNKNOWN_8110: 0 + 00000000 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW } + 00000000 GRAS_2D_SRC_TL_X: 0 + 00000000 GRAS_2D_SRC_BR_X: 0 + 00000000 GRAS_2D_SRC_TL_Y: 0 + 00000000 GRAS_2D_SRC_BR_Y: 0 + 00000000 GRAS_2D_DST_TL: { X = 0 | Y = 0 } + 00000000 GRAS_2D_DST_BR: { X = 0 | Y = 0 } + 00000000 GRAS_2D_UNKNOWN_8407: 0 + 00000000 GRAS_2D_UNKNOWN_8408: 0 + 00000000 GRAS_2D_UNKNOWN_8409: 0 + 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 } + 00000000 GRAS_2D_RESOLVE_CNTL_2: { X = 0 | Y = 0 } + - cluster-name: CLUSTER_PS + - context: 0 + 00000101 RB_BIN_CONTROL: { BINW = 32 | BINH = 16 } + 00000010 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0 } + 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 RB_SAMPLE_CONFIG: { 0 } + 00000000 RB_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 RB_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 RB_RENDER_CONTROL0: { COORD_MASK = 0 } + 00000000 RB_RENDER_CONTROL1: { 0 } + 00000000 RB_FS_OUTPUT_CNTL0: { 0 } + 00000000 RB_FS_OUTPUT_CNTL1: { MRT = 0 } + 00000000 RB_RENDER_COMPONENTS: { RT0 = 0 | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000000 RB_DITHER_CNTL: { DITHER_MODE_MRT0 = DITHER_DISABLE | DITHER_MODE_MRT1 = DITHER_DISABLE | DITHER_MODE_MRT2 = DITHER_DISABLE | DITHER_MODE_MRT3 = DITHER_DISABLE | DITHER_MODE_MRT4 = DITHER_DISABLE | DITHER_MODE_MRT5 = DITHER_DISABLE | DITHER_MODE_MRT6 = DITHER_DISABLE | DITHER_MODE_MRT7 = DITHER_DISABLE } + 00000000 RB_SRGB_CNTL: { 0 } + 00000000 RB_SAMPLE_CNTL: { 0 } + 00000000 RB_UNKNOWN_8811: 0 + 00000000 RB_UNKNOWN_8818: 0 + 00000000 RB_UNKNOWN_8819: 0 + 00000000 RB_UNKNOWN_881A: 0 + 00000000 RB_UNKNOWN_881B: 0 + 00000000 RB_UNKNOWN_881C: 0 + 00000000 RB_UNKNOWN_881D: 0 + 00000000 RB_UNKNOWN_881E: 0 + 00000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0].PITCH: 0 + 00000000 RB_MRT[0].ARRAY_PITCH: 0 + 00000000 RB_MRT[0].BASE_LO: 0 + 00000000 RB_MRT[0].BASE_HI: 0 + 00000000 RB_MRT[0].BASE_GMEM: 0 + 00000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x1].PITCH: 0 + 00000000 RB_MRT[0x1].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x1].BASE_LO: 0 + 00000000 RB_MRT[0x1].BASE_HI: 0 + 00000000 RB_MRT[0x1].BASE_GMEM: 0 + 00000000 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x2].PITCH: 0 + 00000000 RB_MRT[0x2].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x2].BASE_LO: 0 + 00000000 RB_MRT[0x2].BASE_HI: 0 + 00000000 RB_MRT[0x2].BASE_GMEM: 0 + 00000000 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x3].PITCH: 0 + 00000000 RB_MRT[0x3].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x3].BASE_LO: 0 + 00000000 RB_MRT[0x3].BASE_HI: 0 + 00000000 RB_MRT[0x3].BASE_GMEM: 0 + 00000000 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x4].PITCH: 0 + 00000000 RB_MRT[0x4].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x4].BASE_LO: 0 + 00000000 RB_MRT[0x4].BASE_HI: 0 + 00000000 RB_MRT[0x4].BASE_GMEM: 0 + 00000000 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x5].PITCH: 0 + 00000000 RB_MRT[0x5].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x5].BASE_LO: 0 + 00000000 RB_MRT[0x5].BASE_HI: 0 + 00000000 RB_MRT[0x5].BASE_GMEM: 0 + 00000000 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x6].PITCH: 0 + 00000000 RB_MRT[0x6].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x6].BASE_LO: 0 + 00000000 RB_MRT[0x6].BASE_HI: 0 + 00000000 RB_MRT[0x6].BASE_GMEM: 0 + 00000000 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x7].PITCH: 0 + 00000000 RB_MRT[0x7].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x7].BASE_LO: 0 + 00000000 RB_MRT[0x7].BASE_HI: 0 + 00000000 RB_MRT[0x7].BASE_GMEM: 0 + 00000000 RB_BLEND_RED_F32: 0.000000 + 00000000 RB_BLEND_GREEN_F32: 0.000000 + 00000000 RB_BLEND_BLUE_F32: 0.000000 + 00000000 RB_BLEND_ALPHA_F32: 0.000000 + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } + ffff0100 RB_BLEND_CNTL: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff } + 00000000 RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } + 00000000 RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } + 00000000 RB_DEPTH_BUFFER_PITCH: 0 + 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0 + 00000000 RB_DEPTH_BUFFER_BASE_LO: 0 + 00000000 RB_DEPTH_BUFFER_BASE_HI: 0 + 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0 + 00000000 RB_Z_BOUNDS_MIN: 0.000000 + 00000000 RB_Z_BOUNDS_MAX: 0.000000 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { 0 } + 00000000 RB_STENCIL_BUFFER_PITCH: 0 + 00000000 RB_STENCIL_BUFFER_ARRAY_PITCH: 0 + 00000000 RB_STENCIL_BUFFER_BASE_LO: 0 + 00000000 RB_STENCIL_BUFFER_BASE_HI: 0 + 00000000 RB_STENCIL_BUFFER_BASE_GMEM: 0 + 00000000 RB_STENCILREF: { REF = 0 | BFREF = 0 } + 00000000 RB_STENCILMASK: { MASK = 0 | BFMASK = 0 } + 00000000 RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 } + 00000000 RB_WINDOW_OFFSET: { X = 0 | Y = 0 } + 00000000 RB_SAMPLE_COUNT_CONTROL: { 0 } + 00000000 RB_LRZ_CNTL: { 0 } + 00000000 RB_Z_CLAMP_MIN: 0.000000 + 00000000 RB_Z_CLAMP_MAX: 0.000000 + 00000000 RB_UNKNOWN_88D0: { 0 } + 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } + 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 } + 00001008 RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 } + 00000000 RB_WINDOW_OFFSET2: { X = 0 | Y = 0 } + 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 RB_BLIT_BASE_GMEM: 0 + 00004100 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_32_32_32_32_FLOAT } + 00000000 RB_BLIT_DST: 0 + 00000000 RB_BLIT_DST+0x1: 0 + 00000000 RB_BLIT_DST_PITCH: 0 + 00000000 RB_BLIT_DST_ARRAY_PITCH: 0 + 00000000 RB_BLIT_FLAG_DST: 0 + 00000000 RB_BLIT_FLAG_DST+0x1: 0 + 00000000 RB_BLIT_FLAG_DST_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_BLIT_CLEAR_COLOR_DW0: 0 + 00000000 RB_BLIT_CLEAR_COLOR_DW1: 0 + 00000000 RB_BLIT_CLEAR_COLOR_DW2: 0 + 00000000 RB_BLIT_CLEAR_COLOR_DW3: 0 + 000000f2 RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf } + 00000000 RB_DEPTH_FLAG_BUFFER_BASE_LO: 0 + 00000000 RB_DEPTH_FLAG_BUFFER_BASE_HI: 0 + 00000000 RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x1].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x2].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x4].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x5].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x6].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x7].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW } + 00000000 RB_2D_UNKNOWN_8C01: 0 + 00000000 0x8c08: 00000000 + 00000000 0x8c09: 00000000 + 00000000 0x8c0a: 00000000 + 00000000 0x8c0b: 00000000 + 00000000 0x8c0c: 00000000 + 00000000 0x8c0d: 00000000 + 00000000 0x8c0e: 00000000 + 00000000 0x8c0f: 00000000 + 00000000 0x8c10: 00000000 + 00000000 RB_2D_DST_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE } + 00000000 RB_2D_DST_LO: 0 + 00000000 RB_2D_DST_HI: 0 + 00000000 RB_2D_DST_PITCH: 0 + 00000000 RB_2D_DST_PLANE1: 0 + 00000000 RB_2D_DST_PLANE1+0x1: 0 + 00000000 RB_2D_DST_PLANE_PITCH: 0 + 00000000 RB_2D_DST_PLANE2: 0 + 00000000 RB_2D_DST_PLANE2+0x1: 0 + 00000000 0x8c26: 00000000 + 00000000 0x8c27: 00000000 + 00000000 0x8c28: 00000000 + 00000000 0x8c29: 00000000 + 00000000 0x8c2a: 00000000 + 00000000 0x8c2b: 00000000 + 00000000 RB_2D_SRC_SOLID_C0: 0 + 00000000 RB_2D_SRC_SOLID_C1: 0 + 00000000 RB_2D_SRC_SOLID_C2: 0 + 00000000 RB_2D_SRC_SOLID_C3: 0 + 00000000 0x8c30: 00000000 + 00000000 0x8c31: 00000000 + 00000000 0x8c32: 00000000 + 00000000 0x8c33: 00000000 + - context: 1 + 00000101 RB_BIN_CONTROL: { BINW = 32 | BINH = 16 } + 00000010 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0 } + 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 RB_SAMPLE_CONFIG: { 0 } + 00000000 RB_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 RB_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 RB_RENDER_CONTROL0: { COORD_MASK = 0 } + 00000000 RB_RENDER_CONTROL1: { 0 } + 00000000 RB_FS_OUTPUT_CNTL0: { 0 } + 00000000 RB_FS_OUTPUT_CNTL1: { MRT = 0 } + 00000000 RB_RENDER_COMPONENTS: { RT0 = 0 | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + 00000000 RB_DITHER_CNTL: { DITHER_MODE_MRT0 = DITHER_DISABLE | DITHER_MODE_MRT1 = DITHER_DISABLE | DITHER_MODE_MRT2 = DITHER_DISABLE | DITHER_MODE_MRT3 = DITHER_DISABLE | DITHER_MODE_MRT4 = DITHER_DISABLE | DITHER_MODE_MRT5 = DITHER_DISABLE | DITHER_MODE_MRT6 = DITHER_DISABLE | DITHER_MODE_MRT7 = DITHER_DISABLE } + 00000000 RB_SRGB_CNTL: { 0 } + 00000000 RB_SAMPLE_CNTL: { 0 } + 00000000 RB_UNKNOWN_8811: 0 + 00000000 RB_UNKNOWN_8818: 0 + 00000000 RB_UNKNOWN_8819: 0 + 00000000 RB_UNKNOWN_881A: 0 + 00000000 RB_UNKNOWN_881B: 0 + 00000000 RB_UNKNOWN_881C: 0 + 00000000 RB_UNKNOWN_881D: 0 + 00000000 RB_UNKNOWN_881E: 0 + 00000000 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0].PITCH: 0 + 00000000 RB_MRT[0].ARRAY_PITCH: 0 + 00000000 RB_MRT[0].BASE_LO: 0 + 00000000 RB_MRT[0].BASE_HI: 0 + 00000000 RB_MRT[0].BASE_GMEM: 0 + 00000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x1].PITCH: 0 + 00000000 RB_MRT[0x1].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x1].BASE_LO: 0 + 00000000 RB_MRT[0x1].BASE_HI: 0 + 00000000 RB_MRT[0x1].BASE_GMEM: 0 + 00000000 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x2].PITCH: 0 + 00000000 RB_MRT[0x2].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x2].BASE_LO: 0 + 00000000 RB_MRT[0x2].BASE_HI: 0 + 00000000 RB_MRT[0x2].BASE_GMEM: 0 + 00000000 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x3].PITCH: 0 + 00000000 RB_MRT[0x3].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x3].BASE_LO: 0 + 00000000 RB_MRT[0x3].BASE_HI: 0 + 00000000 RB_MRT[0x3].BASE_GMEM: 0 + 00000000 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x4].PITCH: 0 + 00000000 RB_MRT[0x4].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x4].BASE_LO: 0 + 00000000 RB_MRT[0x4].BASE_HI: 0 + 00000000 RB_MRT[0x4].BASE_GMEM: 0 + 00000000 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x5].PITCH: 0 + 00000000 RB_MRT[0x5].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x5].BASE_LO: 0 + 00000000 RB_MRT[0x5].BASE_HI: 0 + 00000000 RB_MRT[0x5].BASE_GMEM: 0 + 00000000 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x6].PITCH: 0 + 00000000 RB_MRT[0x6].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x6].BASE_LO: 0 + 00000000 RB_MRT[0x6].BASE_HI: 0 + 00000000 RB_MRT[0x6].BASE_GMEM: 0 + 00000000 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } + 00000000 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + 00000000 RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX } + 00000000 RB_MRT[0x7].PITCH: 0 + 00000000 RB_MRT[0x7].ARRAY_PITCH: 0 + 00000000 RB_MRT[0x7].BASE_LO: 0 + 00000000 RB_MRT[0x7].BASE_HI: 0 + 00000000 RB_MRT[0x7].BASE_GMEM: 0 + 00000000 RB_BLEND_RED_F32: 0.000000 + 00000000 RB_BLEND_GREEN_F32: 0.000000 + 00000000 RB_BLEND_BLUE_F32: 0.000000 + 00000000 RB_BLEND_ALPHA_F32: 0.000000 + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } + ffff0100 RB_BLEND_CNTL: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff } + 00000000 RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } + 00000000 RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER } + 00000000 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } + 00000000 RB_DEPTH_BUFFER_PITCH: 0 + 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0 + 00000000 RB_DEPTH_BUFFER_BASE_LO: 0 + 00000000 RB_DEPTH_BUFFER_BASE_HI: 0 + 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0 + 00000000 RB_Z_BOUNDS_MIN: 0.000000 + 00000000 RB_Z_BOUNDS_MAX: 0.000000 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + 00000000 RB_STENCIL_INFO: { 0 } + 00000000 RB_STENCIL_BUFFER_PITCH: 0 + 00000000 RB_STENCIL_BUFFER_ARRAY_PITCH: 0 + 00000000 RB_STENCIL_BUFFER_BASE_LO: 0 + 00000000 RB_STENCIL_BUFFER_BASE_HI: 0 + 00000000 RB_STENCIL_BUFFER_BASE_GMEM: 0 + 00000000 RB_STENCILREF: { REF = 0 | BFREF = 0 } + 00000000 RB_STENCILMASK: { MASK = 0 | BFMASK = 0 } + 00000000 RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 } + 00000000 RB_WINDOW_OFFSET: { X = 0 | Y = 0 } + 00000000 RB_SAMPLE_COUNT_CONTROL: { 0 } + 00000000 RB_LRZ_CNTL: { 0 } + 00000000 RB_Z_CLAMP_MIN: 0.000000 + 00000000 RB_Z_CLAMP_MAX: 0.000000 + 00000000 RB_UNKNOWN_88D0: { 0 } + 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } + 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 } + 00001008 RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 } + 00000000 RB_WINDOW_OFFSET2: { X = 0 | Y = 0 } + 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 RB_BLIT_BASE_GMEM: 0 + 00004100 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_32_32_32_32_FLOAT } + 00000000 RB_BLIT_DST: 0 + 00000000 RB_BLIT_DST+0x1: 0 + 00000000 RB_BLIT_DST_PITCH: 0 + 00000000 RB_BLIT_DST_ARRAY_PITCH: 0 + 00000000 RB_BLIT_FLAG_DST: 0 + 00000000 RB_BLIT_FLAG_DST+0x1: 0 + 00000000 RB_BLIT_FLAG_DST_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_BLIT_CLEAR_COLOR_DW0: 0 + 00000000 RB_BLIT_CLEAR_COLOR_DW1: 0 + 00000000 RB_BLIT_CLEAR_COLOR_DW2: 0 + 00000000 RB_BLIT_CLEAR_COLOR_DW3: 0 + 000000f2 RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf } + 00000000 RB_DEPTH_FLAG_BUFFER_BASE_LO: 0 + 00000000 RB_DEPTH_FLAG_BUFFER_BASE_HI: 0 + 00000000 RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x1].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x2].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x4].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x5].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x6].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_LO: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x7].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW } + 00000000 RB_2D_UNKNOWN_8C01: 0 + 00000000 0x8c08: 00000000 + 00000000 0x8c09: 00000000 + 00000000 0x8c0a: 00000000 + 00000000 0x8c0b: 00000000 + 00000000 0x8c0c: 00000000 + 00000000 0x8c0d: 00000000 + 00000000 0x8c0e: 00000000 + 00000000 0x8c0f: 00000000 + 00000000 0x8c10: 00000000 + 00000000 RB_2D_DST_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE } + 00000000 RB_2D_DST_LO: 0 + 00000000 RB_2D_DST_HI: 0 + 00000000 RB_2D_DST_PITCH: 0 + 00000000 RB_2D_DST_PLANE1: 0 + 00000000 RB_2D_DST_PLANE1+0x1: 0 + 00000000 RB_2D_DST_PLANE_PITCH: 0 + 00000000 RB_2D_DST_PLANE2: 0 + 00000000 RB_2D_DST_PLANE2+0x1: 0 + 00000000 0x8c26: 00000000 + 00000000 0x8c27: 00000000 + 00000000 0x8c28: 00000000 + 00000000 0x8c29: 00000000 + 00000000 0x8c2a: 00000000 + 00000000 0x8c2b: 00000000 + 00000000 RB_2D_SRC_SOLID_C0: 0 + 00000000 RB_2D_SRC_SOLID_C1: 0 + 00000000 RB_2D_SRC_SOLID_C2: 0 + 00000000 RB_2D_SRC_SOLID_C3: 0 + 00000000 0x8c30: 00000000 + 00000000 0x8c31: 00000000 + 00000000 0x8c32: 00000000 + 00000000 0x8c33: 00000000 + - cluster-name: CLUSTER_PS + - context: 0 + 00000000 RB_UNKNOWN_88F0: 0 + 00000000 RB_UNK_FLAG_BUFFER_BASE: 0 + 00000000 RB_UNK_FLAG_BUFFER_BASE+0x1: 0 + 00000000 RB_UNK_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x3].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_SAMPLE_COUNT_ADDR_LO: 0 + 00000000 RB_SAMPLE_COUNT_ADDR_HI: 0 + 00000000 0x8bf0: 00000000 + 00000000 0x8bf1: 00000000 + 00000000 0x8c02: 00000000 + 00000000 0x8c03: 00000000 + 00000000 0x8c04: 00000000 + 00000000 0x8c05: 00000000 + 00000000 0x8c06: 00000000 + 00000000 0x8c07: 00000000 + 00000000 0x8c11: 00000000 + 00000000 0x8c12: 00000000 + 00000000 0x8c13: 00000000 + 00000000 0x8c14: 00000000 + 00000000 0x8c15: 00000000 + 00000000 0x8c16: 00000000 + 00000000 RB_2D_DST_FLAGS_LO: 0 + 00000000 RB_2D_DST_FLAGS_HI: 0 + 00000000 RB_2D_DST_FLAGS_PITCH: 0 + 00000000 RB_2D_DST_FLAGS_PLANE: 0 + 00000000 RB_2D_DST_FLAGS_PLANE+0x1: 0 + 00000000 RB_2D_DST_FLAGS_PLANE_PITCH: 0 + - context: 1 + 00000000 RB_UNKNOWN_88F0: 0 + 00000000 RB_UNK_FLAG_BUFFER_BASE: 0 + 00000000 RB_UNK_FLAG_BUFFER_BASE+0x1: 0 + 00000000 RB_UNK_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0x3].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 RB_SAMPLE_COUNT_ADDR_LO: 0 + 00000000 RB_SAMPLE_COUNT_ADDR_HI: 0 + 00000000 0x8bf0: 00000000 + 00000000 0x8bf1: 00000000 + 00000000 0x8c02: 00000000 + 00000000 0x8c03: 00000000 + 00000000 0x8c04: 00000000 + 00000000 0x8c05: 00000000 + 00000000 0x8c06: 00000000 + 00000000 0x8c07: 00000000 + 00000000 0x8c11: 00000000 + 00000000 0x8c12: 00000000 + 00000000 0x8c13: 00000000 + 00000000 0x8c14: 00000000 + 00000000 0x8c15: 00000000 + 00000000 0x8c16: 00000000 + 00000000 RB_2D_DST_FLAGS_LO: 0 + 00000000 RB_2D_DST_FLAGS_HI: 0 + 00000000 RB_2D_DST_FLAGS_PITCH: 0 + 00000000 RB_2D_DST_FLAGS_PLANE: 0 + 00000000 RB_2D_DST_FLAGS_PLANE+0x1: 0 + 00000000 RB_2D_DST_FLAGS_PLANE_PITCH: 0 + - cluster-name: CLUSTER_PS + - context: 0 + 00000000 VPC_VARYING_INTERP[0].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + 00000000 VPC_UNKNOWN_9210: 0 + 00000000 VPC_UNKNOWN_9211: 0 + 00000000 VPC_VAR[0].DISABLE: 0 + 00000000 VPC_VAR[0x1].DISABLE: 0 + 00000000 VPC_VAR[0x2].DISABLE: 0 + 00000000 VPC_VAR[0x3].DISABLE: 0 + 00000000 VPC_SO_CNTL: { 0 } + 00000000 VPC_SO_STREAM_COUNTS_LO: 0 + 00000000 VPC_SO_STREAM_COUNTS_HI: 0 + 00000000 VPC_SO[0].BUFFER_BASE: 0 + 00000000 VPC_SO[0].BUFFER_BASE+0x1: 0 + 00000000 VPC_SO[0].BUFFER_SIZE: 0 + 00000001 VPC_SO[0].NCOMP: 0x1 + 00000000 VPC_SO[0].BUFFER_OFFSET: 0 + 00000000 VPC_SO[0].FLUSH_BASE: 0 + 00000000 VPC_SO[0].FLUSH_BASE+0x1: 0 + 00000000 VPC_SO[0x1].BUFFER_BASE: 0 + 00000000 VPC_SO[0x1].BUFFER_BASE+0x1: 0 + 00000000 VPC_SO[0x1].BUFFER_SIZE: 0 + 00000001 VPC_SO[0x1].NCOMP: 0x1 + 00000000 VPC_SO[0x1].BUFFER_OFFSET: 0 + 00000000 VPC_SO[0x1].FLUSH_BASE: 0 + 00000000 VPC_SO[0x1].FLUSH_BASE+0x1: 0 + 00000000 VPC_SO[0x2].BUFFER_BASE: 0 + 00000000 VPC_SO[0x2].BUFFER_BASE+0x1: 0 + 00000000 VPC_SO[0x2].BUFFER_SIZE: 0 + 00000001 VPC_SO[0x2].NCOMP: 0x1 + 00000000 VPC_SO[0x2].BUFFER_OFFSET: 0 + 00000000 VPC_SO[0x2].FLUSH_BASE: 0 + 00000000 VPC_SO[0x2].FLUSH_BASE+0x1: 0 + 00000000 VPC_SO[0x3].BUFFER_BASE: 0 + 00000000 VPC_SO[0x3].BUFFER_BASE+0x1: 0 + 00000000 VPC_SO[0x3].BUFFER_SIZE: 0 + 00000001 VPC_SO[0x3].NCOMP: 0x1 + 00000000 VPC_SO[0x3].BUFFER_OFFSET: 0 + 00000000 VPC_SO[0x3].FLUSH_BASE: 0 + 00000000 VPC_SO[0x3].FLUSH_BASE+0x1: 0 + 00000000 VPC_POINT_COORD_INVERT: { 0 } + 00000000 VPC_UNKNOWN_9300: 0 + 00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | UNKLOC = 255 } + 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_DISABLE: { 0 } + - context: 1 + 00000000 VPC_VARYING_INTERP[0].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + 00000000 VPC_UNKNOWN_9210: 0 + 00000000 VPC_UNKNOWN_9211: 0 + 00000000 VPC_VAR[0].DISABLE: 0 + 00000000 VPC_VAR[0x1].DISABLE: 0 + 00000000 VPC_VAR[0x2].DISABLE: 0 + 00000000 VPC_VAR[0x3].DISABLE: 0 + 00000000 VPC_SO_CNTL: { 0 } + 00000000 VPC_SO_STREAM_COUNTS_LO: 0 + 00000000 VPC_SO_STREAM_COUNTS_HI: 0 + 00000000 VPC_SO[0].BUFFER_BASE: 0 + 00000000 VPC_SO[0].BUFFER_BASE+0x1: 0 + 00000000 VPC_SO[0].BUFFER_SIZE: 0 + 00000001 VPC_SO[0].NCOMP: 0x1 + 00000000 VPC_SO[0].BUFFER_OFFSET: 0 + 00000000 VPC_SO[0].FLUSH_BASE: 0 + 00000000 VPC_SO[0].FLUSH_BASE+0x1: 0 + 00000000 VPC_SO[0x1].BUFFER_BASE: 0 + 00000000 VPC_SO[0x1].BUFFER_BASE+0x1: 0 + 00000000 VPC_SO[0x1].BUFFER_SIZE: 0 + 00000001 VPC_SO[0x1].NCOMP: 0x1 + 00000000 VPC_SO[0x1].BUFFER_OFFSET: 0 + 00000000 VPC_SO[0x1].FLUSH_BASE: 0 + 00000000 VPC_SO[0x1].FLUSH_BASE+0x1: 0 + 00000000 VPC_SO[0x2].BUFFER_BASE: 0 + 00000000 VPC_SO[0x2].BUFFER_BASE+0x1: 0 + 00000000 VPC_SO[0x2].BUFFER_SIZE: 0 + 00000001 VPC_SO[0x2].NCOMP: 0x1 + 00000000 VPC_SO[0x2].BUFFER_OFFSET: 0 + 00000000 VPC_SO[0x2].FLUSH_BASE: 0 + 00000000 VPC_SO[0x2].FLUSH_BASE+0x1: 0 + 00000000 VPC_SO[0x3].BUFFER_BASE: 0 + 00000000 VPC_SO[0x3].BUFFER_BASE+0x1: 0 + 00000000 VPC_SO[0x3].BUFFER_SIZE: 0 + 00000001 VPC_SO[0x3].NCOMP: 0x1 + 00000000 VPC_SO[0x3].BUFFER_OFFSET: 0 + 00000000 VPC_SO[0x3].FLUSH_BASE: 0 + 00000000 VPC_SO[0x3].FLUSH_BASE+0x1: 0 + 00000000 VPC_POINT_COORD_INVERT: { 0 } + 00000000 VPC_UNKNOWN_9300: 0 + 00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | UNKLOC = 255 } + 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_DISABLE: { 0 } + - cluster-name: CLUSTER_FE + - context: 0 + 00000000 VPC_UNKNOWN_9300: 0 + 00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | UNKLOC = 255 } + 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_DISABLE: { 0 } + 00000000 PC_TESS_NUM_VERTEX: 0 + 00000000 PC_HS_INPUT_SIZE: { SIZE = 0 } + 00000000 PC_TESS_CNTL: { SPACING = TESS_EQUAL | OUTPUT = TESS_POINTS } + ffffffff PC_RESTART_INDEX: 4294967295 + 0000001f PC_MODE_CNTL: 0x1f + 00000001 PC_UNKNOWN_9805: 0x1 + 00000000 PC_PRIMID_PASSTHRU: FALSE + 00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST } + 00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000001 PC_GS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000000 PC_PRIMITIVE_CNTL_3: 0 + 00000001 PC_DS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000000 PC_PRIMITIVE_CNTL_5: { GS_VERTICES_OUT = 0 | GS_INVOCATIONS = 0 | GS_OUTPUT = TESS_POINTS } + 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } + 00000000 PC_UNKNOWN_9B07: 0 + 00000000 VFD_CONTROL_0: { FETCH_CNT = 0 | DECODE_CNT = 0 } + fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | 0xfc000000 } + 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } + fcfcfcfc VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } + 000000fc VFD_CONTROL_4: 0xfc + 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + 00000000 VFD_CONTROL_6: { 0 } + 00000000 VFD_MODE_CNTL: { 0 } + 00000000 VFD_UNKNOWN_A008: 0 + 00000000 VFD_ADD_OFFSET: { 0 } + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 VFD_INSTANCE_START_OFFSET: 0 + 1618e045 VFD_FETCH[0].BASE: 0x1618e045 + 00005505 VFD_FETCH[0].BASE+0x1: 0x5505 + 00840800 VFD_FETCH[0].SIZE: 8652800 + 00000051 VFD_FETCH[0].STRIDE: 81 + 01100401 VFD_FETCH[0x1].BASE: 0x1100401 + 00000040 VFD_FETCH[0x1].BASE+0x1: 0x40 + 04010402 VFD_FETCH[0x1].SIZE: 67175426 + 00000000 VFD_FETCH[0x1].STRIDE: 0 + 40080120 VFD_FETCH[0x2].BASE: 0x40080120 + 00004000 VFD_FETCH[0x2].BASE+0x1: 0x4000 + 00140100 VFD_FETCH[0x2].SIZE: 1310976 + 00000002 VFD_FETCH[0x2].STRIDE: 2 + 00001090 VFD_FETCH[0x3].BASE: 0x1090 + 00000200 VFD_FETCH[0x3].BASE+0x1: 0x200 + 11040100 VFD_FETCH[0x3].SIZE: 285475072 + 00000000 VFD_FETCH[0x3].STRIDE: 0 + 04000900 VFD_FETCH[0x4].BASE: 0x4000900 + 00000451 VFD_FETCH[0x4].BASE+0x1: 0x451 + 01000806 VFD_FETCH[0x4].SIZE: 16779270 + 00000201 VFD_FETCH[0x4].STRIDE: 513 + 00004004 VFD_FETCH[0x5].BASE: 0x4004 + 00000000 VFD_FETCH[0x5].BASE+0x1: 0 + 00000080 VFD_FETCH[0x5].SIZE: 128 + 00000000 VFD_FETCH[0x5].STRIDE: 0 + 14008030 VFD_FETCH[0x6].BASE: 0x14008030 + 0000e303 VFD_FETCH[0x6].BASE+0x1: 0xe303 + 10020400 VFD_FETCH[0x6].SIZE: 268567552 + 00000088 VFD_FETCH[0x6].STRIDE: 136 + 02000030 VFD_FETCH[0x7].BASE: 0x2000030 + 00001140 VFD_FETCH[0x7].BASE+0x1: 0x1140 + 40400000 VFD_FETCH[0x7].SIZE: 1077936128 + 00000041 VFD_FETCH[0x7].STRIDE: 65 + c0100100 VFD_FETCH[0x8].BASE: 0xc0100100 + 00001244 VFD_FETCH[0x8].BASE+0x1: 0x1244 + 00050004 VFD_FETCH[0x8].SIZE: 327684 + 00000040 VFD_FETCH[0x8].STRIDE: 64 + 00044000 VFD_FETCH[0x9].BASE: 0x44000 + 00000000 VFD_FETCH[0x9].BASE+0x1: 0 + 80000020 VFD_FETCH[0x9].SIZE: 2147483680 + 00000008 VFD_FETCH[0x9].STRIDE: 8 + 10006004 VFD_FETCH[0xa].BASE: 0x10006004 + 0000222a VFD_FETCH[0xa].BASE+0x1: 0x222a + 02042020 VFD_FETCH[0xa].SIZE: 33824800 + 00000681 VFD_FETCH[0xa].STRIDE: 1665 + 02101020 VFD_FETCH[0xb].BASE: 0x2101020 + 00000080 VFD_FETCH[0xb].BASE+0x1: 0x80 + 00040020 VFD_FETCH[0xb].SIZE: 262176 + 00000050 VFD_FETCH[0xb].STRIDE: 80 + 0a436062 VFD_FETCH[0xc].BASE: 0xa436062 + 00003041 VFD_FETCH[0xc].BASE+0x1: 0x3041 + 06102040 VFD_FETCH[0xc].SIZE: 101720128 + 00000200 VFD_FETCH[0xc].STRIDE: 512 + 00800864 VFD_FETCH[0xd].BASE: 0x800864 + 00000000 VFD_FETCH[0xd].BASE+0x1: 0 + 10400044 VFD_FETCH[0xd].SIZE: 272629828 + 00000010 VFD_FETCH[0xd].STRIDE: 16 + 061b8c2a VFD_FETCH[0xe].BASE: 0x61b8c2a + 00000004 VFD_FETCH[0xe].BASE+0x1: 0x4 + 01004391 VFD_FETCH[0xe].SIZE: 16794513 + 00000440 VFD_FETCH[0xe].STRIDE: 1088 + 02000000 VFD_FETCH[0xf].BASE: 0x2000000 + 00000200 VFD_FETCH[0xf].BASE+0x1: 0x200 + 41250000 VFD_FETCH[0xf].SIZE: 1092943872 + 00000010 VFD_FETCH[0xf].STRIDE: 16 + 01443027 VFD_FETCH[0x10].BASE: 0x1443027 + 00001000 VFD_FETCH[0x10].BASE+0x1: 0x1000 + c1100240 VFD_FETCH[0x10].SIZE: 3239051840 + 00000002 VFD_FETCH[0x10].STRIDE: 2 + 0000b404 VFD_FETCH[0x11].BASE: 0xb404 + 00000080 VFD_FETCH[0x11].BASE+0x1: 0x80 + 12404000 VFD_FETCH[0x11].SIZE: 306200576 + 00000280 VFD_FETCH[0x11].STRIDE: 640 + 8100011c VFD_FETCH[0x12].BASE: 0x8100011c + 00000218 VFD_FETCH[0x12].BASE+0x1: 0x218 + 0050b000 VFD_FETCH[0x12].SIZE: 5287936 + 00000462 VFD_FETCH[0x12].STRIDE: 1122 + 00004001 VFD_FETCH[0x13].BASE: 0x4001 + 0000000c VFD_FETCH[0x13].BASE+0x1: 0xc + 00810880 VFD_FETCH[0x13].SIZE: 8456320 + 00000000 VFD_FETCH[0x13].STRIDE: 0 + 00025022 VFD_FETCH[0x14].BASE: 0x25022 + 00000040 VFD_FETCH[0x14].BASE+0x1: 0x40 + 015c1040 VFD_FETCH[0x14].SIZE: 22810688 + 00000000 VFD_FETCH[0x14].STRIDE: 0 + 7a540120 VFD_FETCH[0x15].BASE: 0x7a540120 + 00000000 VFD_FETCH[0x15].BASE+0x1: 0 + 02800306 VFD_FETCH[0x15].SIZE: 41943814 + 00000024 VFD_FETCH[0x15].STRIDE: 36 + 00040f13 VFD_FETCH[0x16].BASE: 0x40f13 + 00000850 VFD_FETCH[0x16].BASE+0x1: 0x850 + 00425010 VFD_FETCH[0x16].SIZE: 4345872 + 00000408 VFD_FETCH[0x16].STRIDE: 1032 + 04012000 VFD_FETCH[0x17].BASE: 0x4012000 + 00004111 VFD_FETCH[0x17].BASE+0x1: 0x4111 + 08012800 VFD_FETCH[0x17].SIZE: 134293504 + 00000000 VFD_FETCH[0x17].STRIDE: 0 + 00022003 VFD_FETCH[0x18].BASE: 0x22003 + 00000000 VFD_FETCH[0x18].BASE+0x1: 0 + 504228ac VFD_FETCH[0x18].SIZE: 1346513068 + 00000300 VFD_FETCH[0x18].STRIDE: 768 + 40a40080 VFD_FETCH[0x19].BASE: 0x40a40080 + 0000c010 VFD_FETCH[0x19].BASE+0x1: 0xc010 + 00002000 VFD_FETCH[0x19].SIZE: 8192 + 00000101 VFD_FETCH[0x19].STRIDE: 257 + 88248411 VFD_FETCH[0x1a].BASE: 0x88248411 + 00000400 VFD_FETCH[0x1a].BASE+0x1: 0x400 + 2604c030 VFD_FETCH[0x1a].SIZE: 637845552 + 00000020 VFD_FETCH[0x1a].STRIDE: 32 + 00000000 VFD_FETCH[0x1b].BASE: 0 + 00000924 VFD_FETCH[0x1b].BASE+0x1: 0x924 + 00100000 VFD_FETCH[0x1b].SIZE: 1048576 + 00000000 VFD_FETCH[0x1b].STRIDE: 0 + 048c1100 VFD_FETCH[0x1c].BASE: 0x48c1100 + 00000b06 VFD_FETCH[0x1c].BASE+0x1: 0xb06 + 00007264 VFD_FETCH[0x1c].SIZE: 29284 + 00000c11 VFD_FETCH[0x1c].STRIDE: 3089 + 00000120 VFD_FETCH[0x1d].BASE: 0x120 + 00004547 VFD_FETCH[0x1d].BASE+0x1: 0x4547 + 46000080 VFD_FETCH[0x1d].SIZE: 1174405248 + 00000100 VFD_FETCH[0x1d].STRIDE: 256 + 001a026c VFD_FETCH[0x1e].BASE: 0x1a026c + 00000545 VFD_FETCH[0x1e].BASE+0x1: 0x545 + 22500060 VFD_FETCH[0x1e].SIZE: 575668320 + 00000002 VFD_FETCH[0x1e].STRIDE: 2 + 00041100 VFD_FETCH[0x1f].BASE: 0x41100 + 00001100 VFD_FETCH[0x1f].BASE+0x1: 0x1100 + 01810080 VFD_FETCH[0x1f].SIZE: 25231488 + 00000020 VFD_FETCH[0x1f].STRIDE: 32 + 00002320 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0x119 | FORMAT = 0 | SWAP = WZYX } + 4698e051 VFD_DECODE[0].STEP_RATE: 0x4698e051 + 00000000 VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } + 00400015 VFD_DECODE[0x1].STEP_RATE: 0x400015 + 00002400 VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x120 | FORMAT = 0 | SWAP = WZYX } + 0228c300 VFD_DECODE[0x2].STEP_RATE: 0x228c300 + 00008040 VFD_DECODE[0x3].INSTR: { IDX = 0 | OFFSET = 0x402 | FORMAT = 0 | SWAP = WZYX } + 40804000 VFD_DECODE[0x3].STEP_RATE: 0x40804000 + 00000180 VFD_DECODE[0x4].INSTR: { IDX = 0 | OFFSET = 0xc | FORMAT = 0 | SWAP = WZYX } + 20801028 VFD_DECODE[0x4].STEP_RATE: 0x20801028 + 00002800 VFD_DECODE[0x5].INSTR: { IDX = 0 | OFFSET = 0x140 | FORMAT = 0 | SWAP = WZYX } + 50004104 VFD_DECODE[0x5].STEP_RATE: 0x50004104 + 00000040 VFD_DECODE[0x6].INSTR: { IDX = 0 | OFFSET = 0x2 | FORMAT = 0 | SWAP = WZYX } + c9708400 VFD_DECODE[0x6].STEP_RATE: 0xc9708400 + 00008a00 VFD_DECODE[0x7].INSTR: { IDX = 0 | OFFSET = 0x450 | FORMAT = 0 | SWAP = WZYX } + 00000180 VFD_DECODE[0x7].STEP_RATE: 0x180 + 00018910 VFD_DECODE[0x8].INSTR: { IDX = 16 | OFFSET = 0xc48 | FORMAT = 0 | SWAP = WZYX } + 00202080 VFD_DECODE[0x8].STEP_RATE: 0x202080 + 00000200 VFD_DECODE[0x9].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = 0 | SWAP = WZYX } + 10000400 VFD_DECODE[0x9].STEP_RATE: 0x10000400 + 00019180 VFD_DECODE[0xa].INSTR: { IDX = 0 | OFFSET = 0xc8c | FORMAT = 0 | SWAP = WZYX } + 00010881 VFD_DECODE[0xa].STEP_RATE: 0x10881 + 00002200 VFD_DECODE[0xb].INSTR: { IDX = 0 | OFFSET = 0x110 | FORMAT = 0 | SWAP = WZYX } + 00000008 VFD_DECODE[0xb].STEP_RATE: 0x8 + 00000090 VFD_DECODE[0xc].INSTR: { IDX = 16 | OFFSET = 0x4 | FORMAT = 0 | SWAP = WZYX } + 00108040 VFD_DECODE[0xc].STEP_RATE: 0x108040 + 00002002 VFD_DECODE[0xd].INSTR: { IDX = 2 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } + 40040004 VFD_DECODE[0xd].STEP_RATE: 0x40040004 + 00000000 VFD_DECODE[0xe].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } + 00418202 VFD_DECODE[0xe].STEP_RATE: 0x418202 + 00011200 VFD_DECODE[0xf].INSTR: { IDX = 0 | OFFSET = 0x890 | FORMAT = 0 | SWAP = WZYX } + 05000504 VFD_DECODE[0xf].STEP_RATE: 0x5000504 + 00002002 VFD_DECODE[0x10].INSTR: { IDX = 2 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } + 20210026 VFD_DECODE[0x10].STEP_RATE: 0x20210026 + 00000008 VFD_DECODE[0x11].INSTR: { IDX = 8 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } + 00010400 VFD_DECODE[0x11].STEP_RATE: 0x10400 + 00009000 VFD_DECODE[0x12].INSTR: { IDX = 0 | OFFSET = 0x480 | FORMAT = 0 | SWAP = WZYX } + 00000000 VFD_DECODE[0x12].STEP_RATE: 0 + 00002000 VFD_DECODE[0x13].INSTR: { IDX = 0 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } + 10080000 VFD_DECODE[0x13].STEP_RATE: 0x10080000 + 00001200 VFD_DECODE[0x14].INSTR: { IDX = 0 | OFFSET = 0x90 | FORMAT = 0 | SWAP = WZYX } + 20048020 VFD_DECODE[0x14].STEP_RATE: 0x20048020 + 00000106 VFD_DECODE[0x15].INSTR: { IDX = 6 | OFFSET = 0x8 | FORMAT = 0 | SWAP = WZYX } + 0a200812 VFD_DECODE[0x15].STEP_RATE: 0xa200812 + 00008042 VFD_DECODE[0x16].INSTR: { IDX = 2 | OFFSET = 0x402 | FORMAT = 0 | SWAP = WZYX } + 00140250 VFD_DECODE[0x16].STEP_RATE: 0x140250 + 00008080 VFD_DECODE[0x17].INSTR: { IDX = 0 | OFFSET = 0x404 | FORMAT = 0 | SWAP = WZYX } + 120000c0 VFD_DECODE[0x17].STEP_RATE: 0x120000c0 + 00000482 VFD_DECODE[0x18].INSTR: { IDX = 2 | OFFSET = 0x24 | FORMAT = 0 | SWAP = WZYX } + 00400880 VFD_DECODE[0x18].STEP_RATE: 0x400880 + 00002000 VFD_DECODE[0x19].INSTR: { IDX = 0 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } + 00201000 VFD_DECODE[0x19].STEP_RATE: 0x201000 + 00000000 VFD_DECODE[0x1a].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } + 40000802 VFD_DECODE[0x1a].STEP_RATE: 0x40000802 + 00000028 VFD_DECODE[0x1b].INSTR: { IDX = 8 | OFFSET = 0x1 | FORMAT = 0 | SWAP = WZYX } + 0020a120 VFD_DECODE[0x1b].STEP_RATE: 0x20a120 + 00012480 VFD_DECODE[0x1c].INSTR: { IDX = 0 | OFFSET = 0x924 | FORMAT = 0 | SWAP = WZYX } + 09004200 VFD_DECODE[0x1c].STEP_RATE: 0x9004200 + 00008080 VFD_DECODE[0x1d].INSTR: { IDX = 0 | OFFSET = 0x404 | FORMAT = 0 | SWAP = WZYX } + 00004004 VFD_DECODE[0x1d].STEP_RATE: 0x4004 + 00010888 VFD_DECODE[0x1e].INSTR: { IDX = 8 | OFFSET = 0x844 | FORMAT = 0 | SWAP = WZYX } + 000000b4 VFD_DECODE[0x1e].STEP_RATE: 0xb4 + 00008000 VFD_DECODE[0x1f].INSTR: { IDX = 0 | OFFSET = 0x400 | FORMAT = 0 | SWAP = WZYX } + 04800000 VFD_DECODE[0x1f].STEP_RATE: 0x4800000 + 00000445 VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0x5 | REGID = r17.x } + 00000004 VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0x4 | REGID = r0.x } + 00000804 VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x4 | REGID = r32.x } + 00000040 VFD_DEST_CNTL[0x3].INSTR: { WRITEMASK = 0 | REGID = r1.x } + 00000400 VFD_DEST_CNTL[0x4].INSTR: { WRITEMASK = 0 | REGID = r16.x } + 00000000 VFD_DEST_CNTL[0x5].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000013 VFD_DEST_CNTL[0x6].INSTR: { WRITEMASK = 0x3 | REGID = r0.y } + 00000048 VFD_DEST_CNTL[0x7].INSTR: { WRITEMASK = 0x8 | REGID = r1.x } + 00000042 VFD_DEST_CNTL[0x8].INSTR: { WRITEMASK = 0x2 | REGID = r1.x } + 00000000 VFD_DEST_CNTL[0x9].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000802 VFD_DEST_CNTL[0xa].INSTR: { WRITEMASK = 0x2 | REGID = r32.x } + 00000000 VFD_DEST_CNTL[0xb].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000501 VFD_DEST_CNTL[0xc].INSTR: { WRITEMASK = 0x1 | REGID = r20.x } + 00000002 VFD_DEST_CNTL[0xd].INSTR: { WRITEMASK = 0x2 | REGID = r0.x } + 00000000 VFD_DEST_CNTL[0xe].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000c80 VFD_DEST_CNTL[0xf].INSTR: { WRITEMASK = 0 | REGID = r50.x } + 00000405 VFD_DEST_CNTL[0x10].INSTR: { WRITEMASK = 0x5 | REGID = r16.x } + 00000000 VFD_DEST_CNTL[0x11].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000100 VFD_DEST_CNTL[0x12].INSTR: { WRITEMASK = 0 | REGID = r4.x } + 00000000 VFD_DEST_CNTL[0x13].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000000 VFD_DEST_CNTL[0x14].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000000 VFD_DEST_CNTL[0x15].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000800 VFD_DEST_CNTL[0x16].INSTR: { WRITEMASK = 0 | REGID = r32.x } + 00000040 VFD_DEST_CNTL[0x17].INSTR: { WRITEMASK = 0 | REGID = r1.x } + 00000000 VFD_DEST_CNTL[0x18].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000000 VFD_DEST_CNTL[0x19].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000200 VFD_DEST_CNTL[0x1a].INSTR: { WRITEMASK = 0 | REGID = r8.x } + 00000060 VFD_DEST_CNTL[0x1b].INSTR: { WRITEMASK = 0 | REGID = r1.z } + 000005c4 VFD_DEST_CNTL[0x1c].INSTR: { WRITEMASK = 0x4 | REGID = r23.x } + 00000480 VFD_DEST_CNTL[0x1d].INSTR: { WRITEMASK = 0 | REGID = r18.x } + 00000000 VFD_DEST_CNTL[0x1e].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000400 VFD_DEST_CNTL[0x1f].INSTR: { WRITEMASK = 0 | REGID = r16.x } + 00000001 SP_UNKNOWN_A0F8: 0x1 + - context: 1 + 00000000 VPC_UNKNOWN_9300: 0 + 00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | UNKLOC = 255 } + 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_DISABLE: { 0 } + 00000000 PC_TESS_NUM_VERTEX: 0 + 00000000 PC_HS_INPUT_SIZE: { SIZE = 0 } + 00000000 PC_TESS_CNTL: { SPACING = TESS_EQUAL | OUTPUT = TESS_POINTS } + ffffffff PC_RESTART_INDEX: 4294967295 + 0000001f PC_MODE_CNTL: 0x1f + 00000001 PC_UNKNOWN_9805: 0x1 + 00000000 PC_PRIMID_PASSTHRU: FALSE + 00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST } + 00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000001 PC_GS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000000 PC_PRIMITIVE_CNTL_3: 0 + 00000001 PC_DS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000000 PC_PRIMITIVE_CNTL_5: { GS_VERTICES_OUT = 0 | GS_INVOCATIONS = 0 | GS_OUTPUT = TESS_POINTS } + 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } + 00000000 PC_UNKNOWN_9B07: 0 + 00000000 VFD_CONTROL_0: { FETCH_CNT = 0 | DECODE_CNT = 0 } + fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | 0xfc000000 } + 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } + fcfcfcfc VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } + 000000fc VFD_CONTROL_4: 0xfc + 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + 00000000 VFD_CONTROL_6: { 0 } + 00000000 VFD_MODE_CNTL: { 0 } + 00000000 VFD_UNKNOWN_A008: 0 + 00000000 VFD_ADD_OFFSET: { 0 } + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 VFD_INSTANCE_START_OFFSET: 0 + 1618e045 VFD_FETCH[0].BASE: 0x1618e045 + 00005505 VFD_FETCH[0].BASE+0x1: 0x5505 + 00840800 VFD_FETCH[0].SIZE: 8652800 + 00000051 VFD_FETCH[0].STRIDE: 81 + 01100401 VFD_FETCH[0x1].BASE: 0x1100401 + 00000040 VFD_FETCH[0x1].BASE+0x1: 0x40 + 04010402 VFD_FETCH[0x1].SIZE: 67175426 + 00000000 VFD_FETCH[0x1].STRIDE: 0 + 40080120 VFD_FETCH[0x2].BASE: 0x40080120 + 00004000 VFD_FETCH[0x2].BASE+0x1: 0x4000 + 00140100 VFD_FETCH[0x2].SIZE: 1310976 + 00000002 VFD_FETCH[0x2].STRIDE: 2 + 00001090 VFD_FETCH[0x3].BASE: 0x1090 + 00000200 VFD_FETCH[0x3].BASE+0x1: 0x200 + 11040100 VFD_FETCH[0x3].SIZE: 285475072 + 00000000 VFD_FETCH[0x3].STRIDE: 0 + 04000900 VFD_FETCH[0x4].BASE: 0x4000900 + 00000451 VFD_FETCH[0x4].BASE+0x1: 0x451 + 01000806 VFD_FETCH[0x4].SIZE: 16779270 + 00000201 VFD_FETCH[0x4].STRIDE: 513 + 00004004 VFD_FETCH[0x5].BASE: 0x4004 + 00000000 VFD_FETCH[0x5].BASE+0x1: 0 + 00000080 VFD_FETCH[0x5].SIZE: 128 + 00000000 VFD_FETCH[0x5].STRIDE: 0 + 14008030 VFD_FETCH[0x6].BASE: 0x14008030 + 0000e303 VFD_FETCH[0x6].BASE+0x1: 0xe303 + 10020400 VFD_FETCH[0x6].SIZE: 268567552 + 00000088 VFD_FETCH[0x6].STRIDE: 136 + 02000030 VFD_FETCH[0x7].BASE: 0x2000030 + 00001140 VFD_FETCH[0x7].BASE+0x1: 0x1140 + 40400000 VFD_FETCH[0x7].SIZE: 1077936128 + 00000041 VFD_FETCH[0x7].STRIDE: 65 + c0100100 VFD_FETCH[0x8].BASE: 0xc0100100 + 00001244 VFD_FETCH[0x8].BASE+0x1: 0x1244 + 00050004 VFD_FETCH[0x8].SIZE: 327684 + 00000040 VFD_FETCH[0x8].STRIDE: 64 + 00044000 VFD_FETCH[0x9].BASE: 0x44000 + 00000000 VFD_FETCH[0x9].BASE+0x1: 0 + 80000020 VFD_FETCH[0x9].SIZE: 2147483680 + 00000008 VFD_FETCH[0x9].STRIDE: 8 + 10006004 VFD_FETCH[0xa].BASE: 0x10006004 + 0000222a VFD_FETCH[0xa].BASE+0x1: 0x222a + 02042020 VFD_FETCH[0xa].SIZE: 33824800 + 00000681 VFD_FETCH[0xa].STRIDE: 1665 + 02101020 VFD_FETCH[0xb].BASE: 0x2101020 + 00000080 VFD_FETCH[0xb].BASE+0x1: 0x80 + 00040020 VFD_FETCH[0xb].SIZE: 262176 + 00000050 VFD_FETCH[0xb].STRIDE: 80 + 0a436062 VFD_FETCH[0xc].BASE: 0xa436062 + 00003041 VFD_FETCH[0xc].BASE+0x1: 0x3041 + 06102040 VFD_FETCH[0xc].SIZE: 101720128 + 00000200 VFD_FETCH[0xc].STRIDE: 512 + 00800864 VFD_FETCH[0xd].BASE: 0x800864 + 00000000 VFD_FETCH[0xd].BASE+0x1: 0 + 10400044 VFD_FETCH[0xd].SIZE: 272629828 + 00000010 VFD_FETCH[0xd].STRIDE: 16 + 061b8c2a VFD_FETCH[0xe].BASE: 0x61b8c2a + 00000004 VFD_FETCH[0xe].BASE+0x1: 0x4 + 01004391 VFD_FETCH[0xe].SIZE: 16794513 + 00000440 VFD_FETCH[0xe].STRIDE: 1088 + 02000000 VFD_FETCH[0xf].BASE: 0x2000000 + 00000200 VFD_FETCH[0xf].BASE+0x1: 0x200 + 41250000 VFD_FETCH[0xf].SIZE: 1092943872 + 00000010 VFD_FETCH[0xf].STRIDE: 16 + 01443027 VFD_FETCH[0x10].BASE: 0x1443027 + 00001000 VFD_FETCH[0x10].BASE+0x1: 0x1000 + c1100240 VFD_FETCH[0x10].SIZE: 3239051840 + 00000002 VFD_FETCH[0x10].STRIDE: 2 + 0000b404 VFD_FETCH[0x11].BASE: 0xb404 + 00000080 VFD_FETCH[0x11].BASE+0x1: 0x80 + 12404000 VFD_FETCH[0x11].SIZE: 306200576 + 00000280 VFD_FETCH[0x11].STRIDE: 640 + 8100011c VFD_FETCH[0x12].BASE: 0x8100011c + 00000218 VFD_FETCH[0x12].BASE+0x1: 0x218 + 0050b000 VFD_FETCH[0x12].SIZE: 5287936 + 00000462 VFD_FETCH[0x12].STRIDE: 1122 + 00004001 VFD_FETCH[0x13].BASE: 0x4001 + 0000000c VFD_FETCH[0x13].BASE+0x1: 0xc + 00810880 VFD_FETCH[0x13].SIZE: 8456320 + 00000000 VFD_FETCH[0x13].STRIDE: 0 + 00025022 VFD_FETCH[0x14].BASE: 0x25022 + 00000040 VFD_FETCH[0x14].BASE+0x1: 0x40 + 015c1040 VFD_FETCH[0x14].SIZE: 22810688 + 00000000 VFD_FETCH[0x14].STRIDE: 0 + 7a540120 VFD_FETCH[0x15].BASE: 0x7a540120 + 00000000 VFD_FETCH[0x15].BASE+0x1: 0 + 02800306 VFD_FETCH[0x15].SIZE: 41943814 + 00000024 VFD_FETCH[0x15].STRIDE: 36 + 00040f13 VFD_FETCH[0x16].BASE: 0x40f13 + 00000850 VFD_FETCH[0x16].BASE+0x1: 0x850 + 00425010 VFD_FETCH[0x16].SIZE: 4345872 + 00000408 VFD_FETCH[0x16].STRIDE: 1032 + 04012000 VFD_FETCH[0x17].BASE: 0x4012000 + 00004111 VFD_FETCH[0x17].BASE+0x1: 0x4111 + 08012800 VFD_FETCH[0x17].SIZE: 134293504 + 00000000 VFD_FETCH[0x17].STRIDE: 0 + 00022003 VFD_FETCH[0x18].BASE: 0x22003 + 00000000 VFD_FETCH[0x18].BASE+0x1: 0 + 504228ac VFD_FETCH[0x18].SIZE: 1346513068 + 00000300 VFD_FETCH[0x18].STRIDE: 768 + 40a40080 VFD_FETCH[0x19].BASE: 0x40a40080 + 0000c010 VFD_FETCH[0x19].BASE+0x1: 0xc010 + 00002000 VFD_FETCH[0x19].SIZE: 8192 + 00000101 VFD_FETCH[0x19].STRIDE: 257 + 88248411 VFD_FETCH[0x1a].BASE: 0x88248411 + 00000400 VFD_FETCH[0x1a].BASE+0x1: 0x400 + 2604c030 VFD_FETCH[0x1a].SIZE: 637845552 + 00000020 VFD_FETCH[0x1a].STRIDE: 32 + 00000000 VFD_FETCH[0x1b].BASE: 0 + 00000924 VFD_FETCH[0x1b].BASE+0x1: 0x924 + 00100000 VFD_FETCH[0x1b].SIZE: 1048576 + 00000000 VFD_FETCH[0x1b].STRIDE: 0 + 048c1100 VFD_FETCH[0x1c].BASE: 0x48c1100 + 00000b06 VFD_FETCH[0x1c].BASE+0x1: 0xb06 + 00007264 VFD_FETCH[0x1c].SIZE: 29284 + 00000c11 VFD_FETCH[0x1c].STRIDE: 3089 + 00000120 VFD_FETCH[0x1d].BASE: 0x120 + 00004547 VFD_FETCH[0x1d].BASE+0x1: 0x4547 + 46000080 VFD_FETCH[0x1d].SIZE: 1174405248 + 00000100 VFD_FETCH[0x1d].STRIDE: 256 + 001a026c VFD_FETCH[0x1e].BASE: 0x1a026c + 00000545 VFD_FETCH[0x1e].BASE+0x1: 0x545 + 22500060 VFD_FETCH[0x1e].SIZE: 575668320 + 00000002 VFD_FETCH[0x1e].STRIDE: 2 + 00041100 VFD_FETCH[0x1f].BASE: 0x41100 + 00001100 VFD_FETCH[0x1f].BASE+0x1: 0x1100 + 01810080 VFD_FETCH[0x1f].SIZE: 25231488 + 00000020 VFD_FETCH[0x1f].STRIDE: 32 + 00002320 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0x119 | FORMAT = 0 | SWAP = WZYX } + 4698e051 VFD_DECODE[0].STEP_RATE: 0x4698e051 + 00000000 VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } + 00400015 VFD_DECODE[0x1].STEP_RATE: 0x400015 + 00002400 VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x120 | FORMAT = 0 | SWAP = WZYX } + 0228c300 VFD_DECODE[0x2].STEP_RATE: 0x228c300 + 00008040 VFD_DECODE[0x3].INSTR: { IDX = 0 | OFFSET = 0x402 | FORMAT = 0 | SWAP = WZYX } + 40804000 VFD_DECODE[0x3].STEP_RATE: 0x40804000 + 00000180 VFD_DECODE[0x4].INSTR: { IDX = 0 | OFFSET = 0xc | FORMAT = 0 | SWAP = WZYX } + 20801028 VFD_DECODE[0x4].STEP_RATE: 0x20801028 + 00002800 VFD_DECODE[0x5].INSTR: { IDX = 0 | OFFSET = 0x140 | FORMAT = 0 | SWAP = WZYX } + 50004104 VFD_DECODE[0x5].STEP_RATE: 0x50004104 + 00000040 VFD_DECODE[0x6].INSTR: { IDX = 0 | OFFSET = 0x2 | FORMAT = 0 | SWAP = WZYX } + c9708400 VFD_DECODE[0x6].STEP_RATE: 0xc9708400 + 00008a00 VFD_DECODE[0x7].INSTR: { IDX = 0 | OFFSET = 0x450 | FORMAT = 0 | SWAP = WZYX } + 00000180 VFD_DECODE[0x7].STEP_RATE: 0x180 + 00018910 VFD_DECODE[0x8].INSTR: { IDX = 16 | OFFSET = 0xc48 | FORMAT = 0 | SWAP = WZYX } + 00202080 VFD_DECODE[0x8].STEP_RATE: 0x202080 + 00000200 VFD_DECODE[0x9].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = 0 | SWAP = WZYX } + 10000400 VFD_DECODE[0x9].STEP_RATE: 0x10000400 + 00019180 VFD_DECODE[0xa].INSTR: { IDX = 0 | OFFSET = 0xc8c | FORMAT = 0 | SWAP = WZYX } + 00010881 VFD_DECODE[0xa].STEP_RATE: 0x10881 + 00002200 VFD_DECODE[0xb].INSTR: { IDX = 0 | OFFSET = 0x110 | FORMAT = 0 | SWAP = WZYX } + 00000008 VFD_DECODE[0xb].STEP_RATE: 0x8 + 00000090 VFD_DECODE[0xc].INSTR: { IDX = 16 | OFFSET = 0x4 | FORMAT = 0 | SWAP = WZYX } + 00108040 VFD_DECODE[0xc].STEP_RATE: 0x108040 + 00002002 VFD_DECODE[0xd].INSTR: { IDX = 2 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } + 40040004 VFD_DECODE[0xd].STEP_RATE: 0x40040004 + 00000000 VFD_DECODE[0xe].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } + 00418202 VFD_DECODE[0xe].STEP_RATE: 0x418202 + 00011200 VFD_DECODE[0xf].INSTR: { IDX = 0 | OFFSET = 0x890 | FORMAT = 0 | SWAP = WZYX } + 05000504 VFD_DECODE[0xf].STEP_RATE: 0x5000504 + 00002002 VFD_DECODE[0x10].INSTR: { IDX = 2 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } + 20210026 VFD_DECODE[0x10].STEP_RATE: 0x20210026 + 00000008 VFD_DECODE[0x11].INSTR: { IDX = 8 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } + 00010400 VFD_DECODE[0x11].STEP_RATE: 0x10400 + 00009000 VFD_DECODE[0x12].INSTR: { IDX = 0 | OFFSET = 0x480 | FORMAT = 0 | SWAP = WZYX } + 00000000 VFD_DECODE[0x12].STEP_RATE: 0 + 00002000 VFD_DECODE[0x13].INSTR: { IDX = 0 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } + 10080000 VFD_DECODE[0x13].STEP_RATE: 0x10080000 + 00001200 VFD_DECODE[0x14].INSTR: { IDX = 0 | OFFSET = 0x90 | FORMAT = 0 | SWAP = WZYX } + 20048020 VFD_DECODE[0x14].STEP_RATE: 0x20048020 + 00000106 VFD_DECODE[0x15].INSTR: { IDX = 6 | OFFSET = 0x8 | FORMAT = 0 | SWAP = WZYX } + 0a200812 VFD_DECODE[0x15].STEP_RATE: 0xa200812 + 00008042 VFD_DECODE[0x16].INSTR: { IDX = 2 | OFFSET = 0x402 | FORMAT = 0 | SWAP = WZYX } + 00140250 VFD_DECODE[0x16].STEP_RATE: 0x140250 + 00008080 VFD_DECODE[0x17].INSTR: { IDX = 0 | OFFSET = 0x404 | FORMAT = 0 | SWAP = WZYX } + 120000c0 VFD_DECODE[0x17].STEP_RATE: 0x120000c0 + 00000482 VFD_DECODE[0x18].INSTR: { IDX = 2 | OFFSET = 0x24 | FORMAT = 0 | SWAP = WZYX } + 00400880 VFD_DECODE[0x18].STEP_RATE: 0x400880 + 00002000 VFD_DECODE[0x19].INSTR: { IDX = 0 | OFFSET = 0x100 | FORMAT = 0 | SWAP = WZYX } + 00201000 VFD_DECODE[0x19].STEP_RATE: 0x201000 + 00000000 VFD_DECODE[0x1a].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = 0 | SWAP = WZYX } + 40000802 VFD_DECODE[0x1a].STEP_RATE: 0x40000802 + 00000028 VFD_DECODE[0x1b].INSTR: { IDX = 8 | OFFSET = 0x1 | FORMAT = 0 | SWAP = WZYX } + 0020a120 VFD_DECODE[0x1b].STEP_RATE: 0x20a120 + 00012480 VFD_DECODE[0x1c].INSTR: { IDX = 0 | OFFSET = 0x924 | FORMAT = 0 | SWAP = WZYX } + 09004200 VFD_DECODE[0x1c].STEP_RATE: 0x9004200 + 00008080 VFD_DECODE[0x1d].INSTR: { IDX = 0 | OFFSET = 0x404 | FORMAT = 0 | SWAP = WZYX } + 00004004 VFD_DECODE[0x1d].STEP_RATE: 0x4004 + 00010888 VFD_DECODE[0x1e].INSTR: { IDX = 8 | OFFSET = 0x844 | FORMAT = 0 | SWAP = WZYX } + 000000b4 VFD_DECODE[0x1e].STEP_RATE: 0xb4 + 00008000 VFD_DECODE[0x1f].INSTR: { IDX = 0 | OFFSET = 0x400 | FORMAT = 0 | SWAP = WZYX } + 04800000 VFD_DECODE[0x1f].STEP_RATE: 0x4800000 + 00000445 VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0x5 | REGID = r17.x } + 00000004 VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0x4 | REGID = r0.x } + 00000804 VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x4 | REGID = r32.x } + 00000040 VFD_DEST_CNTL[0x3].INSTR: { WRITEMASK = 0 | REGID = r1.x } + 00000400 VFD_DEST_CNTL[0x4].INSTR: { WRITEMASK = 0 | REGID = r16.x } + 00000000 VFD_DEST_CNTL[0x5].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000013 VFD_DEST_CNTL[0x6].INSTR: { WRITEMASK = 0x3 | REGID = r0.y } + 00000048 VFD_DEST_CNTL[0x7].INSTR: { WRITEMASK = 0x8 | REGID = r1.x } + 00000042 VFD_DEST_CNTL[0x8].INSTR: { WRITEMASK = 0x2 | REGID = r1.x } + 00000000 VFD_DEST_CNTL[0x9].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000802 VFD_DEST_CNTL[0xa].INSTR: { WRITEMASK = 0x2 | REGID = r32.x } + 00000000 VFD_DEST_CNTL[0xb].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000501 VFD_DEST_CNTL[0xc].INSTR: { WRITEMASK = 0x1 | REGID = r20.x } + 00000002 VFD_DEST_CNTL[0xd].INSTR: { WRITEMASK = 0x2 | REGID = r0.x } + 00000000 VFD_DEST_CNTL[0xe].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000c80 VFD_DEST_CNTL[0xf].INSTR: { WRITEMASK = 0 | REGID = r50.x } + 00000405 VFD_DEST_CNTL[0x10].INSTR: { WRITEMASK = 0x5 | REGID = r16.x } + 00000000 VFD_DEST_CNTL[0x11].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000100 VFD_DEST_CNTL[0x12].INSTR: { WRITEMASK = 0 | REGID = r4.x } + 00000000 VFD_DEST_CNTL[0x13].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000000 VFD_DEST_CNTL[0x14].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000000 VFD_DEST_CNTL[0x15].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000800 VFD_DEST_CNTL[0x16].INSTR: { WRITEMASK = 0 | REGID = r32.x } + 00000040 VFD_DEST_CNTL[0x17].INSTR: { WRITEMASK = 0 | REGID = r1.x } + 00000000 VFD_DEST_CNTL[0x18].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000000 VFD_DEST_CNTL[0x19].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000200 VFD_DEST_CNTL[0x1a].INSTR: { WRITEMASK = 0 | REGID = r8.x } + 00000060 VFD_DEST_CNTL[0x1b].INSTR: { WRITEMASK = 0 | REGID = r1.z } + 000005c4 VFD_DEST_CNTL[0x1c].INSTR: { WRITEMASK = 0x4 | REGID = r23.x } + 00000480 VFD_DEST_CNTL[0x1d].INSTR: { WRITEMASK = 0 | REGID = r18.x } + 00000000 VFD_DEST_CNTL[0x1e].INSTR: { WRITEMASK = 0 | REGID = r0.x } + 00000400 VFD_DEST_CNTL[0x1f].INSTR: { WRITEMASK = 0 | REGID = r16.x } + 00000001 SP_UNKNOWN_A0F8: 0x1 + - cluster-name: CLUSTER_PC_VS + - context: 0 + 000000ff VPC_UNKNOWN_9100: 0xff + 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } + 00ffff00 VPC_GS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } + 00ffff00 VPC_DS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } + 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } + 0000ffff VPC_GS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } + 0000ffff VPC_DS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } + 00000000 VPC_UNKNOWN_9107: 0 + 00000003 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } + 00000000 VPC_UNKNOWN_9300: 0 + 00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | UNKLOC = 255 } + 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_DISABLE: { 0 } + 00000000 PC_UNKNOWN_9980: 0 + 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } + 00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST } + 00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000001 PC_GS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000000 PC_PRIMITIVE_CNTL_3: 0 + 00000001 PC_DS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000000 PC_PRIMITIVE_CNTL_5: { GS_VERTICES_OUT = 0 | GS_INVOCATIONS = 0 | GS_OUTPUT = TESS_POINTS } + 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } + 00000000 PC_UNKNOWN_9B07: 0 + - context: 1 + 000000ff VPC_UNKNOWN_9100: 0xff + 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } + 00ffff00 VPC_GS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } + 00ffff00 VPC_DS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } + 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } + 0000ffff VPC_GS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } + 0000ffff VPC_DS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } + 00000000 VPC_UNKNOWN_9107: 0 + 00000003 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } + 00000000 VPC_UNKNOWN_9300: 0 + 00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 } + ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | UNKLOC = 255 } + 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_DISABLE: { 0 } + 00000000 PC_UNKNOWN_9980: 0 + 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } + 00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST } + 00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000001 PC_GS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000000 PC_PRIMITIVE_CNTL_3: 0 + 00000001 PC_DS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } + 00000000 PC_PRIMITIVE_CNTL_5: { GS_VERTICES_OUT = 0 | GS_INVOCATIONS = 0 | GS_OUTPUT = TESS_POINTS } + 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } + 00000000 PC_UNKNOWN_9B07: 0 + - cluster-name: CLUSTER_SP_VS + - context: 0 + 00000140 HLSQ_VS_CNTL: { CONSTLEN = 256 | ENABLED } + 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 } + 00000000 HLSQ_DS_CNTL: { CONSTLEN = 0 } + 00000100 HLSQ_GS_CNTL: { CONSTLEN = 0 | ENABLED } + 40204000 HLSQ_LOAD_STATE_GEOM_CMD: 0x40204000 + 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR: 0 + 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR+0x1: 0 + - context: 1 + 00000140 HLSQ_VS_CNTL: { CONSTLEN = 256 | ENABLED } + 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 } + 00000000 HLSQ_DS_CNTL: { CONSTLEN = 0 } + 00000100 HLSQ_GS_CNTL: { CONSTLEN = 0 | ENABLED } + 40204000 HLSQ_LOAD_STATE_GEOM_CMD: 0x40204000 + 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR: 0 + 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR+0x1: 0 + - cluster-name: CLUSTER_SP_VS + - context: 0 + 00000000 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } + 00000000 SP_VS_BRANCH_COND: 0 + 00000000 SP_VS_PRIMITIVE_CNTL: { OUT = 0 } + 00000000 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_UNKNOWN_A81B: 0 + 8e5d7d37 SP_VS_OBJ_START_LO: 0x8e5d7d37 + 0001fcd5 SP_VS_OBJ_START_HI: 0x1fcd5 + 00000000 0xa81e: 00000000 + 00000000 0xa81f: 00000000 + 00000000 0xa820: 00000000 + 00000000 0xa821: 00000000 + 00000080 SP_VS_TEX_COUNT: 128 + 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_VS_INSTRLEN: 0 + 00000000 SP_HS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } + 00000000 SP_HS_UNKNOWN_A831: 0 + 00000000 0xa832: 00000000 + 00000000 SP_HS_UNKNOWN_A833: 0 + 780a8ca5 SP_HS_OBJ_START_LO: 0x780a8ca5 + 0001aad2 SP_HS_OBJ_START_HI: 0x1aad2 + 00000000 0xa836: 00000000 + 00000000 0xa837: 00000000 + 00000000 0xa838: 00000000 + 00000000 0xa839: 00000000 + 00000080 SP_HS_TEX_COUNT: 128 + 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_HS_INSTRLEN: 0 + 00000000 SP_DS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } + 00000000 0xa841: 00000000 + 00000000 SP_DS_PRIMITIVE_CNTL: { OUT = 0 } + 00000000 SP_DS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_UNKNOWN_A85B: 0 + 7abf500d SP_DS_OBJ_START_LO: 0x7abf500d + 00017e52 SP_DS_OBJ_START_HI: 0x17e52 + 00000000 0xa85e: 00000000 + 00000000 0xa85f: 00000000 + 00000000 0xa860: 00000000 + 00000000 0xa861: 00000000 + 00000080 SP_DS_TEX_COUNT: 128 + 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_DS_INSTRLEN: 0 + 00000000 SP_GS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } + 00000000 SP_GS_PRIM_SIZE: 0 + 00000000 SP_GS_BRANCH_COND: 0 + 00000000 SP_GS_PRIMITIVE_CNTL: { OUT = 0 | FLAGS_REGID = r0.x } + 00000000 SP_GS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 0xa88c: 00000000 + 14e2046b SP_GS_OBJ_START_LO: 0x14e2046b + 00004c8f SP_GS_OBJ_START_HI: 0x4c8f + 00000000 0xa88f: 00000000 + 00000000 0xa890: 00000000 + 00000000 0xa891: 00000000 + 00000000 0xa892: 00000000 + 00000080 SP_GS_TEX_COUNT: 128 + 00000100 SP_GS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_GS_INSTRLEN: 0 + e0c4d9c6 SP_VS_TEX_SAMP_LO: 0xe0c4d9c6 + 0000ed21 SP_VS_TEX_SAMP_HI: 0xed21 + 73a9bba1 SP_HS_TEX_SAMP_LO: 0x73a9bba1 + 00001a05 SP_HS_TEX_SAMP_HI: 0x1a05 + b21263a4 SP_DS_TEX_SAMP_LO: 0xb21263a4 + 0001a6b5 SP_DS_TEX_SAMP_HI: 0x1a6b5 + ee7b37d3 SP_GS_TEX_SAMP_LO: 0xee7b37d3 + 000047fc SP_GS_TEX_SAMP_HI: 0x47fc + 5eb05388 SP_VS_TEX_CONST_LO: 0x5eb05388 + 0001f31d SP_VS_TEX_CONST_HI: 0x1f31d + 90f84815 SP_HS_TEX_CONST_LO: 0x90f84815 + 00018461 SP_HS_TEX_CONST_HI: 0x18461 + 96f329d4 SP_DS_TEX_CONST_LO: 0x96f329d4 + 00015905 SP_DS_TEX_CONST_HI: 0x15905 + e6ce68a3 SP_GS_TEX_CONST_LO: 0xe6ce68a3 + 00007a12 SP_GS_TEX_CONST_HI: 0x7a12 + 00000000 0xa8c0: 00000000 + 00000000 0xa8c1: 00000000 + 00000000 0xa8c2: 00000000 + 00000000 0xa8c3: 00000000 + - context: 1 + 00000000 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } + 00000000 SP_VS_BRANCH_COND: 0 + 00000000 SP_VS_PRIMITIVE_CNTL: { OUT = 0 } + 00000000 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_UNKNOWN_A81B: 0 + 8e5d7d37 SP_VS_OBJ_START_LO: 0x8e5d7d37 + 0001fcd5 SP_VS_OBJ_START_HI: 0x1fcd5 + 00000000 0xa81e: 00000000 + 00000000 0xa81f: 00000000 + 00000000 0xa820: 00000000 + 00000000 0xa821: 00000000 + 00000080 SP_VS_TEX_COUNT: 128 + 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_VS_INSTRLEN: 0 + 00000000 SP_HS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } + 00000000 SP_HS_UNKNOWN_A831: 0 + 00000000 0xa832: 00000000 + 00000000 SP_HS_UNKNOWN_A833: 0 + 780a8ca5 SP_HS_OBJ_START_LO: 0x780a8ca5 + 0001aad2 SP_HS_OBJ_START_HI: 0x1aad2 + 00000000 0xa836: 00000000 + 00000000 0xa837: 00000000 + 00000000 0xa838: 00000000 + 00000000 0xa839: 00000000 + 00000080 SP_HS_TEX_COUNT: 128 + 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_HS_INSTRLEN: 0 + 00000000 SP_DS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } + 00000000 0xa841: 00000000 + 00000000 SP_DS_PRIMITIVE_CNTL: { OUT = 0 } + 00000000 SP_DS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_DS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_DS_UNKNOWN_A85B: 0 + 7abf500d SP_DS_OBJ_START_LO: 0x7abf500d + 00017e52 SP_DS_OBJ_START_HI: 0x17e52 + 00000000 0xa85e: 00000000 + 00000000 0xa85f: 00000000 + 00000000 0xa860: 00000000 + 00000000 0xa861: 00000000 + 00000080 SP_DS_TEX_COUNT: 128 + 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_DS_INSTRLEN: 0 + 00000000 SP_GS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } + 00000000 SP_GS_PRIM_SIZE: 0 + 00000000 SP_GS_BRANCH_COND: 0 + 00000000 SP_GS_PRIMITIVE_CNTL: { OUT = 0 | FLAGS_REGID = r0.x } + 00000000 SP_GS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x3].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x4].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x5].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x6].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x7].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x8].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0x9].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xa].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xb].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xc].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xd].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xe].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_OUT[0xf].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 } + 00000000 SP_GS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x1].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x2].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x3].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x4].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x5].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 SP_GS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + 00000000 0xa88c: 00000000 + 14e2046b SP_GS_OBJ_START_LO: 0x14e2046b + 00004c8f SP_GS_OBJ_START_HI: 0x4c8f + 00000000 0xa88f: 00000000 + 00000000 0xa890: 00000000 + 00000000 0xa891: 00000000 + 00000000 0xa892: 00000000 + 00000080 SP_GS_TEX_COUNT: 128 + 00000100 SP_GS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_GS_INSTRLEN: 0 + e0c4d9c6 SP_VS_TEX_SAMP_LO: 0xe0c4d9c6 + 0000ed21 SP_VS_TEX_SAMP_HI: 0xed21 + 73a9bba1 SP_HS_TEX_SAMP_LO: 0x73a9bba1 + 00001a05 SP_HS_TEX_SAMP_HI: 0x1a05 + b21263a4 SP_DS_TEX_SAMP_LO: 0xb21263a4 + 0001a6b5 SP_DS_TEX_SAMP_HI: 0x1a6b5 + ee7b37d3 SP_GS_TEX_SAMP_LO: 0xee7b37d3 + 000047fc SP_GS_TEX_SAMP_HI: 0x47fc + 5eb05388 SP_VS_TEX_CONST_LO: 0x5eb05388 + 0001f31d SP_VS_TEX_CONST_HI: 0x1f31d + 90f84815 SP_HS_TEX_CONST_LO: 0x90f84815 + 00018461 SP_HS_TEX_CONST_HI: 0x18461 + 96f329d4 SP_DS_TEX_CONST_LO: 0x96f329d4 + 00015905 SP_DS_TEX_CONST_HI: 0x15905 + e6ce68a3 SP_GS_TEX_CONST_LO: 0xe6ce68a3 + 00007a12 SP_GS_TEX_CONST_HI: 0x7a12 + 00000000 0xa8c0: 00000000 + 00000000 0xa8c1: 00000000 + 00000000 0xa8c2: 00000000 + 00000000 0xa8c3: 00000000 + - cluster-name: CLUSTER_SP_VS + - context: 0 + 00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED } + 00000000 HLSQ_SHARED_CONSTS: { 0 } + 00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR+0x1: 0 + - context: 1 + 00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED } + 00000000 HLSQ_SHARED_CONSTS: { 0 } + 00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR+0x1: 0 + - cluster-name: CLUSTER_SP_VS + - context: 0 + deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 } + - context: 1 + deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 } + - cluster-name: CLUSTER_SP_VS + - context: 0 + 00000000 SP_UNKNOWN_AB00: 0 + 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_FS_INSTRLEN: 0 + 2764a40a SP_BINDLESS_BASE[0].ADDR: 0x2764a40a + 0000cd30 SP_BINDLESS_BASE[0].ADDR+0x1: 0xcd30 + 93870830 SP_BINDLESS_BASE[0x1].ADDR: 0x93870830 + 00017dc4 SP_BINDLESS_BASE[0x1].ADDR+0x1: 0x17dc4 + d3064206 SP_BINDLESS_BASE[0x2].ADDR: 0xd3064206 + 00014b45 SP_BINDLESS_BASE[0x2].ADDR+0x1: 0x14b45 + bfafe9ba SP_BINDLESS_BASE[0x3].ADDR: 0xbfafe9ba + 0001ddc9 SP_BINDLESS_BASE[0x3].ADDR+0x1: 0x1ddc9 + efda4292 SP_BINDLESS_BASE[0x4].ADDR: 0xefda4292 + 0000bd3b SP_BINDLESS_BASE[0x4].ADDR+0x1: 0xbd3b + 0c0e0691 SP_IBO_LO: 0xc0e0691 + 00013c40 SP_IBO_HI: 0x13c40 + 00000040 SP_IBO_COUNT: 64 + - context: 1 + 00000000 SP_UNKNOWN_AB00: 0 + 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_FS_INSTRLEN: 0 + 2764a40a SP_BINDLESS_BASE[0].ADDR: 0x2764a40a + 0000cd30 SP_BINDLESS_BASE[0].ADDR+0x1: 0xcd30 + 93870830 SP_BINDLESS_BASE[0x1].ADDR: 0x93870830 + 00017dc4 SP_BINDLESS_BASE[0x1].ADDR+0x1: 0x17dc4 + d3064206 SP_BINDLESS_BASE[0x2].ADDR: 0xd3064206 + 00014b45 SP_BINDLESS_BASE[0x2].ADDR+0x1: 0x14b45 + bfafe9ba SP_BINDLESS_BASE[0x3].ADDR: 0xbfafe9ba + 0001ddc9 SP_BINDLESS_BASE[0x3].ADDR+0x1: 0x1ddc9 + efda4292 SP_BINDLESS_BASE[0x4].ADDR: 0xefda4292 + 0000bd3b SP_BINDLESS_BASE[0x4].ADDR+0x1: 0xbd3b + 0c0e0691 SP_IBO_LO: 0xc0e0691 + 00013c40 SP_IBO_HI: 0x13c40 + 00000040 SP_IBO_COUNT: 64 + - cluster-name: CLUSTER_SP_VS + - context: 0 + 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0 + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0 + 00000000 SP_TP_SAMPLE_CONFIG: { 0 } + 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } + 0000004c SP_TP_UNKNOWN_B309: 0x4c + deadbeef 0xb380: deadbeef + deadbeef 0xb381: deadbeef + deadbeef 0xb382: deadbeef + - context: 1 + 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0 + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0 + 00000000 SP_TP_SAMPLE_CONFIG: { 0 } + 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } + 0000004c SP_TP_UNKNOWN_B309: 0x4c + deadbeef 0xb380: deadbeef + deadbeef 0xb381: deadbeef + deadbeef 0xb382: deadbeef + - cluster-name: CLUSTER_SP_PS + - context: 0 + 00000001 HLSQ_UNKNOWN_B980: 0x1 + 00000007 HLSQ_CONTROL_1_REG: 0x7 + fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } + 000000fc HLSQ_CONTROL_5_REG: 0xfc + 00000101 HLSQ_CS_CNTL: { CONSTLEN = 4 | ENABLED } + 000003fd HLSQ_CS_NDRANGE_0: { KERNELDIM = 1 | LOCALSIZEX = 255 | LOCALSIZEY = 0 | LOCALSIZEZ = 0 } + 00000200 HLSQ_CS_NDRANGE_1: { GLOBALSIZE_X = 512 } + 00000000 HLSQ_CS_NDRANGE_2: { GLOBALOFF_X = 0 } + 00000001 HLSQ_CS_NDRANGE_3: { GLOBALSIZE_Y = 1 } + 00000000 HLSQ_CS_NDRANGE_4: { GLOBALOFF_Y = 0 } + 00000001 HLSQ_CS_NDRANGE_5: { GLOBALSIZE_Z = 1 } + 00000000 HLSQ_CS_NDRANGE_6: { GLOBALOFF_Z = 0 } + 00dcd8d4 HLSQ_CS_CNTL_0: { WGIDCONSTID = r53.x | UNK0 = r54.x | UNK1 = r55.x | LOCALIDREGID = r0.x } + 000000fc HLSQ_CS_UNKNOWN_B998: 0xfc + 00000002 HLSQ_CS_KERNEL_GROUP_X: 0x2 + 00000001 HLSQ_CS_KERNEL_GROUP_Y: 0x1 + 00000001 HLSQ_CS_KERNEL_GROUP_Z: 0x1 + 40304000 HLSQ_LOAD_STATE_FRAG_CMD: 0x40304000 + 8c415430 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR: 0x8c415430 + 00000000 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR+0x1: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR+0x1: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR+0x1: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR+0x1: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR+0x1: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR+0x1: 0 + - context: 1 + 00000001 HLSQ_UNKNOWN_B980: 0x1 + 00000007 HLSQ_CONTROL_1_REG: 0x7 + fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } + 000000fc HLSQ_CONTROL_5_REG: 0xfc + 00000101 HLSQ_CS_CNTL: { CONSTLEN = 4 | ENABLED } + 000003fd HLSQ_CS_NDRANGE_0: { KERNELDIM = 1 | LOCALSIZEX = 255 | LOCALSIZEY = 0 | LOCALSIZEZ = 0 } + 00000200 HLSQ_CS_NDRANGE_1: { GLOBALSIZE_X = 512 } + 00000000 HLSQ_CS_NDRANGE_2: { GLOBALOFF_X = 0 } + 00000001 HLSQ_CS_NDRANGE_3: { GLOBALSIZE_Y = 1 } + 00000000 HLSQ_CS_NDRANGE_4: { GLOBALOFF_Y = 0 } + 00000001 HLSQ_CS_NDRANGE_5: { GLOBALSIZE_Z = 1 } + 00000000 HLSQ_CS_NDRANGE_6: { GLOBALOFF_Z = 0 } + 00dcd8d4 HLSQ_CS_CNTL_0: { WGIDCONSTID = r53.x | UNK0 = r54.x | UNK1 = r55.x | LOCALIDREGID = r0.x } + 000000fc HLSQ_CS_UNKNOWN_B998: 0xfc + 00000002 HLSQ_CS_KERNEL_GROUP_X: 0x2 + 00000001 HLSQ_CS_KERNEL_GROUP_Y: 0x1 + 00000001 HLSQ_CS_KERNEL_GROUP_Z: 0x1 + 40304000 HLSQ_LOAD_STATE_FRAG_CMD: 0x40304000 + 8c415430 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR: 0x8c415430 + 00000000 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR+0x1: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR+0x1: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR+0x1: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR+0x1: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR+0x1: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR: 0 + 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR+0x1: 0 + - cluster-name: CLUSTER_SP_PS + - context: 0 + deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 } + - context: 1 + deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 } + - cluster-name: CLUSTER_SP_PS + - context: 0 + 05100000 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | PIXLODENABLE | 0x1000000 } + 00000000 SP_FS_BRANCH_COND: 0 + 00000000 SP_UNKNOWN_A982: 0 + 4bdb43d8 SP_FS_OBJ_START_LO: 0x4bdb43d8 + 0001af86 SP_FS_OBJ_START_HI: 0x1af86 + 00000000 0xa985: 00000000 + 00000000 0xa986: 00000000 + 00000000 0xa987: 00000000 + 00000000 0xa988: 00000000 + 00000100 SP_BLEND_CNTL: { UNK8 } + 00000000 SP_SRGB_CNTL: { 0 } + 00000000 SP_FS_RENDER_COMPONENTS: { RT0 = 0 | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x } + 00000000 SP_FS_OUTPUT_CNTL1: { MRT = 0 } + 00000000 SP_FS_OUTPUT[0].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x1].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x2].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x3].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x4].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x5].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x6].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x7].REG: { REGID = r0.x } + 00000000 SP_FS_MRT[0].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x1].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x2].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x3].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x4].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x5].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x6].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x7].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_PREFETCH_CNTL: { COUNT = 0 } + 03c00000 SP_FS_PREFETCH[0].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = 0 } + 03c00000 SP_FS_PREFETCH[0x1].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = 0 } + 03c00000 SP_FS_PREFETCH[0x2].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = 0 } + 03c00000 SP_FS_PREFETCH[0x3].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = 0 } + 00000000 SP_FS_BINDLESS_PREFETCH[0].CMD: { SAMP_ID = 0 | TEX_ID = 0 } + 00000000 SP_FS_BINDLESS_PREFETCH[0x1].CMD: { SAMP_ID = 0 | TEX_ID = 0 } + 00000000 SP_FS_BINDLESS_PREFETCH[0x2].CMD: { SAMP_ID = 0 | TEX_ID = 0 } + 00000000 SP_FS_BINDLESS_PREFETCH[0x3].CMD: { SAMP_ID = 0 | TEX_ID = 0 } + 00000080 SP_FS_TEX_COUNT: 128 + 0000f000 SP_UNKNOWN_A9A8: 0xf000 + 00421800 SP_CS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 48 | BRANCHSTACK = 8 | THREADSIZE = TWO_QUADS | VARYING } + 0000001f SP_CS_UNKNOWN_A9B1: 31 + 00000000 0xa9b2: 00000000 + 00000000 SP_CS_UNKNOWN_A9B3: 0 + 8c415420 SP_CS_OBJ_START_LO: 0x8c415420 + 00000000 SP_CS_OBJ_START_HI: 0 + 00000000 0xa9b6: 00000000 + 00000000 0xa9b7: 00000000 + 00000000 0xa9b8: 00000000 + 00000000 0xa9b9: 00000000 + 00000080 SP_CS_TEX_COUNT: 128 + 00200100 SP_CS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 16 | NIBO = 0 } + 00000004 SP_CS_INSTRLEN: 4 + 00000000 0xa9d0: 00000000 + 00000000 0xa9d1: 00000000 + 00000000 0xa9d2: 00000000 + 00000000 0xa9d3: 00000000 + efea5306 SP_FS_TEX_SAMP_LO: 0xefea5306 + 00005e1c SP_FS_TEX_SAMP_HI: 0x5e1c + bf8b2a24 SP_CS_TEX_SAMP_LO: 0xbf8b2a24 + 0001ef50 SP_CS_TEX_SAMP_HI: 0x1ef50 + 693f2108 SP_FS_TEX_CONST_LO: 0x693f2108 + 00001998 SP_FS_TEX_CONST_HI: 0x1998 + be19e77a SP_CS_TEX_CONST_LO: 0xbe19e77a + 0001b500 SP_CS_TEX_CONST_HI: 0x1b500 + 7dd2a41c SP_CS_BINDLESS_BASE[0].ADDR: 0x7dd2a41c + 00012191 SP_CS_BINDLESS_BASE[0].ADDR+0x1: 0x12191 + 7d568030 SP_CS_BINDLESS_BASE[0x1].ADDR: 0x7d568030 + 0000f408 SP_CS_BINDLESS_BASE[0x1].ADDR+0x1: 0xf408 + 6915b33d SP_CS_BINDLESS_BASE[0x2].ADDR: 0x6915b33d + 000076cd SP_CS_BINDLESS_BASE[0x2].ADDR+0x1: 0x76cd + 3cfd0197 SP_CS_BINDLESS_BASE[0x3].ADDR: 0x3cfd0197 + 0001f233 SP_CS_BINDLESS_BASE[0x3].ADDR+0x1: 0x1f233 + a6b745da SP_CS_BINDLESS_BASE[0x4].ADDR: 0xa6b745da + 00016204 SP_CS_BINDLESS_BASE[0x4].ADDR+0x1: 0x16204 + fdfdd365 SP_CS_IBO_LO: 0xfdfdd365 + 0001d693 SP_CS_IBO_HI: 0x1d693 + 00000040 SP_CS_IBO_COUNT: 64 + 00000000 0xaa30: 00000000 + 00000000 0xaa31: 00000000 + - context: 1 + 05100000 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | PIXLODENABLE | 0x1000000 } + 00000000 SP_FS_BRANCH_COND: 0 + 00000000 SP_UNKNOWN_A982: 0 + 4bdb43d8 SP_FS_OBJ_START_LO: 0x4bdb43d8 + 0001af86 SP_FS_OBJ_START_HI: 0x1af86 + 00000000 0xa985: 00000000 + 00000000 0xa986: 00000000 + 00000000 0xa987: 00000000 + 00000000 0xa988: 00000000 + 00000100 SP_BLEND_CNTL: { UNK8 } + 00000000 SP_SRGB_CNTL: { 0 } + 00000000 SP_FS_RENDER_COMPONENTS: { RT0 = 0 | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x } + 00000000 SP_FS_OUTPUT_CNTL1: { MRT = 0 } + 00000000 SP_FS_OUTPUT[0].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x1].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x2].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x3].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x4].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x5].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x6].REG: { REGID = r0.x } + 00000000 SP_FS_OUTPUT[0x7].REG: { REGID = r0.x } + 00000000 SP_FS_MRT[0].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x1].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x2].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x3].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x4].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x5].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x6].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_MRT[0x7].REG: { COLOR_FORMAT = 0 } + 00000000 SP_FS_PREFETCH_CNTL: { COUNT = 0 } + 03c00000 SP_FS_PREFETCH[0].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = 0 } + 03c00000 SP_FS_PREFETCH[0x1].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = 0 } + 03c00000 SP_FS_PREFETCH[0x2].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = 0 } + 03c00000 SP_FS_PREFETCH[0x3].CMD: { SRC = 0 | SAMP_ID = 0 | TEX_ID = 0 | DST = r0.x | WRMASK = 0xf | CMD = 0 } + 00000000 SP_FS_BINDLESS_PREFETCH[0].CMD: { SAMP_ID = 0 | TEX_ID = 0 } + 00000000 SP_FS_BINDLESS_PREFETCH[0x1].CMD: { SAMP_ID = 0 | TEX_ID = 0 } + 00000000 SP_FS_BINDLESS_PREFETCH[0x2].CMD: { SAMP_ID = 0 | TEX_ID = 0 } + 00000000 SP_FS_BINDLESS_PREFETCH[0x3].CMD: { SAMP_ID = 0 | TEX_ID = 0 } + 00000080 SP_FS_TEX_COUNT: 128 + 0000f000 SP_UNKNOWN_A9A8: 0xf000 + 00421800 SP_CS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 48 | BRANCHSTACK = 8 | THREADSIZE = TWO_QUADS | VARYING } + 0000001f SP_CS_UNKNOWN_A9B1: 31 + 00000000 0xa9b2: 00000000 + 00000000 SP_CS_UNKNOWN_A9B3: 0 + 8c415420 SP_CS_OBJ_START_LO: 0x8c415420 + 00000000 SP_CS_OBJ_START_HI: 0 + 00000000 0xa9b6: 00000000 + 00000000 0xa9b7: 00000000 + 00000000 0xa9b8: 00000000 + 00000000 0xa9b9: 00000000 + 00000080 SP_CS_TEX_COUNT: 128 + 00200100 SP_CS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 16 | NIBO = 0 } + 00000004 SP_CS_INSTRLEN: 4 + 00000000 0xa9d0: 00000000 + 00000000 0xa9d1: 00000000 + 00000000 0xa9d2: 00000000 + 00000000 0xa9d3: 00000000 + efea5306 SP_FS_TEX_SAMP_LO: 0xefea5306 + 00005e1c SP_FS_TEX_SAMP_HI: 0x5e1c + bf8b2a24 SP_CS_TEX_SAMP_LO: 0xbf8b2a24 + 0001ef50 SP_CS_TEX_SAMP_HI: 0x1ef50 + 693f2108 SP_FS_TEX_CONST_LO: 0x693f2108 + 00001998 SP_FS_TEX_CONST_HI: 0x1998 + be19e77a SP_CS_TEX_CONST_LO: 0xbe19e77a + 0001b500 SP_CS_TEX_CONST_HI: 0x1b500 + 7dd2a41c SP_CS_BINDLESS_BASE[0].ADDR: 0x7dd2a41c + 00012191 SP_CS_BINDLESS_BASE[0].ADDR+0x1: 0x12191 + 7d568030 SP_CS_BINDLESS_BASE[0x1].ADDR: 0x7d568030 + 0000f408 SP_CS_BINDLESS_BASE[0x1].ADDR+0x1: 0xf408 + 6915b33d SP_CS_BINDLESS_BASE[0x2].ADDR: 0x6915b33d + 000076cd SP_CS_BINDLESS_BASE[0x2].ADDR+0x1: 0x76cd + 3cfd0197 SP_CS_BINDLESS_BASE[0x3].ADDR: 0x3cfd0197 + 0001f233 SP_CS_BINDLESS_BASE[0x3].ADDR+0x1: 0x1f233 + a6b745da SP_CS_BINDLESS_BASE[0x4].ADDR: 0xa6b745da + 00016204 SP_CS_BINDLESS_BASE[0x4].ADDR+0x1: 0x16204 + fdfdd365 SP_CS_IBO_LO: 0xfdfdd365 + 0001d693 SP_CS_IBO_HI: 0x1d693 + 00000040 SP_CS_IBO_COUNT: 64 + 00000000 0xaa30: 00000000 + 00000000 0xaa31: 00000000 + - cluster-name: CLUSTER_SP_PS + - context: 0 + 00000000 SP_2D_DST_FORMAT: { COLOR_FORMAT = 0 | MASK = 0 } + - context: 1 + 00000000 SP_2D_DST_FORMAT: { COLOR_FORMAT = 0 | MASK = 0 } + - cluster-name: CLUSTER_SP_PS + - context: 0 + 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0 + 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0 + 00000000 SP_UNKNOWN_B182: 0 + 00000000 SP_UNKNOWN_B183: 0 + 00000000 0xb190: 00000000 + 00000000 0xb191: 00000000 + - context: 1 + 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0 + 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0 + 00000000 SP_UNKNOWN_B182: 0 + 00000000 SP_UNKNOWN_B183: 0 + 00000000 0xb190: 00000000 + 00000000 0xb191: 00000000 + - cluster-name: CLUSTER_SP_PS + - context: 0 + 00000000 SP_PS_2D_SRC_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE } + 00000000 SP_PS_2D_SRC_SIZE: { WIDTH = 0 | HEIGHT = 0 } + 00000000 SP_PS_2D_SRC_LO: 0 + 00000000 SP_PS_2D_SRC_HI: 0 + 00000000 SP_PS_2D_SRC_PITCH: { PITCH = 0 } + 00000000 0xb4c5: 00000000 + 00000000 0xb4c6: 00000000 + 00000000 0xb4c7: 00000000 + 00000000 0xb4c8: 00000000 + 00000000 0xb4c9: 00000000 + 00000000 SP_PS_2D_SRC_FLAGS_LO: 0 + 00000000 SP_PS_2D_SRC_FLAGS_HI: 0 + 00000000 SP_PS_2D_SRC_FLAGS_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 0xb4cd: 00000000 + 00000000 0xb4ce: 00000000 + 00000000 0xb4cf: 00000000 + 00000000 0xb4d0: 00000000 + 00000000 SP_WINDOW_OFFSET: { X = 0 | Y = 0 } + - context: 1 + 00000000 SP_PS_2D_SRC_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE } + 00000000 SP_PS_2D_SRC_SIZE: { WIDTH = 0 | HEIGHT = 0 } + 00000000 SP_PS_2D_SRC_LO: 0 + 00000000 SP_PS_2D_SRC_HI: 0 + 00000000 SP_PS_2D_SRC_PITCH: { PITCH = 0 } + 00000000 0xb4c5: 00000000 + 00000000 0xb4c6: 00000000 + 00000000 0xb4c7: 00000000 + 00000000 0xb4c8: 00000000 + 00000000 0xb4c9: 00000000 + 00000000 SP_PS_2D_SRC_FLAGS_LO: 0 + 00000000 SP_PS_2D_SRC_FLAGS_HI: 0 + 00000000 SP_PS_2D_SRC_FLAGS_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 0xb4cd: 00000000 + 00000000 0xb4ce: 00000000 + 00000000 0xb4cf: 00000000 + 00000000 0xb4d0: 00000000 + 00000000 SP_WINDOW_OFFSET: { X = 0 | Y = 0 } + - cluster-name: CLUSTER_SP_PS + - context: 0 + 00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED } + 00000000 HLSQ_SHARED_CONSTS: { 0 } + 00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR+0x1: 0 + - context: 1 + 00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED } + 00000000 HLSQ_SHARED_CONSTS: { 0 } + 00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR+0x1: 0 + 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0 + 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR+0x1: 0 + - cluster-name: CLUSTER_SP_PS + - context: 0 + 00000000 SP_UNKNOWN_AB00: 0 + 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_FS_INSTRLEN: 0 + cdb94116 SP_BINDLESS_BASE[0].ADDR: 0xcdb94116 + 000007b4 SP_BINDLESS_BASE[0].ADDR+0x1: 0x7b4 + 6e5e07c3 SP_BINDLESS_BASE[0x1].ADDR: 0x6e5e07c3 + 0001f54b SP_BINDLESS_BASE[0x1].ADDR+0x1: 0x1f54b + 5f979543 SP_BINDLESS_BASE[0x2].ADDR: 0x5f979543 + 0001b455 SP_BINDLESS_BASE[0x2].ADDR+0x1: 0x1b455 + a4d3a8cc SP_BINDLESS_BASE[0x3].ADDR: 0xa4d3a8cc + 00013f8c SP_BINDLESS_BASE[0x3].ADDR+0x1: 0x13f8c + 1d337e76 SP_BINDLESS_BASE[0x4].ADDR: 0x1d337e76 + 0001ff60 SP_BINDLESS_BASE[0x4].ADDR+0x1: 0x1ff60 + e0e8bc18 SP_IBO_LO: 0xe0e8bc18 + 00010202 SP_IBO_HI: 0x10202 + 00000040 SP_IBO_COUNT: 64 + - context: 1 + 00000000 SP_UNKNOWN_AB00: 0 + 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000000 SP_FS_INSTRLEN: 0 + cdb94116 SP_BINDLESS_BASE[0].ADDR: 0xcdb94116 + 000007b4 SP_BINDLESS_BASE[0].ADDR+0x1: 0x7b4 + 6e5e07c3 SP_BINDLESS_BASE[0x1].ADDR: 0x6e5e07c3 + 0001f54b SP_BINDLESS_BASE[0x1].ADDR+0x1: 0x1f54b + 5f979543 SP_BINDLESS_BASE[0x2].ADDR: 0x5f979543 + 0001b455 SP_BINDLESS_BASE[0x2].ADDR+0x1: 0x1b455 + a4d3a8cc SP_BINDLESS_BASE[0x3].ADDR: 0xa4d3a8cc + 00013f8c SP_BINDLESS_BASE[0x3].ADDR+0x1: 0x13f8c + 1d337e76 SP_BINDLESS_BASE[0x4].ADDR: 0x1d337e76 + 0001ff60 SP_BINDLESS_BASE[0x4].ADDR+0x1: 0x1ff60 + e0e8bc18 SP_IBO_LO: 0xe0e8bc18 + 00010202 SP_IBO_HI: 0x10202 + 00000040 SP_IBO_COUNT: 64 + - cluster-name: CLUSTER_SP_PS + - context: 0 + 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0 + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0 + 00000000 SP_TP_SAMPLE_CONFIG: { 0 } + 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } + 0000004c SP_TP_UNKNOWN_B309: 0x4c + deadbeef 0xb380: deadbeef + deadbeef 0xb381: deadbeef + deadbeef 0xb382: deadbeef + - context: 1 + 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0 + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0 + 00000000 SP_TP_SAMPLE_CONFIG: { 0 } + 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } + 0000004c SP_TP_UNKNOWN_B309: 0x4c + deadbeef 0xb380: deadbeef + deadbeef 0xb381: deadbeef + deadbeef 0xb382: deadbeef +debugbus: + - debugbus-block: A6XX_DBGBUS_CP + count: 512 + - debugbus-block: A6XX_DBGBUS_RBBM + count: 512 + - debugbus-block: A6XX_DBGBUS_HLSQ + count: 512 + - debugbus-block: A6XX_DBGBUS_UCHE + count: 512 + - debugbus-block: A6XX_DBGBUS_DPM + count: 512 + - debugbus-block: A6XX_DBGBUS_TESS + count: 512 + - debugbus-block: A6XX_DBGBUS_PC + count: 512 + - debugbus-block: A6XX_DBGBUS_VFDP + count: 512 + - debugbus-block: A6XX_DBGBUS_VPC + count: 512 + - debugbus-block: A6XX_DBGBUS_TSE + count: 512 + - debugbus-block: A6XX_DBGBUS_RAS + count: 512 + - debugbus-block: A6XX_DBGBUS_VSC + count: 512 + - debugbus-block: A6XX_DBGBUS_COM + count: 512 + - debugbus-block: A6XX_DBGBUS_LRZ + count: 512 + - debugbus-block: A6XX_DBGBUS_A2D + count: 512 + - debugbus-block: A6XX_DBGBUS_CCUFCHE + count: 512 + - debugbus-block: A6XX_DBGBUS_RBP + count: 512 + - debugbus-block: A6XX_DBGBUS_DCS + count: 512 + - debugbus-block: A6XX_DBGBUS_DBGC + count: 512 + - debugbus-block: A6XX_DBGBUS_GMU_GX + count: 512 + - debugbus-block: A6XX_DBGBUS_TPFCHE + count: 512 + - debugbus-block: A6XX_DBGBUS_GPC + count: 512 + - debugbus-block: A6XX_DBGBUS_LARC + count: 512 + - debugbus-block: A6XX_DBGBUS_HLSQ_SPTP + count: 512 + - debugbus-block: A6XX_DBGBUS_RB_0 + count: 512 + - debugbus-block: A6XX_DBGBUS_RB_1 + count: 512 + - debugbus-block: A6XX_DBGBUS_UCHE_WRAPPER + count: 512 + - debugbus-block: A6XX_DBGBUS_CCU_0 + count: 512 + - debugbus-block: A6XX_DBGBUS_CCU_1 + count: 512 + - debugbus-block: A6XX_DBGBUS_VFD_0 + count: 512 + - debugbus-block: A6XX_DBGBUS_VFD_1 + count: 512 + - debugbus-block: A6XX_DBGBUS_VFD_2 + count: 512 + - debugbus-block: A6XX_DBGBUS_VFD_3 + count: 512 + - debugbus-block: A6XX_DBGBUS_SP_0 + count: 512 + - debugbus-block: A6XX_DBGBUS_SP_1 + count: 512 + - debugbus-block: A6XX_DBGBUS_TPL1_0 + count: 512 + - debugbus-block: A6XX_DBGBUS_TPL1_1 + count: 512 + - debugbus-block: A6XX_DBGBUS_TPL1_2 + count: 512 + - debugbus-block: A6XX_DBGBUS_TPL1_3 + count: 512 + - debugbus-block: A6XX_DBGBUS_VBIF + count: 170 diff --git a/src/freedreno/.gitlab-ci/reference/es2gears-a320.log b/src/freedreno/.gitlab-ci/reference/es2gears-a320.log new file mode 100644 index 00000000000..c174cc74252 --- /dev/null +++ b/src/freedreno/.gitlab-ci/reference/es2gears-a320.log @@ -0,0 +1,15135 @@ +Reading src/freedreno/.gitlab-ci/traces/es2gears-a320.rd.gz... +gpu_id: 330 +cmd: es2gears/628: fence=276 +############################################################ +cmdstream: 488 dwords +t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) +11848658: 0000: c0003b00 00007fff +t0 write SP_VS_PVT_MEM_PARAM_REG (22d6) + SP_VS_PVT_MEM_PARAM_REG: { MEMSIZEPERITEM = 1 | HWSTACKOFFSET = 0 | HWSTACKSIZEPERTHREAD = 8 } + SP_VS_PVT_MEM_ADDR_REG: { BURSTLEN = 0 | SHADERSTARTADDRESS = 0x127f4000 } + SP_VS_PVT_MEM_SIZE_REG: 0 +11848660: 0000: 000222d6 08000001 127f4000 00000000 +t0 write SP_FS_PVT_MEM_PARAM_REG (22e4) + SP_FS_PVT_MEM_PARAM_REG: { MEMSIZEPERITEM = 1 | HWSTACKOFFSET = 0 | HWSTACKSIZEPERTHREAD = 8 } + SP_FS_PVT_MEM_ADDR_REG: { BURSTLEN = 0 | SHADERSTARTADDRESS = 0x127f6000 } + SP_FS_PVT_MEM_SIZE_REG: 0 +11848670: 0000: 000222e4 08000001 127f6000 00000000 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11848680: 0000: 000021ea 0000000b +t0 write GRAS_SC_CONTROL (2072) + GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0 } +11848688: 0000: 00002072 00000000 +t0 write RB_MSAA_CONTROL (20c2) + RB_MSAA_CONTROL: { DISABLE | SAMPLES = MSAA_ONE | SAMPLE_MASK = 0xffff } + RB_ALPHA_REF: { UINT = 0 | FLOAT = 0.000000 } +11848690: 0000: 000120c2 ffff0400 00000000 +t0 write GRAS_CL_GB_CLIP_ADJ (2044) + GRAS_CL_GB_CLIP_ADJ: { HORZ = 0 | VERT = 0 } +1184869c: 0000: 00002044 00000000 +t0 write GRAS_TSE_DEBUG_ECO (0c81) + GRAS_TSE_DEBUG_ECO: 0x1 +118486a4: 0000: 00000c81 00000001 +t0 write TPL1_TP_VS_TEX_OFFSET (2340) + TPL1_TP_VS_TEX_OFFSET: { SAMPLEROFFSET = 0 | MEMOBJOFFSET = 0 | BASETABLEPTR = 0 } +118486ac: 0000: 00002340 00000000 +t0 write TPL1_TP_FS_TEX_OFFSET (2342) + TPL1_TP_FS_TEX_OFFSET: { SAMPLEROFFSET = 16 | MEMOBJOFFSET = 16 | BASETABLEPTR = 224 } +118486b4: 0000: 00002342 00e01010 +t0 write VPC_VARY_CYLWRAP_ENABLE_0 (228a) + VPC_VARY_CYLWRAP_ENABLE_0: 0 + VPC_VARY_CYLWRAP_ENABLE_1: 0 +118486bc: 0000: 0001228a 00000000 00000000 +t0 write UNKNOWN_0E43 (0e43) + UNKNOWN_0E43: 0x1 +118486c8: 0000: 00000e43 00000001 +t0 write UNKNOWN_0F03 (0f03) + UNKNOWN_0F03: 0x1 +118486d0: 0000: 00000f03 00000001 +t0 write UNKNOWN_0EE0 (0ee0) + UNKNOWN_0EE0: 0x3 +118486d8: 0000: 00000ee0 00000003 +t0 write UNKNOWN_0C3D (0c3d) + UNKNOWN_0C3D: 0x1 +118486e0: 0000: 00000c3d 00000001 +t0 write HLSQ_PERFCOUNTER0_SELECT (0e00) + HLSQ_PERFCOUNTER0_SELECT: HLSQ_PERF_SP_VS_CONSTANT +118486e8: 0000: 00000e00 00000000 +t0 write HLSQ_CONST_VSPRESV_RANGE_REG (2206) + HLSQ_CONST_VSPRESV_RANGE_REG: { STARTENTRY = 0 | ENDENTRY = 0 } + HLSQ_CONST_FSPRESV_RANGE_REG: { STARTENTRY = 0 | ENDENTRY = 0 } +118486f0: 0000: 00012206 00000000 00000000 +t0 write UCHE_CACHE_MODE_CONTROL_REG (0e82) + UCHE_CACHE_MODE_CONTROL_REG: 0x1 +118486fc: 0000: 00000e82 00000001 +t0 write VSC_SIZE_ADDRESS (0c02) + VSC_SIZE_ADDRESS: 0x127f8000 +11848704: 0000: 00000c02 127f8000 +t0 write GRAS_CL_CLIP_CNTL (2040) + GRAS_CL_CLIP_CNTL: { NUM_USER_CLIP_PLANES = 0 } +1184870c: 0000: 00002040 00000000 +t0 write GRAS_SU_POINT_MINMAX (2068) + GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + GRAS_SU_POINT_SIZE: 0.500000 +11848714: 0000: 00012068 ffc00010 00000008 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11848720: 0000: 000021ed ffffffff +t0 write RB_WINDOW_OFFSET (210e) + RB_WINDOW_OFFSET: { X = 0 | Y = 0 } +11848728: 0000: 0000210e 00000000 +t0 write RB_BLEND_RED (20e4) + RB_BLEND_RED: { UINT = 0 | FLOAT = 0.000000 } + RB_BLEND_GREEN: { UINT = 0 | FLOAT = 0.000000 } + RB_BLEND_BLUE: { UINT = 0 | FLOAT = 0.000000 } + RB_BLEND_ALPHA: { UINT = 0xff | FLOAT = 1.000000 } +11848730: 0000: 000320e4 00000000 00000000 00000000 3c0000ff +t0 write GRAS_CL_USER_PLANE[0].X (0ca0) + GRAS_CL_USER_PLANE[0].X: 0 + GRAS_CL_USER_PLANE[0].Y: 0 + GRAS_CL_USER_PLANE[0].Z: 0 + GRAS_CL_USER_PLANE[0].W: 0 +11848744: 0000: 00030ca0 00000000 00000000 00000000 00000000 +t0 write GRAS_CL_USER_PLANE[0x1].X (0ca4) + GRAS_CL_USER_PLANE[0x1].X: 0 + GRAS_CL_USER_PLANE[0x1].Y: 0 + GRAS_CL_USER_PLANE[0x1].Z: 0 + GRAS_CL_USER_PLANE[0x1].W: 0 +11848758: 0000: 00030ca4 00000000 00000000 00000000 00000000 +t0 write GRAS_CL_USER_PLANE[0x2].X (0ca8) + GRAS_CL_USER_PLANE[0x2].X: 0 + GRAS_CL_USER_PLANE[0x2].Y: 0 + GRAS_CL_USER_PLANE[0x2].Z: 0 + GRAS_CL_USER_PLANE[0x2].W: 0 +1184876c: 0000: 00030ca8 00000000 00000000 00000000 00000000 +t0 write GRAS_CL_USER_PLANE[0x3].X (0cac) + GRAS_CL_USER_PLANE[0x3].X: 0 + GRAS_CL_USER_PLANE[0x3].Y: 0 + GRAS_CL_USER_PLANE[0x3].Z: 0 + GRAS_CL_USER_PLANE[0x3].W: 0 +11848780: 0000: 00030cac 00000000 00000000 00000000 00000000 +t0 write GRAS_CL_USER_PLANE[0x4].X (0cb0) + GRAS_CL_USER_PLANE[0x4].X: 0 + GRAS_CL_USER_PLANE[0x4].Y: 0 + GRAS_CL_USER_PLANE[0x4].Z: 0 + GRAS_CL_USER_PLANE[0x4].W: 0 +11848794: 0000: 00030cb0 00000000 00000000 00000000 00000000 +t0 write GRAS_CL_USER_PLANE[0x5].X (0cb4) + GRAS_CL_USER_PLANE[0x5].X: 0 + GRAS_CL_USER_PLANE[0x5].Y: 0 + GRAS_CL_USER_PLANE[0x5].Z: 0 + GRAS_CL_USER_PLANE[0x5].W: 0 +118487a8: 0000: 00030cb4 00000000 00000000 00000000 00000000 +t3 opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = CACHE_FLUSH } + event CACHE_FLUSH +118487bc: 0000: c0004600 00000006 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_POINTLIST_PSIZE | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 0 } + draw: 0 + prim_type: DI_PT_POINTLIST_PSIZE (1) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 0 +118487c4: 0000: c0022200 00000000 00004081 00000000 +t3 opcode: CP_NOP (10) (5 dwords) +118487d4: 0000: c0031000 00000000 00000000 00000000 00000000 +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118487e8: 0000: c0002600 00000000 +t0 write VSC_BIN_SIZE (0c01) + VSC_BIN_SIZE: { WIDTH = 160 | HEIGHT = 320 } +118487f0: 0000: 00000c01 00000145 +t0 write VSC_PIPE[0].CONFIG (0c06) + VSC_PIPE[0].CONFIG: { X = 0 | Y = 0 | W = 2 | H = 1 } + VSC_PIPE[0].DATA_ADDRESS: 0x127f9000 + VSC_PIPE[0].DATA_LENGTH: 0x3ffe0 +118487f8: 0000: 00020c06 01200000 127f9000 0003ffe0 +t0 write VSC_PIPE[0x1].CONFIG (0c09) + VSC_PIPE[0x1].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE[0x1].DATA_ADDRESS: 0 + VSC_PIPE[0x1].DATA_LENGTH: 0 +11848808: 0000: 00020c09 00000000 00000000 00000000 +t0 write VSC_PIPE[0x2].CONFIG (0c0c) + VSC_PIPE[0x2].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE[0x2].DATA_ADDRESS: 0 + VSC_PIPE[0x2].DATA_LENGTH: 0 +11848818: 0000: 00020c0c 00000000 00000000 00000000 +t0 write VSC_PIPE[0x3].CONFIG (0c0f) + VSC_PIPE[0x3].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE[0x3].DATA_ADDRESS: 0 + VSC_PIPE[0x3].DATA_LENGTH: 0 +11848828: 0000: 00020c0f 00000000 00000000 00000000 +t0 write VSC_PIPE[0x4].CONFIG (0c12) + VSC_PIPE[0x4].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE[0x4].DATA_ADDRESS: 0 + VSC_PIPE[0x4].DATA_LENGTH: 0 +11848838: 0000: 00020c12 00000000 00000000 00000000 +t0 write VSC_PIPE[0x5].CONFIG (0c15) + VSC_PIPE[0x5].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE[0x5].DATA_ADDRESS: 0 + VSC_PIPE[0x5].DATA_LENGTH: 0 +11848848: 0000: 00020c15 00000000 00000000 00000000 +t0 write VSC_PIPE[0x6].CONFIG (0c18) + VSC_PIPE[0x6].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE[0x6].DATA_ADDRESS: 0 + VSC_PIPE[0x6].DATA_LENGTH: 0 +11848858: 0000: 00020c18 00000000 00000000 00000000 +t0 write VSC_PIPE[0x7].CONFIG (0c1b) + VSC_PIPE[0x7].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE[0x7].DATA_ADDRESS: 0 + VSC_PIPE[0x7].DATA_LENGTH: 0 +11848868: 0000: 00020c1b 00000000 00000000 00000000 +t0 write RB_DEPTH_INFO (2102) + RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_16 | DEPTH_BASE = 0x40000 } + RB_DEPTH_PITCH: 320 +11848878: 0000: 00012102 00020000 00000028 +t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) + RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 } +11848884: 0000: 00000ce0 004b012c +t0 write RB_MODE_CONTROL (20c0) + RB_MODE_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE } +1184888c: 0000: 000020c0 00008000 +t3 opcode: (null) (4c) (4 dwords) +11848894: 0000: c0024c00 00000000 00000000 012b009f +t0 write RB_MRT[0].BUF_INFO (20c5) + RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 640 } + RB_MRT[0].BUF_BASE: { COLOR_BUF_BASE = 0 } +118488a4: 0000: 000120c5 00280488 00000000 +t0 write SP_FS_IMAGE_OUTPUT[0].REG (22f4) + SP_FS_IMAGE_OUTPUT[0].REG: { MRTFORMAT = RB_R8G8B8A8_UNORM } +118488b0: 0000: 000022f4 00000008 +t0 write RB_MRT[0x1].BUF_INFO (20c9) + RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x1].BUF_BASE: { COLOR_BUF_BASE = 0 } +118488b8: 0000: 000120c9 00000080 00000000 +t0 write SP_FS_IMAGE_OUTPUT[0x1].REG (22f5) + SP_FS_IMAGE_OUTPUT[0x1].REG: { MRTFORMAT = RB_R5G6B5_UNORM } +118488c4: 0000: 000022f5 00000000 +t0 write RB_MRT[0x2].BUF_INFO (20cd) + RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x2].BUF_BASE: { COLOR_BUF_BASE = 0 } +118488cc: 0000: 000120cd 00000080 00000000 +t0 write SP_FS_IMAGE_OUTPUT[0x2].REG (22f6) + SP_FS_IMAGE_OUTPUT[0x2].REG: { MRTFORMAT = RB_R5G6B5_UNORM } +118488d8: 0000: 000022f6 00000000 +t0 write RB_MRT[0x3].BUF_INFO (20d1) + RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x3].BUF_BASE: { COLOR_BUF_BASE = 0 } +118488e0: 0000: 000120d1 00000080 00000000 +t0 write SP_FS_IMAGE_OUTPUT[0x3].REG (22f7) + SP_FS_IMAGE_OUTPUT[0x3].REG: { MRTFORMAT = RB_R5G6B5_UNORM } +118488ec: 0000: 000022f7 00000000 +t3 opcode: CP_REG_RMW (21) (4 dwords) + { DST_REG = 0x20c1 | ROTATE = 0 } + { SRC0 = 4294955023 } + { SRC1 = 8272 } + rmw (RB_RENDER_CONTROL & 0xffffd00f) | 0x00002050) +118488f4: 0000: c0022100 000020c1 ffffd00f 00002050 +t0 write RB_WINDOW_OFFSET (210e) + RB_WINDOW_OFFSET: { X = 0 | Y = 0 } +11848904: 0000: 0000210e 00000000 +t0 write GRAS_SC_SCREEN_SCISSOR_TL (2074) + GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + GRAS_SC_SCREEN_SCISSOR_BR: { X = 159 | Y = 299 } +1184890c: 0000: 00012074 00000000 012b009f +t0 write CP_SCRATCH_REG6 (057e) + CP_SCRATCH_REG6: 12814 + :0,0,12814,0 +11848918: 0000: 0000057e 0000320e +t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) + ibaddr:11842370 + ibsize:000018ba +t0 write CP_SCRATCH_REG5 (057d) + CP_SCRATCH_REG5: 11971 + :0,11971,12814,0 +11842370: 0000: 0000057d 00002ec3 +t0 write GRAS_SC_WINDOW_SCISSOR_TL (2079) + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } + GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } +11842378: 0000: 00012079 00000000 012b012b +t0 write GRAS_CL_VPORT_XOFFSET (2048) + GRAS_CL_VPORT_XOFFSET: 149.500000 + GRAS_CL_VPORT_XSCALE: 150.000000 + GRAS_CL_VPORT_YOFFSET: 149.500000 + GRAS_CL_VPORT_YSCALE: -150.000000 + GRAS_CL_VPORT_ZOFFSET: 0.500000 + GRAS_CL_VPORT_ZSCALE: 0.500000 +11842384: 0000: 00052048 43158000 43160000 43158000 c3160000 3f000000 3f000000 +t0 write RB_BLEND_ALPHA (20e7) + RB_BLEND_ALPHA: { UINT = 0xff | FLOAT = 1.000000 } +118423a0: 0000: 000020e7 3c0000ff +t3 opcode: CP_REG_RMW (21) (4 dwords) + { DST_REG = 0x20c1 | ROTATE = 0 } + { SRC0 = 12272 } + { SRC1 = 0 } + rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00000000) +118423a8: 0000: c0022100 000020c1 00002ff0 00000000 +t0 write RB_DEPTH_CONTROL (2100) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS } +118423b8: 0000: 00002100 00000076 +t0 write GRAS_CL_VPORT_ZOFFSET (204c) + GRAS_CL_VPORT_ZOFFSET: 0.000000 + GRAS_CL_VPORT_ZSCALE: 1.000000 +118423c0: 0000: 0001204c 00000000 3f800000 +t0 write RB_STENCILREFMASK (2108) + RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } +118423cc: 0000: 00012108 00000000 00000000 +t0 write RB_STENCIL_CONTROL (2104) + RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } +118423d8: 0000: 00002104 00000000 +t0 write RB_MRT[0].CONTROL (20c4) + RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf } +118423e0: 0000: 000020c4 0f001c00 +t0 write RB_MRT[0].BLEND_CONTROL (20c7) + RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +118423e8: 0000: 000020c7 20010001 +t0 write RB_MRT[0x1].CONTROL (20c8) + RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf } +118423f0: 0000: 000020c8 0f001c00 +t0 write RB_MRT[0x1].BLEND_CONTROL (20cb) + RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +118423f8: 0000: 000020cb 20010001 +t0 write RB_MRT[0x2].CONTROL (20cc) + RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf } +11842400: 0000: 000020cc 0f001c00 +t0 write RB_MRT[0x2].BLEND_CONTROL (20cf) + RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +11842408: 0000: 000020cf 20010001 +t0 write RB_MRT[0x3].CONTROL (20d0) + RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf } +11842410: 0000: 000020d0 0f001c00 +t0 write RB_MRT[0x3].BLEND_CONTROL (20d3) + RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +11842418: 0000: 000020d3 20010001 +t0 write GRAS_SU_MODE_CONTROL (2070) + GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } +11842420: 0000: 00002070 00000000 +t0 write HLSQ_CONTROL_0_REG (2200) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x } + HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 } + HLSQ_CONTROL_3_REG: { IJPERSPCENTERREGID = r0.x | IJNONPERSPCENTERREGID = r0.x | IJPERSPCENTROIDREGID = r0.x | IJNONPERSPCENTROIDREGID = r0.x } + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 1 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 1 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 1 } +11842428: 0000: 00052200 20000210 00000100 7c000000 00000000 01000000 01080001 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 } +11842444: 0000: 000022c0 00500000 +t0 write SP_VS_LENGTH_REG (22df) + SP_VS_LENGTH_REG: { SHADERLENGTH = 1 } +1184244c: 0000: 000022df 00000001 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 1 } + SP_VS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 } + SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } +11842454: 0000: 000222c4 01200402 04000000 0000fc00 +t0 write SP_FS_LENGTH_REG (22ff) + SP_FS_LENGTH_REG: { SHADERLENGTH = 1 } +11842464: 0000: 000022ff 00000001 +t0 write SP_FS_CTRL_REG0 (22e0) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 0 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 1 } + SP_FS_CTRL_REG1: { CONSTLENGTH = 1 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 0 | HALFPRECVAROFFSET = 63 } +1184246c: 0000: 000122e0 01340012 3f000001 +t0 write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8) + SP_FS_FLAT_SHAD_MODE_REG_0: 0 + SP_FS_FLAT_SHAD_MODE_REG_1: 0 +11842478: 0000: 000122e8 00000000 00000000 +t0 write SP_FS_OUTPUT_REG (22ec) + SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x } +11842484: 0000: 000022ec 00000000 +t0 write SP_FS_MRT[0].REG (22f0) + SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION } + SP_FS_MRT[0x1].REG: { REGID = r0.x } + SP_FS_MRT[0x2].REG: { REGID = r0.x } + SP_FS_MRT[0x3].REG: { REGID = r0.x } +1184248c: 0000: 000322f0 00000100 00000000 00000000 00000000 +t0 write VPC_ATTR (2280) + VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | LMSIZE = 1 } + VPC_PACK: { NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } +118424a0: 0000: 00012280 10001000 00000000 +t0 write VPC_VARYING_INTERP[0].MODE (2282) + VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } +118424ac: 0000: 00032282 00000000 00000000 00000000 00000000 +t0 write VPC_VARYING_PS_REPL[0].MODE (2286) + VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } +118424c0: 0000: 00032286 00000000 00000000 00000000 00000000 +t0 write VFD_VS_THREADING_THRESHOLD (227e) + VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x } +118424d4: 0000: 0000227e 0000fc0f +t3 opcode: CP_LOAD_STATE (30) (3 dwords) + { DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e2000 } +118424dc: 0000: c0013000 00640000 117e2000 +t0 write VFD_PERFCOUNTER0_SELECT (0e44) + VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED +118424e8: 0000: 00000e44 00000000 +t3 opcode: CP_LOAD_STATE (30) (3 dwords) + { DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_FRAG_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e1000 } +118424f0: 0000: c0013000 00740000 117e1000 +t0 write VFD_PERFCOUNTER0_SELECT (0e44) + VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED +118424fc: 0000: 00000e44 00000000 +t0 write VFD_CONTROL_0 (2240) + VFD_CONTROL_0: { TOTALATTRTOVS = 4 | PACKETSIZE = 2 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 } + VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x } +11842504: 0000: 00012240 08480004 fcfc0001 +t0 write VFD_FETCH[0].INSTR_0 (2246) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 | INDEXCODE = 0 | STEPRATE = 1 } + VFD_FETCH[0].INSTR_1: 0x127e9000 +11842510: 0000: 00012246 0100060b 127e9000 +t0 write VFD_DECODE[0].INSTR (2266) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +1184251c: 0000: 00002266 2c00009f +t0 write UCHE_CACHE_INVALIDATE0_REG (0ea0) + UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 } + UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE } +11842524: 0000: 00010ea0 00000000 90000000 +t3 opcode: CP_LOAD_STATE (30) (7 dwords) + { DST_OFF = 0 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_FRAG_SHADER | NUM_UNIT = 2 } + { STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 } +1184253c: 0.000000 0.000000 0.000000 1.000000 +1184253c: 0000: 00000000 00000000 00000000 3f800000 +11842530: 0000: c0053000 00b00000 00000001 00000000 00000000 00000000 3f800000 +t0 write PC_PRIM_VTX_CNTL (21ec) + PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 0 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } +1184254c: 0000: 000021ec 02000240 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 0 + VFD_INDEX_MAX: 2 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 0 +11842554: 0000: 00032242 00000000 00000002 00000000 00000000 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842568: 0000: 000021ed ffffffff +t3 opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = PERFCOUNTER_STOP } + event PERFCOUNTER_STOP +11842570: 0000: c0004600 00000018 +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 11972 + :0,11971,12814,11972 +11842578: 0000: 0000057f 00002ec4 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 2 } + draw: 0 + prim_type: DI_PT_RECTLIST (8) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 2 + draw[0] register values +!+ 00002ec3 CP_SCRATCH_REG5: 11971 + :0,11971,12814,11972 +!+ 0000320e CP_SCRATCH_REG6: 12814 + :0,11971,12814,11972 +!+ 00002ec4 CP_SCRATCH_REG7: 11972 + :0,11971,12814,11972 +!+ 00000145 VSC_BIN_SIZE: { WIDTH = 160 | HEIGHT = 320 } +!+ 127f8000 VSC_SIZE_ADDRESS: 0x127f8000 +!+ 01200000 VSC_PIPE[0].CONFIG: { X = 0 | Y = 0 | W = 2 | H = 1 } +!+ 127f9000 VSC_PIPE[0].DATA_ADDRESS: 0x127f9000 +!+ 0003ffe0 VSC_PIPE[0].DATA_LENGTH: 0x3ffe0 + + 00000000 VSC_PIPE[0x1].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE[0x1].DATA_ADDRESS: 0 + + 00000000 VSC_PIPE[0x1].DATA_LENGTH: 0 + + 00000000 VSC_PIPE[0x2].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE[0x2].DATA_ADDRESS: 0 + + 00000000 VSC_PIPE[0x2].DATA_LENGTH: 0 + + 00000000 VSC_PIPE[0x3].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE[0x3].DATA_ADDRESS: 0 + + 00000000 VSC_PIPE[0x3].DATA_LENGTH: 0 + + 00000000 VSC_PIPE[0x4].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE[0x4].DATA_ADDRESS: 0 + + 00000000 VSC_PIPE[0x4].DATA_LENGTH: 0 + + 00000000 VSC_PIPE[0x5].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE[0x5].DATA_ADDRESS: 0 + + 00000000 VSC_PIPE[0x5].DATA_LENGTH: 0 + + 00000000 VSC_PIPE[0x6].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE[0x6].DATA_ADDRESS: 0 + + 00000000 VSC_PIPE[0x6].DATA_LENGTH: 0 + + 00000000 VSC_PIPE[0x7].CONFIG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE[0x7].DATA_ADDRESS: 0 + + 00000000 VSC_PIPE[0x7].DATA_LENGTH: 0 +!+ 00000001 UNKNOWN_0C3D: 0x1 +!+ 00000001 GRAS_TSE_DEBUG_ECO: 0x1 + + 00000000 GRAS_CL_USER_PLANE[0].X: 0 + + 00000000 GRAS_CL_USER_PLANE[0].Y: 0 + + 00000000 GRAS_CL_USER_PLANE[0].Z: 0 + + 00000000 GRAS_CL_USER_PLANE[0].W: 0 + + 00000000 GRAS_CL_USER_PLANE[0x1].X: 0 + + 00000000 GRAS_CL_USER_PLANE[0x1].Y: 0 + + 00000000 GRAS_CL_USER_PLANE[0x1].Z: 0 + + 00000000 GRAS_CL_USER_PLANE[0x1].W: 0 + + 00000000 GRAS_CL_USER_PLANE[0x2].X: 0 + + 00000000 GRAS_CL_USER_PLANE[0x2].Y: 0 + + 00000000 GRAS_CL_USER_PLANE[0x2].Z: 0 + + 00000000 GRAS_CL_USER_PLANE[0x2].W: 0 + + 00000000 GRAS_CL_USER_PLANE[0x3].X: 0 + + 00000000 GRAS_CL_USER_PLANE[0x3].Y: 0 + + 00000000 GRAS_CL_USER_PLANE[0x3].Z: 0 + + 00000000 GRAS_CL_USER_PLANE[0x3].W: 0 + + 00000000 GRAS_CL_USER_PLANE[0x4].X: 0 + + 00000000 GRAS_CL_USER_PLANE[0x4].Y: 0 + + 00000000 GRAS_CL_USER_PLANE[0x4].Z: 0 + + 00000000 GRAS_CL_USER_PLANE[0x4].W: 0 + + 00000000 GRAS_CL_USER_PLANE[0x5].X: 0 + + 00000000 GRAS_CL_USER_PLANE[0x5].Y: 0 + + 00000000 GRAS_CL_USER_PLANE[0x5].Z: 0 + + 00000000 GRAS_CL_USER_PLANE[0x5].W: 0 +!+ 004b012c RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 } + + 00000000 HLSQ_PERFCOUNTER0_SELECT: HLSQ_PERF_SP_VS_CONSTANT +!+ 00000001 UNKNOWN_0E43: 0x1 + + 00000000 VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED +!+ 00000001 UCHE_CACHE_MODE_CONTROL_REG: 0x1 + + 00000000 UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 } +!+ 90000000 UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE } +!+ 00000003 UNKNOWN_0EE0: 0x3 +!+ 00000001 UNKNOWN_0F03: 0x1 + + 00000000 GRAS_CL_CLIP_CNTL: { NUM_USER_CLIP_PLANES = 0 } + + 00000000 GRAS_CL_GB_CLIP_ADJ: { HORZ = 0 | VERT = 0 } +!+ 43158000 GRAS_CL_VPORT_XOFFSET: 149.500000 +!+ 43160000 GRAS_CL_VPORT_XSCALE: 150.000000 +!+ 43158000 GRAS_CL_VPORT_YOFFSET: 149.500000 +!+ c3160000 GRAS_CL_VPORT_YSCALE: -150.000000 + + 00000000 GRAS_CL_VPORT_ZOFFSET: 0.000000 +!+ 3f800000 GRAS_CL_VPORT_ZSCALE: 1.000000 +!+ ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } +!+ 00000008 GRAS_SU_POINT_SIZE: 0.500000 + + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } + + 00000000 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0 } + + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 012b009f GRAS_SC_SCREEN_SCISSOR_BR: { X = 159 | Y = 299 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } +!+ 00008000 RB_MODE_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE } +!+ 00002050 RB_RENDER_CONTROL: { BIN_WIDTH = 160 | ENABLE_GMEM | COORD_MASK = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } +!+ ffff0400 RB_MSAA_CONTROL: { DISABLE | SAMPLES = MSAA_ONE | SAMPLE_MASK = 0xffff } + + 00000000 RB_ALPHA_REF: { UINT = 0 | FLOAT = 0.000000 } +!+ 0f001c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf } +!+ 00280488 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 640 } + + 00000000 RB_MRT[0].BUF_BASE: { COLOR_BUF_BASE = 0 } +!+ 20010001 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +!+ 0f001c00 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf } +!+ 00000080 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x1].BUF_BASE: { COLOR_BUF_BASE = 0 } +!+ 20010001 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +!+ 0f001c00 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf } +!+ 00000080 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x2].BUF_BASE: { COLOR_BUF_BASE = 0 } +!+ 20010001 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +!+ 0f001c00 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf } +!+ 00000080 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x3].BUF_BASE: { COLOR_BUF_BASE = 0 } +!+ 20010001 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ONE | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ONE | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } + + 00000000 RB_BLEND_RED: { UINT = 0 | FLOAT = 0.000000 } + + 00000000 RB_BLEND_GREEN: { UINT = 0 | FLOAT = 0.000000 } + + 00000000 RB_BLEND_BLUE: { UINT = 0 | FLOAT = 0.000000 } +!+ 3c0000ff RB_BLEND_ALPHA: { UINT = 0xff | FLOAT = 1.000000 } +!+ 00000076 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS } +!+ 00020000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_16 | DEPTH_BASE = 0x40000 } +!+ 00000028 RB_DEPTH_PITCH: 320 + + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + + 00000000 RB_WINDOW_OFFSET: { X = 0 | Y = 0 } +!+ 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +!+ 02000240 PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 0 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } +!+ ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 20000210 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE } +!+ 00000100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x } +!+ 7c000000 HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 } + + 00000000 HLSQ_CONTROL_3_REG: { IJPERSPCENTERREGID = r0.x | IJNONPERSPCENTERREGID = r0.x | IJPERSPCENTROIDREGID = r0.x | IJNONPERSPCENTROIDREGID = r0.x } +!+ 01000000 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 1 } +!+ 01080001 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 1 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 1 } + + 00000000 HLSQ_CONST_VSPRESV_RANGE_REG: { STARTENTRY = 0 | ENDENTRY = 0 } + + 00000000 HLSQ_CONST_FSPRESV_RANGE_REG: { STARTENTRY = 0 | ENDENTRY = 0 } +!+ 08480004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | PACKETSIZE = 2 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 } +!+ fcfc0001 VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x } + + 00000000 VFD_INDEX_MIN: 0 +!+ 00000002 VFD_INDEX_MAX: 2 + + 00000000 VFD_INSTANCEID_OFFSET: 0 + + 00000000 VFD_INDEX_OFFSET: 0 +!+ 0100060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 | INDEXCODE = 0 | STEPRATE = 1 } +!+ 127e9000 VFD_FETCH[0].INSTR_1: 0x127e9000 +!+ 2c00009f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +!+ 0000fc0f VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x } +!+ 10001000 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | LMSIZE = 1 } + + 00000000 VPC_PACK: { NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } + + 00000000 VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARY_CYLWRAP_ENABLE_0: 0 + + 00000000 VPC_VARY_CYLWRAP_ENABLE_1: 0 +!+ 00500000 SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 } +!+ 01200402 SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 1 } +!+ 04000000 SP_VS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 } +!+ 0000fc00 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } +!+ 08000001 SP_VS_PVT_MEM_PARAM_REG: { MEMSIZEPERITEM = 1 | HWSTACKOFFSET = 0 | HWSTACKSIZEPERTHREAD = 8 } +!+ 127f4000 SP_VS_PVT_MEM_ADDR_REG: { BURSTLEN = 0 | SHADERSTARTADDRESS = 0x127f4000 } + + 00000000 SP_VS_PVT_MEM_SIZE_REG: 0 +!+ 00000001 SP_VS_LENGTH_REG: { SHADERLENGTH = 1 } +!+ 01340012 SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 0 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 1 } +!+ 3f000001 SP_FS_CTRL_REG1: { CONSTLENGTH = 1 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 0 | HALFPRECVAROFFSET = 63 } +!+ 08000001 SP_FS_PVT_MEM_PARAM_REG: { MEMSIZEPERITEM = 1 | HWSTACKOFFSET = 0 | HWSTACKSIZEPERTHREAD = 8 } +!+ 127f6000 SP_FS_PVT_MEM_ADDR_REG: { BURSTLEN = 0 | SHADERSTARTADDRESS = 0x127f6000 } + + 00000000 SP_FS_PVT_MEM_SIZE_REG: 0 + + 00000000 SP_FS_FLAT_SHAD_MODE_REG_0: 0 + + 00000000 SP_FS_FLAT_SHAD_MODE_REG_1: 0 + + 00000000 SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x } +!+ 00000100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION } + + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x } + + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x } + + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x } +!+ 00000008 SP_FS_IMAGE_OUTPUT[0].REG: { MRTFORMAT = RB_R8G8B8A8_UNORM } + + 00000000 SP_FS_IMAGE_OUTPUT[0x1].REG: { MRTFORMAT = RB_R5G6B5_UNORM } + + 00000000 SP_FS_IMAGE_OUTPUT[0x2].REG: { MRTFORMAT = RB_R5G6B5_UNORM } + + 00000000 SP_FS_IMAGE_OUTPUT[0x3].REG: { MRTFORMAT = RB_R5G6B5_UNORM } +!+ 00000001 SP_FS_LENGTH_REG: { SHADERLENGTH = 1 } + + 00000000 TPL1_TP_VS_TEX_OFFSET: { SAMPLEROFFSET = 0 | MEMOBJOFFSET = 0 | BASETABLEPTR = 0 } +!+ 00e01010 TPL1_TP_FS_TEX_OFFSET: { SAMPLEROFFSET = 16 | MEMOBJOFFSET = 16 | BASETABLEPTR = 224 } +11842580: 0000: c0022200 00000000 00004088 00000002 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 11973 + :0,11971,12814,11973 +11842590: 0000: 0000057f 00002ec5 +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842598: 0000: c0002600 00000000 +t0 write CP_SCRATCH_REG5 (057d) + CP_SCRATCH_REG5: 11974 + :0,11974,12814,11973 +118425a0: 0000: 0000057d 00002ec6 +t0 write RB_MSAA_CONTROL (20c2) + RB_MSAA_CONTROL: { DISABLE | SAMPLES = MSAA_ONE | SAMPLE_MASK = 0xffff } +118425a8: 0000: 000020c2 ffff0400 +t3 opcode: CP_REG_RMW (21) (4 dwords) + { DST_REG = 0x20c1 | ROTATE = 0 } + { SRC0 = 12272 } + { SRC1 = 0 } + rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00000000) +118425b0: 0000: c0022100 000020c1 00002ff0 00000000 +t0 write RB_ALPHA_REF (20c3) + RB_ALPHA_REF: { UINT = 0 | FLOAT = 0.000000 } +118425c0: 0000: 000020c3 00000000 +t0 write RB_DEPTH_CONTROL (2100) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } +118425c8: 0000: 00002100 80000016 +t0 write RB_STENCIL_CONTROL (2104) + RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } +118425d0: 0000: 00002104 00000000 +t0 write RB_STENCILREFMASK (2108) + RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } +118425d8: 0000: 00012108 00000000 00000000 +t0 write GRAS_SU_MODE_CONTROL (2070) + GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 } +118425e4: 0000: 00002070 00000012 +t0 write GRAS_SU_POINT_MINMAX (2068) + GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + GRAS_SU_POINT_SIZE: 0.500000 +118425ec: 0000: 00012068 ffc00010 00000008 +t0 write GRAS_SU_POLY_OFFSET_SCALE (206c) + GRAS_SU_POLY_OFFSET_SCALE: { VAL = 0.000000 } + GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 +118425f8: 0000: 0001206c 00000000 00000000 +t0 write GRAS_CL_CLIP_CNTL (2040) + GRAS_CL_CLIP_CNTL: { IJ_PERSP_CENTER | NUM_USER_CLIP_PLANES = 0 } +11842604: 0000: 00002040 00001000 +t0 write PC_PRIM_VTX_CNTL (21ec) + PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 2 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } +1184260c: 0000: 000021ec 02000242 +t0 write GRAS_CL_VPORT_XOFFSET (2048) + GRAS_CL_VPORT_XOFFSET: 149.500000 + GRAS_CL_VPORT_XSCALE: 150.000000 + GRAS_CL_VPORT_YOFFSET: 149.500000 + GRAS_CL_VPORT_YSCALE: -150.000000 + GRAS_CL_VPORT_ZOFFSET: 0.500000 + GRAS_CL_VPORT_ZSCALE: 0.500000 +11842614: 0000: 00052048 43158000 43160000 43158000 c3160000 3f000000 3f000000 +t0 write HLSQ_CONTROL_0_REG (2200) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x } + HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 } + HLSQ_CONTROL_3_REG: { IJPERSPCENTERREGID = r0.x | IJNONPERSPCENTERREGID = r0.x | IJPERSPCENTROIDREGID = r0.x | IJNONPERSPCENTROIDREGID = r0.x } + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 11 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 36 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 4 } +11842630: 0000: 00052200 20000210 00000100 7c000000 00000000 2400000b 04080000 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 } +1184264c: 0000: 000022c0 00500000 +t0 write SP_VS_LENGTH_REG (22df) + SP_VS_LENGTH_REG: { SHADERLENGTH = 36 } +11842654: 0000: 000022df 00000024 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 8 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 36 } + SP_VS_CTRL_REG1: { CONSTLENGTH = 11 | CONSTFOOTPRINT = 10 | INITIALOUTSTANDING = 8 } + SP_VS_PARAM_REG: { POSREGID = r2.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +1184265c: 0000: 000222c4 24202002 0800280b 0010fc08 +t0 write SP_VS_OUT[0].REG (22c7) + SP_VS_OUT[0].REG: { A_REGID = r3.x | A_COMPMASK = 0xf | B_REGID = r2.x | B_COMPMASK = 0 } +1184266c: 0000: 000022c7 00081e0c +t0 write SP_VS_VPC_DST[0].REG (22d0) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } +11842674: 0000: 000022d0 00000008 +t0 write SP_FS_LENGTH_REG (22ff) + SP_FS_LENGTH_REG: { SHADERLENGTH = 4 } +1184267c: 0000: 000022ff 00000004 +t0 write SP_FS_CTRL_REG0 (22e0) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 4 } + SP_FS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 | HALFPRECVAROFFSET = 63 } +11842684: 0000: 000122e0 04340c02 3f400000 +t0 write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8) + SP_FS_FLAT_SHAD_MODE_REG_0: 0 + SP_FS_FLAT_SHAD_MODE_REG_1: 0 +11842690: 0000: 000122e8 00000000 00000000 +t0 write SP_FS_OUTPUT_REG (22ec) + SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x } +1184269c: 0000: 000022ec 00000000 +t0 write SP_FS_MRT[0].REG (22f0) + SP_FS_MRT[0].REG: { REGID = r2.x } + SP_FS_MRT[0x1].REG: { REGID = r0.x } + SP_FS_MRT[0x2].REG: { REGID = r0.x } + SP_FS_MRT[0x3].REG: { REGID = r0.x } +118426a4: 0000: 000322f0 00000008 00000000 00000000 00000000 +t0 write VPC_ATTR (2280) + VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | LMSIZE = 1 } + VPC_PACK: { NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +118426b8: 0000: 00012280 10001004 00040400 +t0 write VPC_VARYING_INTERP[0].MODE (2282) + VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } +118426c4: 0000: 00032282 00000000 00000000 00000000 00000000 +t0 write VPC_VARYING_PS_REPL[0].MODE (2286) + VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } +118426d8: 0000: 00032286 00000000 00000000 00000000 00000000 +t0 write VFD_VS_THREADING_THRESHOLD (227e) + VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x } +118426ec: 0000: 0000227e 0000fc0f +t3 opcode: CP_LOAD_STATE (30) (3 dwords) + { DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 36 } + { STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x127f3000 } +118426f4: 0000: c0013000 09240000 127f3000 +t0 write VFD_PERFCOUNTER0_SELECT (0e44) + VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED +11842700: 0000: 00000e44 00000000 +t3 opcode: CP_LOAD_STATE (30) (3 dwords) + { DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_FRAG_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x127f2000 } +11842708: 0000: c0013000 01340000 127f2000 +t0 write VFD_PERFCOUNTER0_SELECT (0e44) + VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED +11842714: 0000: 00000e44 00000000 +t0 write VFD_CONTROL_0 (2240) + VFD_CONTROL_0: { TOTALATTRTOVS = 8 | PACKETSIZE = 2 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 } + VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x } +1184271c: 0000: 00012240 10880008 fcfc0001 +t0 write UCHE_CACHE_INVALIDATE0_REG (0ea0) + UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 } + UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE } +11842728: 0000: 00010ea0 00000000 90000000 +t3 opcode: CP_LOAD_STATE (30) (43 dwords) + { DST_OFF = 0 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 20 } + { STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 } +11842740: 1.499184 0.349716 0.459207 0.458311 -0.049471 1.616941 -0.358029 -0.357330 +11842760: 0.866025 -0.513030 -0.815389 -0.813798 -4.500000 -4.143785 17.310228 19.274502 +11842780: 0.865554 0.201909 -0.458311 -6.101883 -0.028562 0.933541 0.357330 9.046569 +118427a0: 0.500000 -0.296198 0.813798 16.275953 0.000000 0.000000 0.000000 1.000000 +118427c0: 5.000000 5.000000 10.000000 1.000000 0.800000 0.100000 0.000000 1.000000 +11842740: 0000: 3fbfe542 3eb30e03 3eeb1d21 3eeaa7b0 bd4aa238 3fcef7ec beb74f84 beb6f3f3 +11842760: 0020: 3f5db3d7 bf0355f2 bf50bd50 bf50550b c08fffff c08499e3 418a7b59 419a322e +11842780: 0040: 3f5d94f7 3e4ec12e beeaa7b0 c0c342a0 bce9fb30 3f6efc91 3eb6f3f3 4110bebf +118427a0: 0060: 3f000000 be97a747 3f50550b 41823527 00000000 00000000 00000000 3f800000 +118427c0: 0080: 40a00000 40a00000 41200000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 +11842734: 0000: c0293000 05200000 00000001 3fbfe542 3eb30e03 3eeb1d21 3eeaa7b0 bd4aa238 +11842754: 0020: 3fcef7ec beb74f84 beb6f3f3 3f5db3d7 bf0355f2 bf50bd50 bf50550b c08fffff +11842774: 0040: c08499e3 418a7b59 419a322e 3f5d94f7 3e4ec12e beeaa7b0 c0c342a0 bce9fb30 +11842794: 0060: 3f6efc91 3eb6f3f3 4110bebf 3f000000 be97a747 3f50550b 41823527 00000000 +118427b4: 0080: 00000000 00000000 3f800000 40a00000 40a00000 41200000 3f800000 3f4ccccd +118427d4: 00a0: 3dcccccd 00000000 3f800000 +t0 write UCHE_CACHE_INVALIDATE0_REG (0ea0) + UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 } + UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE } +118427e0: 0000: 00010ea0 00000000 90000000 +t3 opcode: CP_LOAD_STATE (30) (7 dwords) + { DST_OFF = 20 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 2 } + { STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 } +118427f8: 0.000000 0.000000 0.000000 0.000000 +118427f8: 0000: 00000000 00000000 00000000 00000000 +118427ec: 0000: c0053000 00a00014 00000001 00000000 00000000 00000000 00000000 +t0 write RB_MRT[0].CONTROL (20c4) + RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf } +11842808: 0000: 000020c4 0f001c00 +t0 write RB_MRT[0].BLEND_CONTROL (20c7) + RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +11842810: 0000: 000020c7 20000000 +t0 write RB_MRT[0x1].CONTROL (20c8) + RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0 } +11842818: 0000: 000020c8 00001c00 +t0 write RB_MRT[0x1].BLEND_CONTROL (20cb) + RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +11842820: 0000: 000020cb 20000000 +t0 write RB_MRT[0x2].CONTROL (20cc) + RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0 } +11842828: 0000: 000020cc 00001c00 +t0 write RB_MRT[0x2].BLEND_CONTROL (20cf) + RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +11842830: 0000: 000020cf 20000000 +t0 write RB_MRT[0x3].CONTROL (20d0) + RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0 } +11842838: 0000: 000020d0 00001c00 +t0 write RB_MRT[0x3].BLEND_CONTROL (20d3) + RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +11842840: 0000: 000020d3 20000000 +t0 write VFD_FETCH[0].INSTR_0 (2246) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT | INDEXCODE = 0 | STEPRATE = 1 } + VFD_FETCH[0].INSTR_1: 0x127ea000 +11842848: 0000: 00012246 01020c0b 127ea000 +t0 write VFD_DECODE[0].INSTR (2266) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } +11842854: 0000: 00002266 6c00009f +t0 write VFD_FETCH[0x1].INSTR_0 (2248) + VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | INDEXCODE = 1 | STEPRATE = 1 } + VFD_FETCH[0x1].INSTR_1: 0x127ea00c +1184285c: 0000: 00012248 01040c0b 127ea00c +t0 write VFD_DECODE[0x1].INSTR (2267) + VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +11842868: 0000: 00002267 2c00409f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842870: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842878: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 0 + VFD_INDEX_MAX: 6 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 0 +11842880: 0000: 00032242 00000000 00000006 00000000 00000000 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842894: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 11975 + :0,11974,12814,11975 +1184289c: 0000: 0000057f 00002ec7 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 1 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[1] register values +!+ 00002ec6 CP_SCRATCH_REG5: 11974 + :0,11974,12814,11975 +!+ 00002ec7 CP_SCRATCH_REG7: 11975 + :0,11974,12814,11975 + + 00000000 VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED + + 00000000 UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 } + + 90000000 UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE } +!+ 00001000 GRAS_CL_CLIP_CNTL: { IJ_PERSP_CENTER | NUM_USER_CLIP_PLANES = 0 } + + 43158000 GRAS_CL_VPORT_XOFFSET: 149.500000 + + 43160000 GRAS_CL_VPORT_XSCALE: 150.000000 + + 43158000 GRAS_CL_VPORT_YOFFSET: 149.500000 + + c3160000 GRAS_CL_VPORT_YSCALE: -150.000000 +!+ 3f000000 GRAS_CL_VPORT_ZOFFSET: 0.500000 +!+ 3f000000 GRAS_CL_VPORT_ZSCALE: 0.500000 + + ffc00010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 4092.000000 } + + 00000008 GRAS_SU_POINT_SIZE: 0.500000 + + 00000000 GRAS_SU_POLY_OFFSET_SCALE: { VAL = 0.000000 } + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 +!+ 00000012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 } + + 00002050 RB_RENDER_CONTROL: { BIN_WIDTH = 160 | ENABLE_GMEM | COORD_MASK = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } + + ffff0400 RB_MSAA_CONTROL: { DISABLE | SAMPLES = MSAA_ONE | SAMPLE_MASK = 0xffff } + + 00000000 RB_ALPHA_REF: { UINT = 0 | FLOAT = 0.000000 } + + 0f001c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0xf } +!+ 20000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +!+ 00001c00 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0 } +!+ 20000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +!+ 00001c00 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0 } +!+ 20000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +!+ 00001c00 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0 } +!+ 20000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE } +!+ 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } + + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +!+ 02000242 PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 2 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 20000210 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE } + + 00000100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x } + + 7c000000 HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 } + + 00000000 HLSQ_CONTROL_3_REG: { IJPERSPCENTERREGID = r0.x | IJNONPERSPCENTERREGID = r0.x | IJPERSPCENTROIDREGID = r0.x | IJNONPERSPCENTROIDREGID = r0.x } +!+ 2400000b HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 11 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 36 } +!+ 04080000 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 4 } +!+ 10880008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | PACKETSIZE = 2 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 } + + fcfc0001 VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x } + + 00000000 VFD_INDEX_MIN: 0 +!+ 00000006 VFD_INDEX_MAX: 6 + + 00000000 VFD_INSTANCEID_OFFSET: 0 + + 00000000 VFD_INDEX_OFFSET: 0 +!+ 01020c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT | INDEXCODE = 0 | STEPRATE = 1 } +!+ 127ea000 VFD_FETCH[0].INSTR_1: 0x127ea000 +!+ 01040c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | INDEXCODE = 1 | STEPRATE = 1 } +!+ 127ea00c VFD_FETCH[0x1].INSTR_1: 0x127ea00c +!+ 6c00009f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } +!+ 2c00409f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } + + 0000fc0f VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x } +!+ 10001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | LMSIZE = 1 } +!+ 00040400 VPC_PACK: { NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + + 00000000 VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00500000 SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 } +!+ 24202002 SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 8 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 36 } +!+ 0800280b SP_VS_CTRL_REG1: { CONSTLENGTH = 11 | CONSTFOOTPRINT = 10 | INITIALOUTSTANDING = 8 } +!+ 0010fc08 SP_VS_PARAM_REG: { POSREGID = r2.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +!+ 00081e0c SP_VS_OUT[0].REG: { A_REGID = r3.x | A_COMPMASK = 0xf | B_REGID = r2.x | B_COMPMASK = 0 } +!+ 00000008 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } +!+ 00000024 SP_VS_LENGTH_REG: { SHADERLENGTH = 36 } +!+ 04340c02 SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 4 } +!+ 3f400000 SP_FS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 | HALFPRECVAROFFSET = 63 } + + 00000000 SP_FS_FLAT_SHAD_MODE_REG_0: 0 + + 00000000 SP_FS_FLAT_SHAD_MODE_REG_1: 0 + + 00000000 SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x } +!+ 00000008 SP_FS_MRT[0].REG: { REGID = r2.x } + + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x } + + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x } + + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x } +!+ 00000004 SP_FS_LENGTH_REG: { SHADERLENGTH = 4 } +118428a4: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 11976 + :0,11974,12814,11976 +118428b4: 0000: 0000057f 00002ec8 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 11977 + :0,11977,12814,11976 +118428bc: 0000: 0000057d 00002ec9 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118428c4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118428cc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 7 + VFD_INDEX_MAX: 10 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 7 +118428d4: 0000: 00032242 00000007 0000000a 00000000 00000007 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118428e8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 11978 + :0,11977,12814,11978 +118428f0: 0000: 0000057f 00002eca +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 2 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[2] register values +!+ 00002ec9 CP_SCRATCH_REG5: 11977 + :0,11977,12814,11978 +!+ 00002eca CP_SCRATCH_REG7: 11978 + :0,11977,12814,11978 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000007 VFD_INDEX_MIN: 7 +!+ 0000000a VFD_INDEX_MAX: 10 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000007 VFD_INDEX_OFFSET: 7 +118428f8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 11979 + :0,11977,12814,11979 +11842908: 0000: 0000057f 00002ecb +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 11980 + :0,11980,12814,11979 +11842910: 0000: 0000057d 00002ecc +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842918: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842920: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 11 + VFD_INDEX_MAX: 17 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 11 +11842928: 0000: 00032242 0000000b 00000011 00000000 0000000b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184293c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 11981 + :0,11980,12814,11981 +11842944: 0000: 0000057f 00002ecd +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 3 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[3] register values +!+ 00002ecc CP_SCRATCH_REG5: 11980 + :0,11980,12814,11981 +!+ 00002ecd CP_SCRATCH_REG7: 11981 + :0,11980,12814,11981 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000000b VFD_INDEX_MIN: 11 +!+ 00000011 VFD_INDEX_MAX: 17 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000000b VFD_INDEX_OFFSET: 11 +1184294c: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 11982 + :0,11980,12814,11982 +1184295c: 0000: 0000057f 00002ece +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 11983 + :0,11983,12814,11982 +11842964: 0000: 0000057d 00002ecf +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184296c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842974: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 18 + VFD_INDEX_MAX: 21 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 18 +1184297c: 0000: 00032242 00000012 00000015 00000000 00000012 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842990: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 11984 + :0,11983,12814,11984 +11842998: 0000: 0000057f 00002ed0 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 4 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[4] register values +!+ 00002ecf CP_SCRATCH_REG5: 11983 + :0,11983,12814,11984 +!+ 00002ed0 CP_SCRATCH_REG7: 11984 + :0,11983,12814,11984 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000012 VFD_INDEX_MIN: 18 +!+ 00000015 VFD_INDEX_MAX: 21 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000012 VFD_INDEX_OFFSET: 18 +118429a0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 11985 + :0,11983,12814,11985 +118429b0: 0000: 0000057f 00002ed1 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 11986 + :0,11986,12814,11985 +118429b8: 0000: 0000057d 00002ed2 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118429c0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118429c8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 22 + VFD_INDEX_MAX: 25 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 22 +118429d0: 0000: 00032242 00000016 00000019 00000000 00000016 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118429e4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 11987 + :0,11986,12814,11987 +118429ec: 0000: 0000057f 00002ed3 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 5 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[5] register values +!+ 00002ed2 CP_SCRATCH_REG5: 11986 + :0,11986,12814,11987 +!+ 00002ed3 CP_SCRATCH_REG7: 11987 + :0,11986,12814,11987 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000016 VFD_INDEX_MIN: 22 +!+ 00000019 VFD_INDEX_MAX: 25 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000016 VFD_INDEX_OFFSET: 22 +118429f4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 11988 + :0,11986,12814,11988 +11842a04: 0000: 0000057f 00002ed4 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 11989 + :0,11989,12814,11988 +11842a0c: 0000: 0000057d 00002ed5 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842a14: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842a1c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 26 + VFD_INDEX_MAX: 29 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 26 +11842a24: 0000: 00032242 0000001a 0000001d 00000000 0000001a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842a38: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 11990 + :0,11989,12814,11990 +11842a40: 0000: 0000057f 00002ed6 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 6 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[6] register values +!+ 00002ed5 CP_SCRATCH_REG5: 11989 + :0,11989,12814,11990 +!+ 00002ed6 CP_SCRATCH_REG7: 11990 + :0,11989,12814,11990 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000001a VFD_INDEX_MIN: 26 +!+ 0000001d VFD_INDEX_MAX: 29 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000001a VFD_INDEX_OFFSET: 26 +11842a48: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 11991 + :0,11989,12814,11991 +11842a58: 0000: 0000057f 00002ed7 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 11992 + :0,11992,12814,11991 +11842a60: 0000: 0000057d 00002ed8 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842a68: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842a70: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 30 + VFD_INDEX_MAX: 33 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 30 +11842a78: 0000: 00032242 0000001e 00000021 00000000 0000001e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842a8c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 11993 + :0,11992,12814,11993 +11842a94: 0000: 0000057f 00002ed9 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 7 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[7] register values +!+ 00002ed8 CP_SCRATCH_REG5: 11992 + :0,11992,12814,11993 +!+ 00002ed9 CP_SCRATCH_REG7: 11993 + :0,11992,12814,11993 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000001e VFD_INDEX_MIN: 30 +!+ 00000021 VFD_INDEX_MAX: 33 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000001e VFD_INDEX_OFFSET: 30 +11842a9c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 11994 + :0,11992,12814,11994 +11842aac: 0000: 0000057f 00002eda +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 11995 + :0,11995,12814,11994 +11842ab4: 0000: 0000057d 00002edb +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842abc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842ac4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 34 + VFD_INDEX_MAX: 40 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 34 +11842acc: 0000: 00032242 00000022 00000028 00000000 00000022 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842ae0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 11996 + :0,11995,12814,11996 +11842ae8: 0000: 0000057f 00002edc +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 8 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[8] register values +!+ 00002edb CP_SCRATCH_REG5: 11995 + :0,11995,12814,11996 +!+ 00002edc CP_SCRATCH_REG7: 11996 + :0,11995,12814,11996 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000022 VFD_INDEX_MIN: 34 +!+ 00000028 VFD_INDEX_MAX: 40 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000022 VFD_INDEX_OFFSET: 34 +11842af0: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 11997 + :0,11995,12814,11997 +11842b00: 0000: 0000057f 00002edd +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 11998 + :0,11998,12814,11997 +11842b08: 0000: 0000057d 00002ede +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842b10: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842b18: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 41 + VFD_INDEX_MAX: 44 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 41 +11842b20: 0000: 00032242 00000029 0000002c 00000000 00000029 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842b34: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 11999 + :0,11998,12814,11999 +11842b3c: 0000: 0000057f 00002edf +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 9 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[9] register values +!+ 00002ede CP_SCRATCH_REG5: 11998 + :0,11998,12814,11999 +!+ 00002edf CP_SCRATCH_REG7: 11999 + :0,11998,12814,11999 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000029 VFD_INDEX_MIN: 41 +!+ 0000002c VFD_INDEX_MAX: 44 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000029 VFD_INDEX_OFFSET: 41 +11842b44: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12000 + :0,11998,12814,12000 +11842b54: 0000: 0000057f 00002ee0 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12001 + :0,12001,12814,12000 +11842b5c: 0000: 0000057d 00002ee1 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842b64: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842b6c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 45 + VFD_INDEX_MAX: 51 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 45 +11842b74: 0000: 00032242 0000002d 00000033 00000000 0000002d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842b88: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12002 + :0,12001,12814,12002 +11842b90: 0000: 0000057f 00002ee2 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 10 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[10] register values +!+ 00002ee1 CP_SCRATCH_REG5: 12001 + :0,12001,12814,12002 +!+ 00002ee2 CP_SCRATCH_REG7: 12002 + :0,12001,12814,12002 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000002d VFD_INDEX_MIN: 45 +!+ 00000033 VFD_INDEX_MAX: 51 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000002d VFD_INDEX_OFFSET: 45 +11842b98: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12003 + :0,12001,12814,12003 +11842ba8: 0000: 0000057f 00002ee3 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12004 + :0,12004,12814,12003 +11842bb0: 0000: 0000057d 00002ee4 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842bb8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842bc0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 52 + VFD_INDEX_MAX: 55 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 52 +11842bc8: 0000: 00032242 00000034 00000037 00000000 00000034 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842bdc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12005 + :0,12004,12814,12005 +11842be4: 0000: 0000057f 00002ee5 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 11 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[11] register values +!+ 00002ee4 CP_SCRATCH_REG5: 12004 + :0,12004,12814,12005 +!+ 00002ee5 CP_SCRATCH_REG7: 12005 + :0,12004,12814,12005 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000034 VFD_INDEX_MIN: 52 +!+ 00000037 VFD_INDEX_MAX: 55 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000034 VFD_INDEX_OFFSET: 52 +11842bec: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12006 + :0,12004,12814,12006 +11842bfc: 0000: 0000057f 00002ee6 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12007 + :0,12007,12814,12006 +11842c04: 0000: 0000057d 00002ee7 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842c0c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842c14: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 56 + VFD_INDEX_MAX: 59 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 56 +11842c1c: 0000: 00032242 00000038 0000003b 00000000 00000038 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842c30: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12008 + :0,12007,12814,12008 +11842c38: 0000: 0000057f 00002ee8 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 12 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[12] register values +!+ 00002ee7 CP_SCRATCH_REG5: 12007 + :0,12007,12814,12008 +!+ 00002ee8 CP_SCRATCH_REG7: 12008 + :0,12007,12814,12008 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000038 VFD_INDEX_MIN: 56 +!+ 0000003b VFD_INDEX_MAX: 59 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000038 VFD_INDEX_OFFSET: 56 +11842c40: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12009 + :0,12007,12814,12009 +11842c50: 0000: 0000057f 00002ee9 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12010 + :0,12010,12814,12009 +11842c58: 0000: 0000057d 00002eea +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842c60: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842c68: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 60 + VFD_INDEX_MAX: 63 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 60 +11842c70: 0000: 00032242 0000003c 0000003f 00000000 0000003c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842c84: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12011 + :0,12010,12814,12011 +11842c8c: 0000: 0000057f 00002eeb +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 13 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[13] register values +!+ 00002eea CP_SCRATCH_REG5: 12010 + :0,12010,12814,12011 +!+ 00002eeb CP_SCRATCH_REG7: 12011 + :0,12010,12814,12011 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000003c VFD_INDEX_MIN: 60 +!+ 0000003f VFD_INDEX_MAX: 63 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000003c VFD_INDEX_OFFSET: 60 +11842c94: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12012 + :0,12010,12814,12012 +11842ca4: 0000: 0000057f 00002eec +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12013 + :0,12013,12814,12012 +11842cac: 0000: 0000057d 00002eed +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842cb4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842cbc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 64 + VFD_INDEX_MAX: 67 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 64 +11842cc4: 0000: 00032242 00000040 00000043 00000000 00000040 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842cd8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12014 + :0,12013,12814,12014 +11842ce0: 0000: 0000057f 00002eee +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 14 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[14] register values +!+ 00002eed CP_SCRATCH_REG5: 12013 + :0,12013,12814,12014 +!+ 00002eee CP_SCRATCH_REG7: 12014 + :0,12013,12814,12014 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000040 VFD_INDEX_MIN: 64 +!+ 00000043 VFD_INDEX_MAX: 67 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000040 VFD_INDEX_OFFSET: 64 +11842ce8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12015 + :0,12013,12814,12015 +11842cf8: 0000: 0000057f 00002eef +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12016 + :0,12016,12814,12015 +11842d00: 0000: 0000057d 00002ef0 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842d08: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842d10: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 68 + VFD_INDEX_MAX: 74 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 68 +11842d18: 0000: 00032242 00000044 0000004a 00000000 00000044 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842d2c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12017 + :0,12016,12814,12017 +11842d34: 0000: 0000057f 00002ef1 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 15 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[15] register values +!+ 00002ef0 CP_SCRATCH_REG5: 12016 + :0,12016,12814,12017 +!+ 00002ef1 CP_SCRATCH_REG7: 12017 + :0,12016,12814,12017 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000044 VFD_INDEX_MIN: 68 +!+ 0000004a VFD_INDEX_MAX: 74 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000044 VFD_INDEX_OFFSET: 68 +11842d3c: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12018 + :0,12016,12814,12018 +11842d4c: 0000: 0000057f 00002ef2 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12019 + :0,12019,12814,12018 +11842d54: 0000: 0000057d 00002ef3 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842d5c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842d64: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 75 + VFD_INDEX_MAX: 78 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 75 +11842d6c: 0000: 00032242 0000004b 0000004e 00000000 0000004b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842d80: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12020 + :0,12019,12814,12020 +11842d88: 0000: 0000057f 00002ef4 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 16 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[16] register values +!+ 00002ef3 CP_SCRATCH_REG5: 12019 + :0,12019,12814,12020 +!+ 00002ef4 CP_SCRATCH_REG7: 12020 + :0,12019,12814,12020 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000004b VFD_INDEX_MIN: 75 +!+ 0000004e VFD_INDEX_MAX: 78 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000004b VFD_INDEX_OFFSET: 75 +11842d90: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12021 + :0,12019,12814,12021 +11842da0: 0000: 0000057f 00002ef5 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12022 + :0,12022,12814,12021 +11842da8: 0000: 0000057d 00002ef6 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842db0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842db8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 79 + VFD_INDEX_MAX: 85 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 79 +11842dc0: 0000: 00032242 0000004f 00000055 00000000 0000004f +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842dd4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12023 + :0,12022,12814,12023 +11842ddc: 0000: 0000057f 00002ef7 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 17 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[17] register values +!+ 00002ef6 CP_SCRATCH_REG5: 12022 + :0,12022,12814,12023 +!+ 00002ef7 CP_SCRATCH_REG7: 12023 + :0,12022,12814,12023 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000004f VFD_INDEX_MIN: 79 +!+ 00000055 VFD_INDEX_MAX: 85 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000004f VFD_INDEX_OFFSET: 79 +11842de4: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12024 + :0,12022,12814,12024 +11842df4: 0000: 0000057f 00002ef8 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12025 + :0,12025,12814,12024 +11842dfc: 0000: 0000057d 00002ef9 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842e04: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842e0c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 86 + VFD_INDEX_MAX: 89 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 86 +11842e14: 0000: 00032242 00000056 00000059 00000000 00000056 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842e28: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12026 + :0,12025,12814,12026 +11842e30: 0000: 0000057f 00002efa +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 18 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[18] register values +!+ 00002ef9 CP_SCRATCH_REG5: 12025 + :0,12025,12814,12026 +!+ 00002efa CP_SCRATCH_REG7: 12026 + :0,12025,12814,12026 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000056 VFD_INDEX_MIN: 86 +!+ 00000059 VFD_INDEX_MAX: 89 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000056 VFD_INDEX_OFFSET: 86 +11842e38: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12027 + :0,12025,12814,12027 +11842e48: 0000: 0000057f 00002efb +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12028 + :0,12028,12814,12027 +11842e50: 0000: 0000057d 00002efc +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842e58: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842e60: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 90 + VFD_INDEX_MAX: 93 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 90 +11842e68: 0000: 00032242 0000005a 0000005d 00000000 0000005a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842e7c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12029 + :0,12028,12814,12029 +11842e84: 0000: 0000057f 00002efd +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 19 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[19] register values +!+ 00002efc CP_SCRATCH_REG5: 12028 + :0,12028,12814,12029 +!+ 00002efd CP_SCRATCH_REG7: 12029 + :0,12028,12814,12029 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000005a VFD_INDEX_MIN: 90 +!+ 0000005d VFD_INDEX_MAX: 93 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000005a VFD_INDEX_OFFSET: 90 +11842e8c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12030 + :0,12028,12814,12030 +11842e9c: 0000: 0000057f 00002efe +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12031 + :0,12031,12814,12030 +11842ea4: 0000: 0000057d 00002eff +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842eac: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842eb4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 94 + VFD_INDEX_MAX: 97 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 94 +11842ebc: 0000: 00032242 0000005e 00000061 00000000 0000005e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842ed0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12032 + :0,12031,12814,12032 +11842ed8: 0000: 0000057f 00002f00 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 20 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[20] register values +!+ 00002eff CP_SCRATCH_REG5: 12031 + :0,12031,12814,12032 +!+ 00002f00 CP_SCRATCH_REG7: 12032 + :0,12031,12814,12032 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000005e VFD_INDEX_MIN: 94 +!+ 00000061 VFD_INDEX_MAX: 97 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000005e VFD_INDEX_OFFSET: 94 +11842ee0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12033 + :0,12031,12814,12033 +11842ef0: 0000: 0000057f 00002f01 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12034 + :0,12034,12814,12033 +11842ef8: 0000: 0000057d 00002f02 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842f00: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842f08: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 98 + VFD_INDEX_MAX: 101 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 98 +11842f10: 0000: 00032242 00000062 00000065 00000000 00000062 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842f24: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12035 + :0,12034,12814,12035 +11842f2c: 0000: 0000057f 00002f03 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 21 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[21] register values +!+ 00002f02 CP_SCRATCH_REG5: 12034 + :0,12034,12814,12035 +!+ 00002f03 CP_SCRATCH_REG7: 12035 + :0,12034,12814,12035 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000062 VFD_INDEX_MIN: 98 +!+ 00000065 VFD_INDEX_MAX: 101 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000062 VFD_INDEX_OFFSET: 98 +11842f34: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12036 + :0,12034,12814,12036 +11842f44: 0000: 0000057f 00002f04 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12037 + :0,12037,12814,12036 +11842f4c: 0000: 0000057d 00002f05 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842f54: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842f5c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 102 + VFD_INDEX_MAX: 108 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 102 +11842f64: 0000: 00032242 00000066 0000006c 00000000 00000066 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842f78: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12038 + :0,12037,12814,12038 +11842f80: 0000: 0000057f 00002f06 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 22 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[22] register values +!+ 00002f05 CP_SCRATCH_REG5: 12037 + :0,12037,12814,12038 +!+ 00002f06 CP_SCRATCH_REG7: 12038 + :0,12037,12814,12038 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000066 VFD_INDEX_MIN: 102 +!+ 0000006c VFD_INDEX_MAX: 108 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000066 VFD_INDEX_OFFSET: 102 +11842f88: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12039 + :0,12037,12814,12039 +11842f98: 0000: 0000057f 00002f07 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12040 + :0,12040,12814,12039 +11842fa0: 0000: 0000057d 00002f08 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842fa8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11842fb0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 109 + VFD_INDEX_MAX: 112 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 109 +11842fb8: 0000: 00032242 0000006d 00000070 00000000 0000006d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11842fcc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12041 + :0,12040,12814,12041 +11842fd4: 0000: 0000057f 00002f09 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 23 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[23] register values +!+ 00002f08 CP_SCRATCH_REG5: 12040 + :0,12040,12814,12041 +!+ 00002f09 CP_SCRATCH_REG7: 12041 + :0,12040,12814,12041 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000006d VFD_INDEX_MIN: 109 +!+ 00000070 VFD_INDEX_MAX: 112 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000006d VFD_INDEX_OFFSET: 109 +11842fdc: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12042 + :0,12040,12814,12042 +11842fec: 0000: 0000057f 00002f0a +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12043 + :0,12043,12814,12042 +11842ff4: 0000: 0000057d 00002f0b +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11842ffc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843004: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 113 + VFD_INDEX_MAX: 119 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 113 +1184300c: 0000: 00032242 00000071 00000077 00000000 00000071 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843020: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12044 + :0,12043,12814,12044 +11843028: 0000: 0000057f 00002f0c +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 24 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[24] register values +!+ 00002f0b CP_SCRATCH_REG5: 12043 + :0,12043,12814,12044 +!+ 00002f0c CP_SCRATCH_REG7: 12044 + :0,12043,12814,12044 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000071 VFD_INDEX_MIN: 113 +!+ 00000077 VFD_INDEX_MAX: 119 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000071 VFD_INDEX_OFFSET: 113 +11843030: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12045 + :0,12043,12814,12045 +11843040: 0000: 0000057f 00002f0d +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12046 + :0,12046,12814,12045 +11843048: 0000: 0000057d 00002f0e +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843050: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843058: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 120 + VFD_INDEX_MAX: 123 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 120 +11843060: 0000: 00032242 00000078 0000007b 00000000 00000078 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843074: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12047 + :0,12046,12814,12047 +1184307c: 0000: 0000057f 00002f0f +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 25 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[25] register values +!+ 00002f0e CP_SCRATCH_REG5: 12046 + :0,12046,12814,12047 +!+ 00002f0f CP_SCRATCH_REG7: 12047 + :0,12046,12814,12047 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000078 VFD_INDEX_MIN: 120 +!+ 0000007b VFD_INDEX_MAX: 123 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000078 VFD_INDEX_OFFSET: 120 +11843084: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12048 + :0,12046,12814,12048 +11843094: 0000: 0000057f 00002f10 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12049 + :0,12049,12814,12048 +1184309c: 0000: 0000057d 00002f11 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118430a4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118430ac: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 124 + VFD_INDEX_MAX: 127 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 124 +118430b4: 0000: 00032242 0000007c 0000007f 00000000 0000007c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118430c8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12050 + :0,12049,12814,12050 +118430d0: 0000: 0000057f 00002f12 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 26 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[26] register values +!+ 00002f11 CP_SCRATCH_REG5: 12049 + :0,12049,12814,12050 +!+ 00002f12 CP_SCRATCH_REG7: 12050 + :0,12049,12814,12050 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000007c VFD_INDEX_MIN: 124 +!+ 0000007f VFD_INDEX_MAX: 127 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000007c VFD_INDEX_OFFSET: 124 +118430d8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12051 + :0,12049,12814,12051 +118430e8: 0000: 0000057f 00002f13 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12052 + :0,12052,12814,12051 +118430f0: 0000: 0000057d 00002f14 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118430f8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843100: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 128 + VFD_INDEX_MAX: 131 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 128 +11843108: 0000: 00032242 00000080 00000083 00000000 00000080 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184311c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12053 + :0,12052,12814,12053 +11843124: 0000: 0000057f 00002f15 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 27 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[27] register values +!+ 00002f14 CP_SCRATCH_REG5: 12052 + :0,12052,12814,12053 +!+ 00002f15 CP_SCRATCH_REG7: 12053 + :0,12052,12814,12053 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000080 VFD_INDEX_MIN: 128 +!+ 00000083 VFD_INDEX_MAX: 131 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000080 VFD_INDEX_OFFSET: 128 +1184312c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12054 + :0,12052,12814,12054 +1184313c: 0000: 0000057f 00002f16 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12055 + :0,12055,12814,12054 +11843144: 0000: 0000057d 00002f17 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184314c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843154: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 132 + VFD_INDEX_MAX: 135 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 132 +1184315c: 0000: 00032242 00000084 00000087 00000000 00000084 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843170: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12056 + :0,12055,12814,12056 +11843178: 0000: 0000057f 00002f18 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 28 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[28] register values +!+ 00002f17 CP_SCRATCH_REG5: 12055 + :0,12055,12814,12056 +!+ 00002f18 CP_SCRATCH_REG7: 12056 + :0,12055,12814,12056 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000084 VFD_INDEX_MIN: 132 +!+ 00000087 VFD_INDEX_MAX: 135 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000084 VFD_INDEX_OFFSET: 132 +11843180: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12057 + :0,12055,12814,12057 +11843190: 0000: 0000057f 00002f19 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12058 + :0,12058,12814,12057 +11843198: 0000: 0000057d 00002f1a +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118431a0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118431a8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 136 + VFD_INDEX_MAX: 142 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 136 +118431b0: 0000: 00032242 00000088 0000008e 00000000 00000088 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118431c4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12059 + :0,12058,12814,12059 +118431cc: 0000: 0000057f 00002f1b +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 29 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[29] register values +!+ 00002f1a CP_SCRATCH_REG5: 12058 + :0,12058,12814,12059 +!+ 00002f1b CP_SCRATCH_REG7: 12059 + :0,12058,12814,12059 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000088 VFD_INDEX_MIN: 136 +!+ 0000008e VFD_INDEX_MAX: 142 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000088 VFD_INDEX_OFFSET: 136 +118431d4: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12060 + :0,12058,12814,12060 +118431e4: 0000: 0000057f 00002f1c +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12061 + :0,12061,12814,12060 +118431ec: 0000: 0000057d 00002f1d +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118431f4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118431fc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 143 + VFD_INDEX_MAX: 146 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 143 +11843204: 0000: 00032242 0000008f 00000092 00000000 0000008f +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843218: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12062 + :0,12061,12814,12062 +11843220: 0000: 0000057f 00002f1e +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 30 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[30] register values +!+ 00002f1d CP_SCRATCH_REG5: 12061 + :0,12061,12814,12062 +!+ 00002f1e CP_SCRATCH_REG7: 12062 + :0,12061,12814,12062 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000008f VFD_INDEX_MIN: 143 +!+ 00000092 VFD_INDEX_MAX: 146 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000008f VFD_INDEX_OFFSET: 143 +11843228: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12063 + :0,12061,12814,12063 +11843238: 0000: 0000057f 00002f1f +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12064 + :0,12064,12814,12063 +11843240: 0000: 0000057d 00002f20 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843248: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843250: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 147 + VFD_INDEX_MAX: 153 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 147 +11843258: 0000: 00032242 00000093 00000099 00000000 00000093 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184326c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12065 + :0,12064,12814,12065 +11843274: 0000: 0000057f 00002f21 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 31 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[31] register values +!+ 00002f20 CP_SCRATCH_REG5: 12064 + :0,12064,12814,12065 +!+ 00002f21 CP_SCRATCH_REG7: 12065 + :0,12064,12814,12065 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000093 VFD_INDEX_MIN: 147 +!+ 00000099 VFD_INDEX_MAX: 153 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000093 VFD_INDEX_OFFSET: 147 +1184327c: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12066 + :0,12064,12814,12066 +1184328c: 0000: 0000057f 00002f22 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12067 + :0,12067,12814,12066 +11843294: 0000: 0000057d 00002f23 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184329c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118432a4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 154 + VFD_INDEX_MAX: 157 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 154 +118432ac: 0000: 00032242 0000009a 0000009d 00000000 0000009a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118432c0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12068 + :0,12067,12814,12068 +118432c8: 0000: 0000057f 00002f24 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 32 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[32] register values +!+ 00002f23 CP_SCRATCH_REG5: 12067 + :0,12067,12814,12068 +!+ 00002f24 CP_SCRATCH_REG7: 12068 + :0,12067,12814,12068 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000009a VFD_INDEX_MIN: 154 +!+ 0000009d VFD_INDEX_MAX: 157 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000009a VFD_INDEX_OFFSET: 154 +118432d0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12069 + :0,12067,12814,12069 +118432e0: 0000: 0000057f 00002f25 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12070 + :0,12070,12814,12069 +118432e8: 0000: 0000057d 00002f26 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118432f0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118432f8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 158 + VFD_INDEX_MAX: 161 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 158 +11843300: 0000: 00032242 0000009e 000000a1 00000000 0000009e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843314: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12071 + :0,12070,12814,12071 +1184331c: 0000: 0000057f 00002f27 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 33 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[33] register values +!+ 00002f26 CP_SCRATCH_REG5: 12070 + :0,12070,12814,12071 +!+ 00002f27 CP_SCRATCH_REG7: 12071 + :0,12070,12814,12071 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000009e VFD_INDEX_MIN: 158 +!+ 000000a1 VFD_INDEX_MAX: 161 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000009e VFD_INDEX_OFFSET: 158 +11843324: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12072 + :0,12070,12814,12072 +11843334: 0000: 0000057f 00002f28 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12073 + :0,12073,12814,12072 +1184333c: 0000: 0000057d 00002f29 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843344: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184334c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 162 + VFD_INDEX_MAX: 165 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 162 +11843354: 0000: 00032242 000000a2 000000a5 00000000 000000a2 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843368: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12074 + :0,12073,12814,12074 +11843370: 0000: 0000057f 00002f2a +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 34 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[34] register values +!+ 00002f29 CP_SCRATCH_REG5: 12073 + :0,12073,12814,12074 +!+ 00002f2a CP_SCRATCH_REG7: 12074 + :0,12073,12814,12074 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000a2 VFD_INDEX_MIN: 162 +!+ 000000a5 VFD_INDEX_MAX: 165 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000a2 VFD_INDEX_OFFSET: 162 +11843378: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12075 + :0,12073,12814,12075 +11843388: 0000: 0000057f 00002f2b +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12076 + :0,12076,12814,12075 +11843390: 0000: 0000057d 00002f2c +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843398: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118433a0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 166 + VFD_INDEX_MAX: 169 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 166 +118433a8: 0000: 00032242 000000a6 000000a9 00000000 000000a6 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118433bc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12077 + :0,12076,12814,12077 +118433c4: 0000: 0000057f 00002f2d +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 35 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[35] register values +!+ 00002f2c CP_SCRATCH_REG5: 12076 + :0,12076,12814,12077 +!+ 00002f2d CP_SCRATCH_REG7: 12077 + :0,12076,12814,12077 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000a6 VFD_INDEX_MIN: 166 +!+ 000000a9 VFD_INDEX_MAX: 169 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000a6 VFD_INDEX_OFFSET: 166 +118433cc: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12078 + :0,12076,12814,12078 +118433dc: 0000: 0000057f 00002f2e +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12079 + :0,12079,12814,12078 +118433e4: 0000: 0000057d 00002f2f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118433ec: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118433f4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 170 + VFD_INDEX_MAX: 176 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 170 +118433fc: 0000: 00032242 000000aa 000000b0 00000000 000000aa +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843410: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12080 + :0,12079,12814,12080 +11843418: 0000: 0000057f 00002f30 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 36 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[36] register values +!+ 00002f2f CP_SCRATCH_REG5: 12079 + :0,12079,12814,12080 +!+ 00002f30 CP_SCRATCH_REG7: 12080 + :0,12079,12814,12080 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000aa VFD_INDEX_MIN: 170 +!+ 000000b0 VFD_INDEX_MAX: 176 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000aa VFD_INDEX_OFFSET: 170 +11843420: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12081 + :0,12079,12814,12081 +11843430: 0000: 0000057f 00002f31 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12082 + :0,12082,12814,12081 +11843438: 0000: 0000057d 00002f32 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843440: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843448: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 177 + VFD_INDEX_MAX: 180 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 177 +11843450: 0000: 00032242 000000b1 000000b4 00000000 000000b1 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843464: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12083 + :0,12082,12814,12083 +1184346c: 0000: 0000057f 00002f33 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 37 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[37] register values +!+ 00002f32 CP_SCRATCH_REG5: 12082 + :0,12082,12814,12083 +!+ 00002f33 CP_SCRATCH_REG7: 12083 + :0,12082,12814,12083 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000b1 VFD_INDEX_MIN: 177 +!+ 000000b4 VFD_INDEX_MAX: 180 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000b1 VFD_INDEX_OFFSET: 177 +11843474: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12084 + :0,12082,12814,12084 +11843484: 0000: 0000057f 00002f34 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12085 + :0,12085,12814,12084 +1184348c: 0000: 0000057d 00002f35 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843494: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184349c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 181 + VFD_INDEX_MAX: 187 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 181 +118434a4: 0000: 00032242 000000b5 000000bb 00000000 000000b5 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118434b8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12086 + :0,12085,12814,12086 +118434c0: 0000: 0000057f 00002f36 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 38 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[38] register values +!+ 00002f35 CP_SCRATCH_REG5: 12085 + :0,12085,12814,12086 +!+ 00002f36 CP_SCRATCH_REG7: 12086 + :0,12085,12814,12086 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000b5 VFD_INDEX_MIN: 181 +!+ 000000bb VFD_INDEX_MAX: 187 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000b5 VFD_INDEX_OFFSET: 181 +118434c8: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12087 + :0,12085,12814,12087 +118434d8: 0000: 0000057f 00002f37 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12088 + :0,12088,12814,12087 +118434e0: 0000: 0000057d 00002f38 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118434e8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118434f0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 188 + VFD_INDEX_MAX: 191 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 188 +118434f8: 0000: 00032242 000000bc 000000bf 00000000 000000bc +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184350c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12089 + :0,12088,12814,12089 +11843514: 0000: 0000057f 00002f39 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 39 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[39] register values +!+ 00002f38 CP_SCRATCH_REG5: 12088 + :0,12088,12814,12089 +!+ 00002f39 CP_SCRATCH_REG7: 12089 + :0,12088,12814,12089 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000bc VFD_INDEX_MIN: 188 +!+ 000000bf VFD_INDEX_MAX: 191 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000bc VFD_INDEX_OFFSET: 188 +1184351c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12090 + :0,12088,12814,12090 +1184352c: 0000: 0000057f 00002f3a +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12091 + :0,12091,12814,12090 +11843534: 0000: 0000057d 00002f3b +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184353c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843544: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 192 + VFD_INDEX_MAX: 195 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 192 +1184354c: 0000: 00032242 000000c0 000000c3 00000000 000000c0 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843560: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12092 + :0,12091,12814,12092 +11843568: 0000: 0000057f 00002f3c +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 40 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[40] register values +!+ 00002f3b CP_SCRATCH_REG5: 12091 + :0,12091,12814,12092 +!+ 00002f3c CP_SCRATCH_REG7: 12092 + :0,12091,12814,12092 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000c0 VFD_INDEX_MIN: 192 +!+ 000000c3 VFD_INDEX_MAX: 195 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000c0 VFD_INDEX_OFFSET: 192 +11843570: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12093 + :0,12091,12814,12093 +11843580: 0000: 0000057f 00002f3d +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12094 + :0,12094,12814,12093 +11843588: 0000: 0000057d 00002f3e +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843590: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843598: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 196 + VFD_INDEX_MAX: 199 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 196 +118435a0: 0000: 00032242 000000c4 000000c7 00000000 000000c4 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118435b4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12095 + :0,12094,12814,12095 +118435bc: 0000: 0000057f 00002f3f +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 41 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[41] register values +!+ 00002f3e CP_SCRATCH_REG5: 12094 + :0,12094,12814,12095 +!+ 00002f3f CP_SCRATCH_REG7: 12095 + :0,12094,12814,12095 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000c4 VFD_INDEX_MIN: 196 +!+ 000000c7 VFD_INDEX_MAX: 199 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000c4 VFD_INDEX_OFFSET: 196 +118435c4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12096 + :0,12094,12814,12096 +118435d4: 0000: 0000057f 00002f40 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12097 + :0,12097,12814,12096 +118435dc: 0000: 0000057d 00002f41 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118435e4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118435ec: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 200 + VFD_INDEX_MAX: 203 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 200 +118435f4: 0000: 00032242 000000c8 000000cb 00000000 000000c8 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843608: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12098 + :0,12097,12814,12098 +11843610: 0000: 0000057f 00002f42 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 42 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[42] register values +!+ 00002f41 CP_SCRATCH_REG5: 12097 + :0,12097,12814,12098 +!+ 00002f42 CP_SCRATCH_REG7: 12098 + :0,12097,12814,12098 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000c8 VFD_INDEX_MIN: 200 +!+ 000000cb VFD_INDEX_MAX: 203 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000c8 VFD_INDEX_OFFSET: 200 +11843618: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12099 + :0,12097,12814,12099 +11843628: 0000: 0000057f 00002f43 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12100 + :0,12100,12814,12099 +11843630: 0000: 0000057d 00002f44 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843638: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843640: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 204 + VFD_INDEX_MAX: 210 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 204 +11843648: 0000: 00032242 000000cc 000000d2 00000000 000000cc +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184365c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12101 + :0,12100,12814,12101 +11843664: 0000: 0000057f 00002f45 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 43 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[43] register values +!+ 00002f44 CP_SCRATCH_REG5: 12100 + :0,12100,12814,12101 +!+ 00002f45 CP_SCRATCH_REG7: 12101 + :0,12100,12814,12101 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000cc VFD_INDEX_MIN: 204 +!+ 000000d2 VFD_INDEX_MAX: 210 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000cc VFD_INDEX_OFFSET: 204 +1184366c: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12102 + :0,12100,12814,12102 +1184367c: 0000: 0000057f 00002f46 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12103 + :0,12103,12814,12102 +11843684: 0000: 0000057d 00002f47 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184368c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843694: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 211 + VFD_INDEX_MAX: 214 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 211 +1184369c: 0000: 00032242 000000d3 000000d6 00000000 000000d3 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118436b0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12104 + :0,12103,12814,12104 +118436b8: 0000: 0000057f 00002f48 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 44 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[44] register values +!+ 00002f47 CP_SCRATCH_REG5: 12103 + :0,12103,12814,12104 +!+ 00002f48 CP_SCRATCH_REG7: 12104 + :0,12103,12814,12104 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000d3 VFD_INDEX_MIN: 211 +!+ 000000d6 VFD_INDEX_MAX: 214 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000d3 VFD_INDEX_OFFSET: 211 +118436c0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12105 + :0,12103,12814,12105 +118436d0: 0000: 0000057f 00002f49 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12106 + :0,12106,12814,12105 +118436d8: 0000: 0000057d 00002f4a +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118436e0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118436e8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 215 + VFD_INDEX_MAX: 221 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 215 +118436f0: 0000: 00032242 000000d7 000000dd 00000000 000000d7 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843704: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12107 + :0,12106,12814,12107 +1184370c: 0000: 0000057f 00002f4b +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 45 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[45] register values +!+ 00002f4a CP_SCRATCH_REG5: 12106 + :0,12106,12814,12107 +!+ 00002f4b CP_SCRATCH_REG7: 12107 + :0,12106,12814,12107 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000d7 VFD_INDEX_MIN: 215 +!+ 000000dd VFD_INDEX_MAX: 221 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000d7 VFD_INDEX_OFFSET: 215 +11843714: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12108 + :0,12106,12814,12108 +11843724: 0000: 0000057f 00002f4c +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12109 + :0,12109,12814,12108 +1184372c: 0000: 0000057d 00002f4d +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843734: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184373c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 222 + VFD_INDEX_MAX: 225 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 222 +11843744: 0000: 00032242 000000de 000000e1 00000000 000000de +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843758: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12110 + :0,12109,12814,12110 +11843760: 0000: 0000057f 00002f4e +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 46 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[46] register values +!+ 00002f4d CP_SCRATCH_REG5: 12109 + :0,12109,12814,12110 +!+ 00002f4e CP_SCRATCH_REG7: 12110 + :0,12109,12814,12110 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000de VFD_INDEX_MIN: 222 +!+ 000000e1 VFD_INDEX_MAX: 225 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000de VFD_INDEX_OFFSET: 222 +11843768: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12111 + :0,12109,12814,12111 +11843778: 0000: 0000057f 00002f4f +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12112 + :0,12112,12814,12111 +11843780: 0000: 0000057d 00002f50 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843788: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843790: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 226 + VFD_INDEX_MAX: 229 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 226 +11843798: 0000: 00032242 000000e2 000000e5 00000000 000000e2 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118437ac: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12113 + :0,12112,12814,12113 +118437b4: 0000: 0000057f 00002f51 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 47 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[47] register values +!+ 00002f50 CP_SCRATCH_REG5: 12112 + :0,12112,12814,12113 +!+ 00002f51 CP_SCRATCH_REG7: 12113 + :0,12112,12814,12113 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000e2 VFD_INDEX_MIN: 226 +!+ 000000e5 VFD_INDEX_MAX: 229 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000e2 VFD_INDEX_OFFSET: 226 +118437bc: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12114 + :0,12112,12814,12114 +118437cc: 0000: 0000057f 00002f52 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12115 + :0,12115,12814,12114 +118437d4: 0000: 0000057d 00002f53 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118437dc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118437e4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 230 + VFD_INDEX_MAX: 233 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 230 +118437ec: 0000: 00032242 000000e6 000000e9 00000000 000000e6 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843800: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12116 + :0,12115,12814,12116 +11843808: 0000: 0000057f 00002f54 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 48 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[48] register values +!+ 00002f53 CP_SCRATCH_REG5: 12115 + :0,12115,12814,12116 +!+ 00002f54 CP_SCRATCH_REG7: 12116 + :0,12115,12814,12116 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000e6 VFD_INDEX_MIN: 230 +!+ 000000e9 VFD_INDEX_MAX: 233 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000e6 VFD_INDEX_OFFSET: 230 +11843810: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12117 + :0,12115,12814,12117 +11843820: 0000: 0000057f 00002f55 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12118 + :0,12118,12814,12117 +11843828: 0000: 0000057d 00002f56 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843830: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843838: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 234 + VFD_INDEX_MAX: 237 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 234 +11843840: 0000: 00032242 000000ea 000000ed 00000000 000000ea +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843854: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12119 + :0,12118,12814,12119 +1184385c: 0000: 0000057f 00002f57 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 49 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[49] register values +!+ 00002f56 CP_SCRATCH_REG5: 12118 + :0,12118,12814,12119 +!+ 00002f57 CP_SCRATCH_REG7: 12119 + :0,12118,12814,12119 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000ea VFD_INDEX_MIN: 234 +!+ 000000ed VFD_INDEX_MAX: 237 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000ea VFD_INDEX_OFFSET: 234 +11843864: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12120 + :0,12118,12814,12120 +11843874: 0000: 0000057f 00002f58 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12121 + :0,12121,12814,12120 +1184387c: 0000: 0000057d 00002f59 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843884: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184388c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 238 + VFD_INDEX_MAX: 244 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 238 +11843894: 0000: 00032242 000000ee 000000f4 00000000 000000ee +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118438a8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12122 + :0,12121,12814,12122 +118438b0: 0000: 0000057f 00002f5a +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 50 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[50] register values +!+ 00002f59 CP_SCRATCH_REG5: 12121 + :0,12121,12814,12122 +!+ 00002f5a CP_SCRATCH_REG7: 12122 + :0,12121,12814,12122 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000ee VFD_INDEX_MIN: 238 +!+ 000000f4 VFD_INDEX_MAX: 244 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000ee VFD_INDEX_OFFSET: 238 +118438b8: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12123 + :0,12121,12814,12123 +118438c8: 0000: 0000057f 00002f5b +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12124 + :0,12124,12814,12123 +118438d0: 0000: 0000057d 00002f5c +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118438d8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118438e0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 245 + VFD_INDEX_MAX: 248 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 245 +118438e8: 0000: 00032242 000000f5 000000f8 00000000 000000f5 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118438fc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12125 + :0,12124,12814,12125 +11843904: 0000: 0000057f 00002f5d +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 51 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[51] register values +!+ 00002f5c CP_SCRATCH_REG5: 12124 + :0,12124,12814,12125 +!+ 00002f5d CP_SCRATCH_REG7: 12125 + :0,12124,12814,12125 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000f5 VFD_INDEX_MIN: 245 +!+ 000000f8 VFD_INDEX_MAX: 248 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000f5 VFD_INDEX_OFFSET: 245 +1184390c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12126 + :0,12124,12814,12126 +1184391c: 0000: 0000057f 00002f5e +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12127 + :0,12127,12814,12126 +11843924: 0000: 0000057d 00002f5f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184392c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843934: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 249 + VFD_INDEX_MAX: 255 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 249 +1184393c: 0000: 00032242 000000f9 000000ff 00000000 000000f9 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843950: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12128 + :0,12127,12814,12128 +11843958: 0000: 0000057f 00002f60 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 52 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[52] register values +!+ 00002f5f CP_SCRATCH_REG5: 12127 + :0,12127,12814,12128 +!+ 00002f60 CP_SCRATCH_REG7: 12128 + :0,12127,12814,12128 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000f9 VFD_INDEX_MIN: 249 +!+ 000000ff VFD_INDEX_MAX: 255 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000f9 VFD_INDEX_OFFSET: 249 +11843960: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12129 + :0,12127,12814,12129 +11843970: 0000: 0000057f 00002f61 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12130 + :0,12130,12814,12129 +11843978: 0000: 0000057d 00002f62 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843980: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843988: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 256 + VFD_INDEX_MAX: 259 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 256 +11843990: 0000: 00032242 00000100 00000103 00000000 00000100 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118439a4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12131 + :0,12130,12814,12131 +118439ac: 0000: 0000057f 00002f63 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 53 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[53] register values +!+ 00002f62 CP_SCRATCH_REG5: 12130 + :0,12130,12814,12131 +!+ 00002f63 CP_SCRATCH_REG7: 12131 + :0,12130,12814,12131 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000100 VFD_INDEX_MIN: 256 +!+ 00000103 VFD_INDEX_MAX: 259 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000100 VFD_INDEX_OFFSET: 256 +118439b4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12132 + :0,12130,12814,12132 +118439c4: 0000: 0000057f 00002f64 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12133 + :0,12133,12814,12132 +118439cc: 0000: 0000057d 00002f65 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118439d4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118439dc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 260 + VFD_INDEX_MAX: 263 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 260 +118439e4: 0000: 00032242 00000104 00000107 00000000 00000104 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118439f8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12134 + :0,12133,12814,12134 +11843a00: 0000: 0000057f 00002f66 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 54 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[54] register values +!+ 00002f65 CP_SCRATCH_REG5: 12133 + :0,12133,12814,12134 +!+ 00002f66 CP_SCRATCH_REG7: 12134 + :0,12133,12814,12134 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000104 VFD_INDEX_MIN: 260 +!+ 00000107 VFD_INDEX_MAX: 263 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000104 VFD_INDEX_OFFSET: 260 +11843a08: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12135 + :0,12133,12814,12135 +11843a18: 0000: 0000057f 00002f67 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12136 + :0,12136,12814,12135 +11843a20: 0000: 0000057d 00002f68 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843a28: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843a30: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 264 + VFD_INDEX_MAX: 267 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 264 +11843a38: 0000: 00032242 00000108 0000010b 00000000 00000108 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843a4c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12137 + :0,12136,12814,12137 +11843a54: 0000: 0000057f 00002f69 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 55 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[55] register values +!+ 00002f68 CP_SCRATCH_REG5: 12136 + :0,12136,12814,12137 +!+ 00002f69 CP_SCRATCH_REG7: 12137 + :0,12136,12814,12137 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000108 VFD_INDEX_MIN: 264 +!+ 0000010b VFD_INDEX_MAX: 267 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000108 VFD_INDEX_OFFSET: 264 +11843a5c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12138 + :0,12136,12814,12138 +11843a6c: 0000: 0000057f 00002f6a +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12139 + :0,12139,12814,12138 +11843a74: 0000: 0000057d 00002f6b +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843a7c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843a84: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 268 + VFD_INDEX_MAX: 271 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 268 +11843a8c: 0000: 00032242 0000010c 0000010f 00000000 0000010c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843aa0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12140 + :0,12139,12814,12140 +11843aa8: 0000: 0000057f 00002f6c +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 56 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[56] register values +!+ 00002f6b CP_SCRATCH_REG5: 12139 + :0,12139,12814,12140 +!+ 00002f6c CP_SCRATCH_REG7: 12140 + :0,12139,12814,12140 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000010c VFD_INDEX_MIN: 268 +!+ 0000010f VFD_INDEX_MAX: 271 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000010c VFD_INDEX_OFFSET: 268 +11843ab0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12141 + :0,12139,12814,12141 +11843ac0: 0000: 0000057f 00002f6d +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12142 + :0,12142,12814,12141 +11843ac8: 0000: 0000057d 00002f6e +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843ad0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843ad8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 272 + VFD_INDEX_MAX: 278 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 272 +11843ae0: 0000: 00032242 00000110 00000116 00000000 00000110 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843af4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12143 + :0,12142,12814,12143 +11843afc: 0000: 0000057f 00002f6f +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 57 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[57] register values +!+ 00002f6e CP_SCRATCH_REG5: 12142 + :0,12142,12814,12143 +!+ 00002f6f CP_SCRATCH_REG7: 12143 + :0,12142,12814,12143 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000110 VFD_INDEX_MIN: 272 +!+ 00000116 VFD_INDEX_MAX: 278 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000110 VFD_INDEX_OFFSET: 272 +11843b04: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12144 + :0,12142,12814,12144 +11843b14: 0000: 0000057f 00002f70 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12145 + :0,12145,12814,12144 +11843b1c: 0000: 0000057d 00002f71 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843b24: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843b2c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 279 + VFD_INDEX_MAX: 282 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 279 +11843b34: 0000: 00032242 00000117 0000011a 00000000 00000117 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843b48: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12146 + :0,12145,12814,12146 +11843b50: 0000: 0000057f 00002f72 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 58 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[58] register values +!+ 00002f71 CP_SCRATCH_REG5: 12145 + :0,12145,12814,12146 +!+ 00002f72 CP_SCRATCH_REG7: 12146 + :0,12145,12814,12146 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000117 VFD_INDEX_MIN: 279 +!+ 0000011a VFD_INDEX_MAX: 282 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000117 VFD_INDEX_OFFSET: 279 +11843b58: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12147 + :0,12145,12814,12147 +11843b68: 0000: 0000057f 00002f73 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12148 + :0,12148,12814,12147 +11843b70: 0000: 0000057d 00002f74 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843b78: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843b80: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 283 + VFD_INDEX_MAX: 289 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 283 +11843b88: 0000: 00032242 0000011b 00000121 00000000 0000011b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843b9c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12149 + :0,12148,12814,12149 +11843ba4: 0000: 0000057f 00002f75 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 59 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[59] register values +!+ 00002f74 CP_SCRATCH_REG5: 12148 + :0,12148,12814,12149 +!+ 00002f75 CP_SCRATCH_REG7: 12149 + :0,12148,12814,12149 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000011b VFD_INDEX_MIN: 283 +!+ 00000121 VFD_INDEX_MAX: 289 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000011b VFD_INDEX_OFFSET: 283 +11843bac: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12150 + :0,12148,12814,12150 +11843bbc: 0000: 0000057f 00002f76 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12151 + :0,12151,12814,12150 +11843bc4: 0000: 0000057d 00002f77 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843bcc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843bd4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 290 + VFD_INDEX_MAX: 293 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 290 +11843bdc: 0000: 00032242 00000122 00000125 00000000 00000122 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843bf0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12152 + :0,12151,12814,12152 +11843bf8: 0000: 0000057f 00002f78 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 60 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[60] register values +!+ 00002f77 CP_SCRATCH_REG5: 12151 + :0,12151,12814,12152 +!+ 00002f78 CP_SCRATCH_REG7: 12152 + :0,12151,12814,12152 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000122 VFD_INDEX_MIN: 290 +!+ 00000125 VFD_INDEX_MAX: 293 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000122 VFD_INDEX_OFFSET: 290 +11843c00: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12153 + :0,12151,12814,12153 +11843c10: 0000: 0000057f 00002f79 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12154 + :0,12154,12814,12153 +11843c18: 0000: 0000057d 00002f7a +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843c20: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843c28: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 294 + VFD_INDEX_MAX: 297 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 294 +11843c30: 0000: 00032242 00000126 00000129 00000000 00000126 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843c44: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12155 + :0,12154,12814,12155 +11843c4c: 0000: 0000057f 00002f7b +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 61 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[61] register values +!+ 00002f7a CP_SCRATCH_REG5: 12154 + :0,12154,12814,12155 +!+ 00002f7b CP_SCRATCH_REG7: 12155 + :0,12154,12814,12155 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000126 VFD_INDEX_MIN: 294 +!+ 00000129 VFD_INDEX_MAX: 297 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000126 VFD_INDEX_OFFSET: 294 +11843c54: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12156 + :0,12154,12814,12156 +11843c64: 0000: 0000057f 00002f7c +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12157 + :0,12157,12814,12156 +11843c6c: 0000: 0000057d 00002f7d +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843c74: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843c7c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 298 + VFD_INDEX_MAX: 301 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 298 +11843c84: 0000: 00032242 0000012a 0000012d 00000000 0000012a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843c98: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12158 + :0,12157,12814,12158 +11843ca0: 0000: 0000057f 00002f7e +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 62 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[62] register values +!+ 00002f7d CP_SCRATCH_REG5: 12157 + :0,12157,12814,12158 +!+ 00002f7e CP_SCRATCH_REG7: 12158 + :0,12157,12814,12158 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000012a VFD_INDEX_MIN: 298 +!+ 0000012d VFD_INDEX_MAX: 301 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000012a VFD_INDEX_OFFSET: 298 +11843ca8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12159 + :0,12157,12814,12159 +11843cb8: 0000: 0000057f 00002f7f +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12160 + :0,12160,12814,12159 +11843cc0: 0000: 0000057d 00002f80 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843cc8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843cd0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 302 + VFD_INDEX_MAX: 305 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 302 +11843cd8: 0000: 00032242 0000012e 00000131 00000000 0000012e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843cec: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12161 + :0,12160,12814,12161 +11843cf4: 0000: 0000057f 00002f81 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 63 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[63] register values +!+ 00002f80 CP_SCRATCH_REG5: 12160 + :0,12160,12814,12161 +!+ 00002f81 CP_SCRATCH_REG7: 12161 + :0,12160,12814,12161 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000012e VFD_INDEX_MIN: 302 +!+ 00000131 VFD_INDEX_MAX: 305 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000012e VFD_INDEX_OFFSET: 302 +11843cfc: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12162 + :0,12160,12814,12162 +11843d0c: 0000: 0000057f 00002f82 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12163 + :0,12163,12814,12162 +11843d14: 0000: 0000057d 00002f83 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843d1c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843d24: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 306 + VFD_INDEX_MAX: 312 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 306 +11843d2c: 0000: 00032242 00000132 00000138 00000000 00000132 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843d40: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12164 + :0,12163,12814,12164 +11843d48: 0000: 0000057f 00002f84 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 64 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[64] register values +!+ 00002f83 CP_SCRATCH_REG5: 12163 + :0,12163,12814,12164 +!+ 00002f84 CP_SCRATCH_REG7: 12164 + :0,12163,12814,12164 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000132 VFD_INDEX_MIN: 306 +!+ 00000138 VFD_INDEX_MAX: 312 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000132 VFD_INDEX_OFFSET: 306 +11843d50: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12165 + :0,12163,12814,12165 +11843d60: 0000: 0000057f 00002f85 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12166 + :0,12166,12814,12165 +11843d68: 0000: 0000057d 00002f86 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843d70: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843d78: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 313 + VFD_INDEX_MAX: 316 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 313 +11843d80: 0000: 00032242 00000139 0000013c 00000000 00000139 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843d94: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12167 + :0,12166,12814,12167 +11843d9c: 0000: 0000057f 00002f87 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 65 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[65] register values +!+ 00002f86 CP_SCRATCH_REG5: 12166 + :0,12166,12814,12167 +!+ 00002f87 CP_SCRATCH_REG7: 12167 + :0,12166,12814,12167 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000139 VFD_INDEX_MIN: 313 +!+ 0000013c VFD_INDEX_MAX: 316 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000139 VFD_INDEX_OFFSET: 313 +11843da4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12168 + :0,12166,12814,12168 +11843db4: 0000: 0000057f 00002f88 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12169 + :0,12169,12814,12168 +11843dbc: 0000: 0000057d 00002f89 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843dc4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843dcc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 317 + VFD_INDEX_MAX: 323 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 317 +11843dd4: 0000: 00032242 0000013d 00000143 00000000 0000013d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843de8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12170 + :0,12169,12814,12170 +11843df0: 0000: 0000057f 00002f8a +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 66 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[66] register values +!+ 00002f89 CP_SCRATCH_REG5: 12169 + :0,12169,12814,12170 +!+ 00002f8a CP_SCRATCH_REG7: 12170 + :0,12169,12814,12170 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000013d VFD_INDEX_MIN: 317 +!+ 00000143 VFD_INDEX_MAX: 323 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000013d VFD_INDEX_OFFSET: 317 +11843df8: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12171 + :0,12169,12814,12171 +11843e08: 0000: 0000057f 00002f8b +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12172 + :0,12172,12814,12171 +11843e10: 0000: 0000057d 00002f8c +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843e18: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843e20: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 324 + VFD_INDEX_MAX: 327 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 324 +11843e28: 0000: 00032242 00000144 00000147 00000000 00000144 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843e3c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12173 + :0,12172,12814,12173 +11843e44: 0000: 0000057f 00002f8d +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 67 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[67] register values +!+ 00002f8c CP_SCRATCH_REG5: 12172 + :0,12172,12814,12173 +!+ 00002f8d CP_SCRATCH_REG7: 12173 + :0,12172,12814,12173 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000144 VFD_INDEX_MIN: 324 +!+ 00000147 VFD_INDEX_MAX: 327 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000144 VFD_INDEX_OFFSET: 324 +11843e4c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12174 + :0,12172,12814,12174 +11843e5c: 0000: 0000057f 00002f8e +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12175 + :0,12175,12814,12174 +11843e64: 0000: 0000057d 00002f8f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843e6c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843e74: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 328 + VFD_INDEX_MAX: 331 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 328 +11843e7c: 0000: 00032242 00000148 0000014b 00000000 00000148 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843e90: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12176 + :0,12175,12814,12176 +11843e98: 0000: 0000057f 00002f90 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 68 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[68] register values +!+ 00002f8f CP_SCRATCH_REG5: 12175 + :0,12175,12814,12176 +!+ 00002f90 CP_SCRATCH_REG7: 12176 + :0,12175,12814,12176 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000148 VFD_INDEX_MIN: 328 +!+ 0000014b VFD_INDEX_MAX: 331 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000148 VFD_INDEX_OFFSET: 328 +11843ea0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12177 + :0,12175,12814,12177 +11843eb0: 0000: 0000057f 00002f91 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12178 + :0,12178,12814,12177 +11843eb8: 0000: 0000057d 00002f92 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843ec0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843ec8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 332 + VFD_INDEX_MAX: 335 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 332 +11843ed0: 0000: 00032242 0000014c 0000014f 00000000 0000014c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843ee4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12179 + :0,12178,12814,12179 +11843eec: 0000: 0000057f 00002f93 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 69 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[69] register values +!+ 00002f92 CP_SCRATCH_REG5: 12178 + :0,12178,12814,12179 +!+ 00002f93 CP_SCRATCH_REG7: 12179 + :0,12178,12814,12179 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000014c VFD_INDEX_MIN: 332 +!+ 0000014f VFD_INDEX_MAX: 335 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000014c VFD_INDEX_OFFSET: 332 +11843ef4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12180 + :0,12178,12814,12180 +11843f04: 0000: 0000057f 00002f94 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12181 + :0,12181,12814,12180 +11843f0c: 0000: 0000057d 00002f95 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843f14: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843f1c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 336 + VFD_INDEX_MAX: 339 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 336 +11843f24: 0000: 00032242 00000150 00000153 00000000 00000150 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843f38: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12182 + :0,12181,12814,12182 +11843f40: 0000: 0000057f 00002f96 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 70 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[70] register values +!+ 00002f95 CP_SCRATCH_REG5: 12181 + :0,12181,12814,12182 +!+ 00002f96 CP_SCRATCH_REG7: 12182 + :0,12181,12814,12182 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000150 VFD_INDEX_MIN: 336 +!+ 00000153 VFD_INDEX_MAX: 339 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000150 VFD_INDEX_OFFSET: 336 +11843f48: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12183 + :0,12181,12814,12183 +11843f58: 0000: 0000057f 00002f97 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12184 + :0,12184,12814,12183 +11843f60: 0000: 0000057d 00002f98 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843f68: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843f70: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 340 + VFD_INDEX_MAX: 346 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 340 +11843f78: 0000: 00032242 00000154 0000015a 00000000 00000154 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843f8c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12185 + :0,12184,12814,12185 +11843f94: 0000: 0000057f 00002f99 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 71 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[71] register values +!+ 00002f98 CP_SCRATCH_REG5: 12184 + :0,12184,12814,12185 +!+ 00002f99 CP_SCRATCH_REG7: 12185 + :0,12184,12814,12185 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000154 VFD_INDEX_MIN: 340 +!+ 0000015a VFD_INDEX_MAX: 346 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000154 VFD_INDEX_OFFSET: 340 +11843f9c: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12186 + :0,12184,12814,12186 +11843fac: 0000: 0000057f 00002f9a +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12187 + :0,12187,12814,12186 +11843fb4: 0000: 0000057d 00002f9b +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11843fbc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11843fc4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 347 + VFD_INDEX_MAX: 350 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 347 +11843fcc: 0000: 00032242 0000015b 0000015e 00000000 0000015b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11843fe0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12188 + :0,12187,12814,12188 +11843fe8: 0000: 0000057f 00002f9c +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 72 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[72] register values +!+ 00002f9b CP_SCRATCH_REG5: 12187 + :0,12187,12814,12188 +!+ 00002f9c CP_SCRATCH_REG7: 12188 + :0,12187,12814,12188 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000015b VFD_INDEX_MIN: 347 +!+ 0000015e VFD_INDEX_MAX: 350 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000015b VFD_INDEX_OFFSET: 347 +11843ff0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12189 + :0,12187,12814,12189 +11844000: 0000: 0000057f 00002f9d +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12190 + :0,12190,12814,12189 +11844008: 0000: 0000057d 00002f9e +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844010: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844018: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 351 + VFD_INDEX_MAX: 357 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 351 +11844020: 0000: 00032242 0000015f 00000165 00000000 0000015f +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844034: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12191 + :0,12190,12814,12191 +1184403c: 0000: 0000057f 00002f9f +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 73 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[73] register values +!+ 00002f9e CP_SCRATCH_REG5: 12190 + :0,12190,12814,12191 +!+ 00002f9f CP_SCRATCH_REG7: 12191 + :0,12190,12814,12191 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000015f VFD_INDEX_MIN: 351 +!+ 00000165 VFD_INDEX_MAX: 357 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000015f VFD_INDEX_OFFSET: 351 +11844044: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12192 + :0,12190,12814,12192 +11844054: 0000: 0000057f 00002fa0 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12193 + :0,12193,12814,12192 +1184405c: 0000: 0000057d 00002fa1 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844064: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184406c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 358 + VFD_INDEX_MAX: 361 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 358 +11844074: 0000: 00032242 00000166 00000169 00000000 00000166 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844088: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12194 + :0,12193,12814,12194 +11844090: 0000: 0000057f 00002fa2 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 74 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[74] register values +!+ 00002fa1 CP_SCRATCH_REG5: 12193 + :0,12193,12814,12194 +!+ 00002fa2 CP_SCRATCH_REG7: 12194 + :0,12193,12814,12194 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000166 VFD_INDEX_MIN: 358 +!+ 00000169 VFD_INDEX_MAX: 361 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000166 VFD_INDEX_OFFSET: 358 +11844098: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12195 + :0,12193,12814,12195 +118440a8: 0000: 0000057f 00002fa3 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12196 + :0,12196,12814,12195 +118440b0: 0000: 0000057d 00002fa4 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118440b8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118440c0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 362 + VFD_INDEX_MAX: 365 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 362 +118440c8: 0000: 00032242 0000016a 0000016d 00000000 0000016a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118440dc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12197 + :0,12196,12814,12197 +118440e4: 0000: 0000057f 00002fa5 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 75 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[75] register values +!+ 00002fa4 CP_SCRATCH_REG5: 12196 + :0,12196,12814,12197 +!+ 00002fa5 CP_SCRATCH_REG7: 12197 + :0,12196,12814,12197 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000016a VFD_INDEX_MIN: 362 +!+ 0000016d VFD_INDEX_MAX: 365 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000016a VFD_INDEX_OFFSET: 362 +118440ec: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12198 + :0,12196,12814,12198 +118440fc: 0000: 0000057f 00002fa6 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12199 + :0,12199,12814,12198 +11844104: 0000: 0000057d 00002fa7 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184410c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844114: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 366 + VFD_INDEX_MAX: 369 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 366 +1184411c: 0000: 00032242 0000016e 00000171 00000000 0000016e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844130: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12200 + :0,12199,12814,12200 +11844138: 0000: 0000057f 00002fa8 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 76 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[76] register values +!+ 00002fa7 CP_SCRATCH_REG5: 12199 + :0,12199,12814,12200 +!+ 00002fa8 CP_SCRATCH_REG7: 12200 + :0,12199,12814,12200 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000016e VFD_INDEX_MIN: 366 +!+ 00000171 VFD_INDEX_MAX: 369 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000016e VFD_INDEX_OFFSET: 366 +11844140: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12201 + :0,12199,12814,12201 +11844150: 0000: 0000057f 00002fa9 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12202 + :0,12202,12814,12201 +11844158: 0000: 0000057d 00002faa +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844160: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844168: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 370 + VFD_INDEX_MAX: 373 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 370 +11844170: 0000: 00032242 00000172 00000175 00000000 00000172 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844184: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12203 + :0,12202,12814,12203 +1184418c: 0000: 0000057f 00002fab +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 77 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[77] register values +!+ 00002faa CP_SCRATCH_REG5: 12202 + :0,12202,12814,12203 +!+ 00002fab CP_SCRATCH_REG7: 12203 + :0,12202,12814,12203 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000172 VFD_INDEX_MIN: 370 +!+ 00000175 VFD_INDEX_MAX: 373 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000172 VFD_INDEX_OFFSET: 370 +11844194: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12204 + :0,12202,12814,12204 +118441a4: 0000: 0000057f 00002fac +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12205 + :0,12205,12814,12204 +118441ac: 0000: 0000057d 00002fad +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118441b4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118441bc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 374 + VFD_INDEX_MAX: 380 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 374 +118441c4: 0000: 00032242 00000176 0000017c 00000000 00000176 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118441d8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12206 + :0,12205,12814,12206 +118441e0: 0000: 0000057f 00002fae +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 78 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[78] register values +!+ 00002fad CP_SCRATCH_REG5: 12205 + :0,12205,12814,12206 +!+ 00002fae CP_SCRATCH_REG7: 12206 + :0,12205,12814,12206 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000176 VFD_INDEX_MIN: 374 +!+ 0000017c VFD_INDEX_MAX: 380 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000176 VFD_INDEX_OFFSET: 374 +118441e8: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12207 + :0,12205,12814,12207 +118441f8: 0000: 0000057f 00002faf +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12208 + :0,12208,12814,12207 +11844200: 0000: 0000057d 00002fb0 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844208: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844210: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 381 + VFD_INDEX_MAX: 384 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 381 +11844218: 0000: 00032242 0000017d 00000180 00000000 0000017d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184422c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12209 + :0,12208,12814,12209 +11844234: 0000: 0000057f 00002fb1 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 79 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[79] register values +!+ 00002fb0 CP_SCRATCH_REG5: 12208 + :0,12208,12814,12209 +!+ 00002fb1 CP_SCRATCH_REG7: 12209 + :0,12208,12814,12209 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000017d VFD_INDEX_MIN: 381 +!+ 00000180 VFD_INDEX_MAX: 384 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000017d VFD_INDEX_OFFSET: 381 +1184423c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12210 + :0,12208,12814,12210 +1184424c: 0000: 0000057f 00002fb2 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12211 + :0,12211,12814,12210 +11844254: 0000: 0000057d 00002fb3 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184425c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844264: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 385 + VFD_INDEX_MAX: 391 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 385 +1184426c: 0000: 00032242 00000181 00000187 00000000 00000181 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844280: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12212 + :0,12211,12814,12212 +11844288: 0000: 0000057f 00002fb4 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 80 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[80] register values +!+ 00002fb3 CP_SCRATCH_REG5: 12211 + :0,12211,12814,12212 +!+ 00002fb4 CP_SCRATCH_REG7: 12212 + :0,12211,12814,12212 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000181 VFD_INDEX_MIN: 385 +!+ 00000187 VFD_INDEX_MAX: 391 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000181 VFD_INDEX_OFFSET: 385 +11844290: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12213 + :0,12211,12814,12213 +118442a0: 0000: 0000057f 00002fb5 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12214 + :0,12214,12814,12213 +118442a8: 0000: 0000057d 00002fb6 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118442b0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118442b8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 392 + VFD_INDEX_MAX: 395 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 392 +118442c0: 0000: 00032242 00000188 0000018b 00000000 00000188 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118442d4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12215 + :0,12214,12814,12215 +118442dc: 0000: 0000057f 00002fb7 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 81 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[81] register values +!+ 00002fb6 CP_SCRATCH_REG5: 12214 + :0,12214,12814,12215 +!+ 00002fb7 CP_SCRATCH_REG7: 12215 + :0,12214,12814,12215 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000188 VFD_INDEX_MIN: 392 +!+ 0000018b VFD_INDEX_MAX: 395 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000188 VFD_INDEX_OFFSET: 392 +118442e4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12216 + :0,12214,12814,12216 +118442f4: 0000: 0000057f 00002fb8 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12217 + :0,12217,12814,12216 +118442fc: 0000: 0000057d 00002fb9 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844304: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184430c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 396 + VFD_INDEX_MAX: 399 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 396 +11844314: 0000: 00032242 0000018c 0000018f 00000000 0000018c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844328: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12218 + :0,12217,12814,12218 +11844330: 0000: 0000057f 00002fba +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 82 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[82] register values +!+ 00002fb9 CP_SCRATCH_REG5: 12217 + :0,12217,12814,12218 +!+ 00002fba CP_SCRATCH_REG7: 12218 + :0,12217,12814,12218 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000018c VFD_INDEX_MIN: 396 +!+ 0000018f VFD_INDEX_MAX: 399 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000018c VFD_INDEX_OFFSET: 396 +11844338: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12219 + :0,12217,12814,12219 +11844348: 0000: 0000057f 00002fbb +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12220 + :0,12220,12814,12219 +11844350: 0000: 0000057d 00002fbc +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844358: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844360: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 400 + VFD_INDEX_MAX: 403 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 400 +11844368: 0000: 00032242 00000190 00000193 00000000 00000190 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184437c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12221 + :0,12220,12814,12221 +11844384: 0000: 0000057f 00002fbd +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 83 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[83] register values +!+ 00002fbc CP_SCRATCH_REG5: 12220 + :0,12220,12814,12221 +!+ 00002fbd CP_SCRATCH_REG7: 12221 + :0,12220,12814,12221 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000190 VFD_INDEX_MIN: 400 +!+ 00000193 VFD_INDEX_MAX: 403 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000190 VFD_INDEX_OFFSET: 400 +1184438c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12222 + :0,12220,12814,12222 +1184439c: 0000: 0000057f 00002fbe +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12223 + :0,12223,12814,12222 +118443a4: 0000: 0000057d 00002fbf +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118443ac: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118443b4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 404 + VFD_INDEX_MAX: 407 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 404 +118443bc: 0000: 00032242 00000194 00000197 00000000 00000194 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118443d0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12224 + :0,12223,12814,12224 +118443d8: 0000: 0000057f 00002fc0 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 84 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[84] register values +!+ 00002fbf CP_SCRATCH_REG5: 12223 + :0,12223,12814,12224 +!+ 00002fc0 CP_SCRATCH_REG7: 12224 + :0,12223,12814,12224 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000194 VFD_INDEX_MIN: 404 +!+ 00000197 VFD_INDEX_MAX: 407 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000194 VFD_INDEX_OFFSET: 404 +118443e0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12225 + :0,12223,12814,12225 +118443f0: 0000: 0000057f 00002fc1 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12226 + :0,12226,12814,12225 +118443f8: 0000: 0000057d 00002fc2 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844400: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844408: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 408 + VFD_INDEX_MAX: 414 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 408 +11844410: 0000: 00032242 00000198 0000019e 00000000 00000198 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844424: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12227 + :0,12226,12814,12227 +1184442c: 0000: 0000057f 00002fc3 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 85 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[85] register values +!+ 00002fc2 CP_SCRATCH_REG5: 12226 + :0,12226,12814,12227 +!+ 00002fc3 CP_SCRATCH_REG7: 12227 + :0,12226,12814,12227 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000198 VFD_INDEX_MIN: 408 +!+ 0000019e VFD_INDEX_MAX: 414 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000198 VFD_INDEX_OFFSET: 408 +11844434: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12228 + :0,12226,12814,12228 +11844444: 0000: 0000057f 00002fc4 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12229 + :0,12229,12814,12228 +1184444c: 0000: 0000057d 00002fc5 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844454: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184445c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 415 + VFD_INDEX_MAX: 418 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 415 +11844464: 0000: 00032242 0000019f 000001a2 00000000 0000019f +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844478: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12230 + :0,12229,12814,12230 +11844480: 0000: 0000057f 00002fc6 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 86 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[86] register values +!+ 00002fc5 CP_SCRATCH_REG5: 12229 + :0,12229,12814,12230 +!+ 00002fc6 CP_SCRATCH_REG7: 12230 + :0,12229,12814,12230 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000019f VFD_INDEX_MIN: 415 +!+ 000001a2 VFD_INDEX_MAX: 418 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000019f VFD_INDEX_OFFSET: 415 +11844488: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12231 + :0,12229,12814,12231 +11844498: 0000: 0000057f 00002fc7 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12232 + :0,12232,12814,12231 +118444a0: 0000: 0000057d 00002fc8 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118444a8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118444b0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 419 + VFD_INDEX_MAX: 425 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 419 +118444b8: 0000: 00032242 000001a3 000001a9 00000000 000001a3 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118444cc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12233 + :0,12232,12814,12233 +118444d4: 0000: 0000057f 00002fc9 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 87 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[87] register values +!+ 00002fc8 CP_SCRATCH_REG5: 12232 + :0,12232,12814,12233 +!+ 00002fc9 CP_SCRATCH_REG7: 12233 + :0,12232,12814,12233 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001a3 VFD_INDEX_MIN: 419 +!+ 000001a9 VFD_INDEX_MAX: 425 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001a3 VFD_INDEX_OFFSET: 419 +118444dc: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12234 + :0,12232,12814,12234 +118444ec: 0000: 0000057f 00002fca +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12235 + :0,12235,12814,12234 +118444f4: 0000: 0000057d 00002fcb +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118444fc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844504: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 426 + VFD_INDEX_MAX: 429 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 426 +1184450c: 0000: 00032242 000001aa 000001ad 00000000 000001aa +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844520: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12236 + :0,12235,12814,12236 +11844528: 0000: 0000057f 00002fcc +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 88 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[88] register values +!+ 00002fcb CP_SCRATCH_REG5: 12235 + :0,12235,12814,12236 +!+ 00002fcc CP_SCRATCH_REG7: 12236 + :0,12235,12814,12236 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001aa VFD_INDEX_MIN: 426 +!+ 000001ad VFD_INDEX_MAX: 429 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001aa VFD_INDEX_OFFSET: 426 +11844530: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12237 + :0,12235,12814,12237 +11844540: 0000: 0000057f 00002fcd +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12238 + :0,12238,12814,12237 +11844548: 0000: 0000057d 00002fce +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844550: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844558: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 430 + VFD_INDEX_MAX: 433 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 430 +11844560: 0000: 00032242 000001ae 000001b1 00000000 000001ae +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844574: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12239 + :0,12238,12814,12239 +1184457c: 0000: 0000057f 00002fcf +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 89 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[89] register values +!+ 00002fce CP_SCRATCH_REG5: 12238 + :0,12238,12814,12239 +!+ 00002fcf CP_SCRATCH_REG7: 12239 + :0,12238,12814,12239 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001ae VFD_INDEX_MIN: 430 +!+ 000001b1 VFD_INDEX_MAX: 433 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001ae VFD_INDEX_OFFSET: 430 +11844584: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12240 + :0,12238,12814,12240 +11844594: 0000: 0000057f 00002fd0 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12241 + :0,12241,12814,12240 +1184459c: 0000: 0000057d 00002fd1 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118445a4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118445ac: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 434 + VFD_INDEX_MAX: 437 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 434 +118445b4: 0000: 00032242 000001b2 000001b5 00000000 000001b2 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118445c8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12242 + :0,12241,12814,12242 +118445d0: 0000: 0000057f 00002fd2 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 90 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[90] register values +!+ 00002fd1 CP_SCRATCH_REG5: 12241 + :0,12241,12814,12242 +!+ 00002fd2 CP_SCRATCH_REG7: 12242 + :0,12241,12814,12242 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001b2 VFD_INDEX_MIN: 434 +!+ 000001b5 VFD_INDEX_MAX: 437 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001b2 VFD_INDEX_OFFSET: 434 +118445d8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12243 + :0,12241,12814,12243 +118445e8: 0000: 0000057f 00002fd3 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12244 + :0,12244,12814,12243 +118445f0: 0000: 0000057d 00002fd4 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118445f8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844600: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 438 + VFD_INDEX_MAX: 441 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 438 +11844608: 0000: 00032242 000001b6 000001b9 00000000 000001b6 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184461c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12245 + :0,12244,12814,12245 +11844624: 0000: 0000057f 00002fd5 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 91 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[91] register values +!+ 00002fd4 CP_SCRATCH_REG5: 12244 + :0,12244,12814,12245 +!+ 00002fd5 CP_SCRATCH_REG7: 12245 + :0,12244,12814,12245 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001b6 VFD_INDEX_MIN: 438 +!+ 000001b9 VFD_INDEX_MAX: 441 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001b6 VFD_INDEX_OFFSET: 438 +1184462c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12246 + :0,12244,12814,12246 +1184463c: 0000: 0000057f 00002fd6 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12247 + :0,12247,12814,12246 +11844644: 0000: 0000057d 00002fd7 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184464c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844654: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 442 + VFD_INDEX_MAX: 448 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 442 +1184465c: 0000: 00032242 000001ba 000001c0 00000000 000001ba +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844670: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12248 + :0,12247,12814,12248 +11844678: 0000: 0000057f 00002fd8 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 92 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[92] register values +!+ 00002fd7 CP_SCRATCH_REG5: 12247 + :0,12247,12814,12248 +!+ 00002fd8 CP_SCRATCH_REG7: 12248 + :0,12247,12814,12248 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001ba VFD_INDEX_MIN: 442 +!+ 000001c0 VFD_INDEX_MAX: 448 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001ba VFD_INDEX_OFFSET: 442 +11844680: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12249 + :0,12247,12814,12249 +11844690: 0000: 0000057f 00002fd9 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12250 + :0,12250,12814,12249 +11844698: 0000: 0000057d 00002fda +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118446a0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118446a8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 449 + VFD_INDEX_MAX: 452 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 449 +118446b0: 0000: 00032242 000001c1 000001c4 00000000 000001c1 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118446c4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12251 + :0,12250,12814,12251 +118446cc: 0000: 0000057f 00002fdb +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 93 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[93] register values +!+ 00002fda CP_SCRATCH_REG5: 12250 + :0,12250,12814,12251 +!+ 00002fdb CP_SCRATCH_REG7: 12251 + :0,12250,12814,12251 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001c1 VFD_INDEX_MIN: 449 +!+ 000001c4 VFD_INDEX_MAX: 452 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001c1 VFD_INDEX_OFFSET: 449 +118446d4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12252 + :0,12250,12814,12252 +118446e4: 0000: 0000057f 00002fdc +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12253 + :0,12253,12814,12252 +118446ec: 0000: 0000057d 00002fdd +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118446f4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118446fc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 453 + VFD_INDEX_MAX: 459 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 453 +11844704: 0000: 00032242 000001c5 000001cb 00000000 000001c5 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844718: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12254 + :0,12253,12814,12254 +11844720: 0000: 0000057f 00002fde +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 94 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[94] register values +!+ 00002fdd CP_SCRATCH_REG5: 12253 + :0,12253,12814,12254 +!+ 00002fde CP_SCRATCH_REG7: 12254 + :0,12253,12814,12254 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001c5 VFD_INDEX_MIN: 453 +!+ 000001cb VFD_INDEX_MAX: 459 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001c5 VFD_INDEX_OFFSET: 453 +11844728: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12255 + :0,12253,12814,12255 +11844738: 0000: 0000057f 00002fdf +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12256 + :0,12256,12814,12255 +11844740: 0000: 0000057d 00002fe0 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844748: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844750: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 460 + VFD_INDEX_MAX: 463 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 460 +11844758: 0000: 00032242 000001cc 000001cf 00000000 000001cc +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184476c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12257 + :0,12256,12814,12257 +11844774: 0000: 0000057f 00002fe1 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 95 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[95] register values +!+ 00002fe0 CP_SCRATCH_REG5: 12256 + :0,12256,12814,12257 +!+ 00002fe1 CP_SCRATCH_REG7: 12257 + :0,12256,12814,12257 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001cc VFD_INDEX_MIN: 460 +!+ 000001cf VFD_INDEX_MAX: 463 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001cc VFD_INDEX_OFFSET: 460 +1184477c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12258 + :0,12256,12814,12258 +1184478c: 0000: 0000057f 00002fe2 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12259 + :0,12259,12814,12258 +11844794: 0000: 0000057d 00002fe3 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184479c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118447a4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 464 + VFD_INDEX_MAX: 467 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 464 +118447ac: 0000: 00032242 000001d0 000001d3 00000000 000001d0 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118447c0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12260 + :0,12259,12814,12260 +118447c8: 0000: 0000057f 00002fe4 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 96 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[96] register values +!+ 00002fe3 CP_SCRATCH_REG5: 12259 + :0,12259,12814,12260 +!+ 00002fe4 CP_SCRATCH_REG7: 12260 + :0,12259,12814,12260 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001d0 VFD_INDEX_MIN: 464 +!+ 000001d3 VFD_INDEX_MAX: 467 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001d0 VFD_INDEX_OFFSET: 464 +118447d0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12261 + :0,12259,12814,12261 +118447e0: 0000: 0000057f 00002fe5 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12262 + :0,12262,12814,12261 +118447e8: 0000: 0000057d 00002fe6 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118447f0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118447f8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 468 + VFD_INDEX_MAX: 471 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 468 +11844800: 0000: 00032242 000001d4 000001d7 00000000 000001d4 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844814: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12263 + :0,12262,12814,12263 +1184481c: 0000: 0000057f 00002fe7 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 97 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[97] register values +!+ 00002fe6 CP_SCRATCH_REG5: 12262 + :0,12262,12814,12263 +!+ 00002fe7 CP_SCRATCH_REG7: 12263 + :0,12262,12814,12263 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001d4 VFD_INDEX_MIN: 468 +!+ 000001d7 VFD_INDEX_MAX: 471 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001d4 VFD_INDEX_OFFSET: 468 +11844824: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12264 + :0,12262,12814,12264 +11844834: 0000: 0000057f 00002fe8 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12265 + :0,12265,12814,12264 +1184483c: 0000: 0000057d 00002fe9 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844844: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184484c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 472 + VFD_INDEX_MAX: 475 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 472 +11844854: 0000: 00032242 000001d8 000001db 00000000 000001d8 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844868: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12266 + :0,12265,12814,12266 +11844870: 0000: 0000057f 00002fea +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 98 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[98] register values +!+ 00002fe9 CP_SCRATCH_REG5: 12265 + :0,12265,12814,12266 +!+ 00002fea CP_SCRATCH_REG7: 12266 + :0,12265,12814,12266 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001d8 VFD_INDEX_MIN: 472 +!+ 000001db VFD_INDEX_MAX: 475 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001d8 VFD_INDEX_OFFSET: 472 +11844878: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12267 + :0,12265,12814,12267 +11844888: 0000: 0000057f 00002feb +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12268 + :0,12268,12814,12267 +11844890: 0000: 0000057d 00002fec +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844898: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118448a0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 476 + VFD_INDEX_MAX: 482 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 476 +118448a8: 0000: 00032242 000001dc 000001e2 00000000 000001dc +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118448bc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12269 + :0,12268,12814,12269 +118448c4: 0000: 0000057f 00002fed +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 99 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[99] register values +!+ 00002fec CP_SCRATCH_REG5: 12268 + :0,12268,12814,12269 +!+ 00002fed CP_SCRATCH_REG7: 12269 + :0,12268,12814,12269 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001dc VFD_INDEX_MIN: 476 +!+ 000001e2 VFD_INDEX_MAX: 482 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001dc VFD_INDEX_OFFSET: 476 +118448cc: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12270 + :0,12268,12814,12270 +118448dc: 0000: 0000057f 00002fee +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12271 + :0,12271,12814,12270 +118448e4: 0000: 0000057d 00002fef +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118448ec: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118448f4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 483 + VFD_INDEX_MAX: 486 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 483 +118448fc: 0000: 00032242 000001e3 000001e6 00000000 000001e3 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844910: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12272 + :0,12271,12814,12272 +11844918: 0000: 0000057f 00002ff0 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 100 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[100] register values +!+ 00002fef CP_SCRATCH_REG5: 12271 + :0,12271,12814,12272 +!+ 00002ff0 CP_SCRATCH_REG7: 12272 + :0,12271,12814,12272 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001e3 VFD_INDEX_MIN: 483 +!+ 000001e6 VFD_INDEX_MAX: 486 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001e3 VFD_INDEX_OFFSET: 483 +11844920: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12273 + :0,12271,12814,12273 +11844930: 0000: 0000057f 00002ff1 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12274 + :0,12274,12814,12273 +11844938: 0000: 0000057d 00002ff2 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844940: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844948: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 487 + VFD_INDEX_MAX: 493 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 487 +11844950: 0000: 00032242 000001e7 000001ed 00000000 000001e7 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844964: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12275 + :0,12274,12814,12275 +1184496c: 0000: 0000057f 00002ff3 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 101 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[101] register values +!+ 00002ff2 CP_SCRATCH_REG5: 12274 + :0,12274,12814,12275 +!+ 00002ff3 CP_SCRATCH_REG7: 12275 + :0,12274,12814,12275 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001e7 VFD_INDEX_MIN: 487 +!+ 000001ed VFD_INDEX_MAX: 493 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001e7 VFD_INDEX_OFFSET: 487 +11844974: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12276 + :0,12274,12814,12276 +11844984: 0000: 0000057f 00002ff4 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12277 + :0,12277,12814,12276 +1184498c: 0000: 0000057d 00002ff5 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844994: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184499c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 494 + VFD_INDEX_MAX: 497 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 494 +118449a4: 0000: 00032242 000001ee 000001f1 00000000 000001ee +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118449b8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12278 + :0,12277,12814,12278 +118449c0: 0000: 0000057f 00002ff6 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 102 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[102] register values +!+ 00002ff5 CP_SCRATCH_REG5: 12277 + :0,12277,12814,12278 +!+ 00002ff6 CP_SCRATCH_REG7: 12278 + :0,12277,12814,12278 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001ee VFD_INDEX_MIN: 494 +!+ 000001f1 VFD_INDEX_MAX: 497 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001ee VFD_INDEX_OFFSET: 494 +118449c8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12279 + :0,12277,12814,12279 +118449d8: 0000: 0000057f 00002ff7 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12280 + :0,12280,12814,12279 +118449e0: 0000: 0000057d 00002ff8 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118449e8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118449f0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 498 + VFD_INDEX_MAX: 501 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 498 +118449f8: 0000: 00032242 000001f2 000001f5 00000000 000001f2 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844a0c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12281 + :0,12280,12814,12281 +11844a14: 0000: 0000057f 00002ff9 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 103 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[103] register values +!+ 00002ff8 CP_SCRATCH_REG5: 12280 + :0,12280,12814,12281 +!+ 00002ff9 CP_SCRATCH_REG7: 12281 + :0,12280,12814,12281 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001f2 VFD_INDEX_MIN: 498 +!+ 000001f5 VFD_INDEX_MAX: 501 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001f2 VFD_INDEX_OFFSET: 498 +11844a1c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12282 + :0,12280,12814,12282 +11844a2c: 0000: 0000057f 00002ffa +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12283 + :0,12283,12814,12282 +11844a34: 0000: 0000057d 00002ffb +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844a3c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844a44: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 502 + VFD_INDEX_MAX: 505 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 502 +11844a4c: 0000: 00032242 000001f6 000001f9 00000000 000001f6 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844a60: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12284 + :0,12283,12814,12284 +11844a68: 0000: 0000057f 00002ffc +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 104 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[104] register values +!+ 00002ffb CP_SCRATCH_REG5: 12283 + :0,12283,12814,12284 +!+ 00002ffc CP_SCRATCH_REG7: 12284 + :0,12283,12814,12284 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001f6 VFD_INDEX_MIN: 502 +!+ 000001f9 VFD_INDEX_MAX: 505 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001f6 VFD_INDEX_OFFSET: 502 +11844a70: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12285 + :0,12283,12814,12285 +11844a80: 0000: 0000057f 00002ffd +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12286 + :0,12286,12814,12285 +11844a88: 0000: 0000057d 00002ffe +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844a90: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844a98: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 506 + VFD_INDEX_MAX: 509 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 506 +11844aa0: 0000: 00032242 000001fa 000001fd 00000000 000001fa +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844ab4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12287 + :0,12286,12814,12287 +11844abc: 0000: 0000057f 00002fff +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 105 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[105] register values +!+ 00002ffe CP_SCRATCH_REG5: 12286 + :0,12286,12814,12287 +!+ 00002fff CP_SCRATCH_REG7: 12287 + :0,12286,12814,12287 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001fa VFD_INDEX_MIN: 506 +!+ 000001fd VFD_INDEX_MAX: 509 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001fa VFD_INDEX_OFFSET: 506 +11844ac4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12288 + :0,12286,12814,12288 +11844ad4: 0000: 0000057f 00003000 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12289 + :0,12289,12814,12288 +11844adc: 0000: 0000057d 00003001 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844ae4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844aec: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 510 + VFD_INDEX_MAX: 516 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 510 +11844af4: 0000: 00032242 000001fe 00000204 00000000 000001fe +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844b08: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12290 + :0,12289,12814,12290 +11844b10: 0000: 0000057f 00003002 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 106 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[106] register values +!+ 00003001 CP_SCRATCH_REG5: 12289 + :0,12289,12814,12290 +!+ 00003002 CP_SCRATCH_REG7: 12290 + :0,12289,12814,12290 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000001fe VFD_INDEX_MIN: 510 +!+ 00000204 VFD_INDEX_MAX: 516 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000001fe VFD_INDEX_OFFSET: 510 +11844b18: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12291 + :0,12289,12814,12291 +11844b28: 0000: 0000057f 00003003 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12292 + :0,12292,12814,12291 +11844b30: 0000: 0000057d 00003004 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844b38: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844b40: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 517 + VFD_INDEX_MAX: 520 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 517 +11844b48: 0000: 00032242 00000205 00000208 00000000 00000205 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844b5c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12293 + :0,12292,12814,12293 +11844b64: 0000: 0000057f 00003005 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 107 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[107] register values +!+ 00003004 CP_SCRATCH_REG5: 12292 + :0,12292,12814,12293 +!+ 00003005 CP_SCRATCH_REG7: 12293 + :0,12292,12814,12293 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000205 VFD_INDEX_MIN: 517 +!+ 00000208 VFD_INDEX_MAX: 520 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000205 VFD_INDEX_OFFSET: 517 +11844b6c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12294 + :0,12292,12814,12294 +11844b7c: 0000: 0000057f 00003006 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12295 + :0,12295,12814,12294 +11844b84: 0000: 0000057d 00003007 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844b8c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844b94: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 521 + VFD_INDEX_MAX: 527 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 521 +11844b9c: 0000: 00032242 00000209 0000020f 00000000 00000209 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844bb0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12296 + :0,12295,12814,12296 +11844bb8: 0000: 0000057f 00003008 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 108 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[108] register values +!+ 00003007 CP_SCRATCH_REG5: 12295 + :0,12295,12814,12296 +!+ 00003008 CP_SCRATCH_REG7: 12296 + :0,12295,12814,12296 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000209 VFD_INDEX_MIN: 521 +!+ 0000020f VFD_INDEX_MAX: 527 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000209 VFD_INDEX_OFFSET: 521 +11844bc0: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12297 + :0,12295,12814,12297 +11844bd0: 0000: 0000057f 00003009 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12298 + :0,12298,12814,12297 +11844bd8: 0000: 0000057d 0000300a +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844be0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844be8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 528 + VFD_INDEX_MAX: 531 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 528 +11844bf0: 0000: 00032242 00000210 00000213 00000000 00000210 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844c04: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12299 + :0,12298,12814,12299 +11844c0c: 0000: 0000057f 0000300b +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 109 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[109] register values +!+ 0000300a CP_SCRATCH_REG5: 12298 + :0,12298,12814,12299 +!+ 0000300b CP_SCRATCH_REG7: 12299 + :0,12298,12814,12299 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000210 VFD_INDEX_MIN: 528 +!+ 00000213 VFD_INDEX_MAX: 531 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000210 VFD_INDEX_OFFSET: 528 +11844c14: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12300 + :0,12298,12814,12300 +11844c24: 0000: 0000057f 0000300c +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12301 + :0,12301,12814,12300 +11844c2c: 0000: 0000057d 0000300d +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844c34: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844c3c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 532 + VFD_INDEX_MAX: 535 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 532 +11844c44: 0000: 00032242 00000214 00000217 00000000 00000214 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844c58: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12302 + :0,12301,12814,12302 +11844c60: 0000: 0000057f 0000300e +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 110 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[110] register values +!+ 0000300d CP_SCRATCH_REG5: 12301 + :0,12301,12814,12302 +!+ 0000300e CP_SCRATCH_REG7: 12302 + :0,12301,12814,12302 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000214 VFD_INDEX_MIN: 532 +!+ 00000217 VFD_INDEX_MAX: 535 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000214 VFD_INDEX_OFFSET: 532 +11844c68: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12303 + :0,12301,12814,12303 +11844c78: 0000: 0000057f 0000300f +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12304 + :0,12304,12814,12303 +11844c80: 0000: 0000057d 00003010 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844c88: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844c90: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 536 + VFD_INDEX_MAX: 539 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 536 +11844c98: 0000: 00032242 00000218 0000021b 00000000 00000218 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844cac: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12305 + :0,12304,12814,12305 +11844cb4: 0000: 0000057f 00003011 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 111 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[111] register values +!+ 00003010 CP_SCRATCH_REG5: 12304 + :0,12304,12814,12305 +!+ 00003011 CP_SCRATCH_REG7: 12305 + :0,12304,12814,12305 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000218 VFD_INDEX_MIN: 536 +!+ 0000021b VFD_INDEX_MAX: 539 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000218 VFD_INDEX_OFFSET: 536 +11844cbc: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12306 + :0,12304,12814,12306 +11844ccc: 0000: 0000057f 00003012 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12307 + :0,12307,12814,12306 +11844cd4: 0000: 0000057d 00003013 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844cdc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844ce4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 540 + VFD_INDEX_MAX: 543 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 540 +11844cec: 0000: 00032242 0000021c 0000021f 00000000 0000021c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844d00: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12308 + :0,12307,12814,12308 +11844d08: 0000: 0000057f 00003014 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 112 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[112] register values +!+ 00003013 CP_SCRATCH_REG5: 12307 + :0,12307,12814,12308 +!+ 00003014 CP_SCRATCH_REG7: 12308 + :0,12307,12814,12308 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000021c VFD_INDEX_MIN: 540 +!+ 0000021f VFD_INDEX_MAX: 543 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000021c VFD_INDEX_OFFSET: 540 +11844d10: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12309 + :0,12307,12814,12309 +11844d20: 0000: 0000057f 00003015 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12310 + :0,12310,12814,12309 +11844d28: 0000: 0000057d 00003016 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844d30: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844d38: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 544 + VFD_INDEX_MAX: 550 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 544 +11844d40: 0000: 00032242 00000220 00000226 00000000 00000220 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844d54: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12311 + :0,12310,12814,12311 +11844d5c: 0000: 0000057f 00003017 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 113 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[113] register values +!+ 00003016 CP_SCRATCH_REG5: 12310 + :0,12310,12814,12311 +!+ 00003017 CP_SCRATCH_REG7: 12311 + :0,12310,12814,12311 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000220 VFD_INDEX_MIN: 544 +!+ 00000226 VFD_INDEX_MAX: 550 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000220 VFD_INDEX_OFFSET: 544 +11844d64: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12312 + :0,12310,12814,12312 +11844d74: 0000: 0000057f 00003018 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12313 + :0,12313,12814,12312 +11844d7c: 0000: 0000057d 00003019 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844d84: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844d8c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 551 + VFD_INDEX_MAX: 554 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 551 +11844d94: 0000: 00032242 00000227 0000022a 00000000 00000227 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844da8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12314 + :0,12313,12814,12314 +11844db0: 0000: 0000057f 0000301a +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 114 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[114] register values +!+ 00003019 CP_SCRATCH_REG5: 12313 + :0,12313,12814,12314 +!+ 0000301a CP_SCRATCH_REG7: 12314 + :0,12313,12814,12314 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000227 VFD_INDEX_MIN: 551 +!+ 0000022a VFD_INDEX_MAX: 554 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000227 VFD_INDEX_OFFSET: 551 +11844db8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12315 + :0,12313,12814,12315 +11844dc8: 0000: 0000057f 0000301b +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12316 + :0,12316,12814,12315 +11844dd0: 0000: 0000057d 0000301c +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844dd8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844de0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 555 + VFD_INDEX_MAX: 561 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 555 +11844de8: 0000: 00032242 0000022b 00000231 00000000 0000022b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844dfc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12317 + :0,12316,12814,12317 +11844e04: 0000: 0000057f 0000301d +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 115 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[115] register values +!+ 0000301c CP_SCRATCH_REG5: 12316 + :0,12316,12814,12317 +!+ 0000301d CP_SCRATCH_REG7: 12317 + :0,12316,12814,12317 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000022b VFD_INDEX_MIN: 555 +!+ 00000231 VFD_INDEX_MAX: 561 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000022b VFD_INDEX_OFFSET: 555 +11844e0c: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12318 + :0,12316,12814,12318 +11844e1c: 0000: 0000057f 0000301e +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12319 + :0,12319,12814,12318 +11844e24: 0000: 0000057d 0000301f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844e2c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844e34: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 562 + VFD_INDEX_MAX: 565 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 562 +11844e3c: 0000: 00032242 00000232 00000235 00000000 00000232 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844e50: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12320 + :0,12319,12814,12320 +11844e58: 0000: 0000057f 00003020 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 116 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[116] register values +!+ 0000301f CP_SCRATCH_REG5: 12319 + :0,12319,12814,12320 +!+ 00003020 CP_SCRATCH_REG7: 12320 + :0,12319,12814,12320 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000232 VFD_INDEX_MIN: 562 +!+ 00000235 VFD_INDEX_MAX: 565 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000232 VFD_INDEX_OFFSET: 562 +11844e60: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12321 + :0,12319,12814,12321 +11844e70: 0000: 0000057f 00003021 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12322 + :0,12322,12814,12321 +11844e78: 0000: 0000057d 00003022 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844e80: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844e88: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 566 + VFD_INDEX_MAX: 569 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 566 +11844e90: 0000: 00032242 00000236 00000239 00000000 00000236 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844ea4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12323 + :0,12322,12814,12323 +11844eac: 0000: 0000057f 00003023 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 117 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[117] register values +!+ 00003022 CP_SCRATCH_REG5: 12322 + :0,12322,12814,12323 +!+ 00003023 CP_SCRATCH_REG7: 12323 + :0,12322,12814,12323 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000236 VFD_INDEX_MIN: 566 +!+ 00000239 VFD_INDEX_MAX: 569 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000236 VFD_INDEX_OFFSET: 566 +11844eb4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12324 + :0,12322,12814,12324 +11844ec4: 0000: 0000057f 00003024 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12325 + :0,12325,12814,12324 +11844ecc: 0000: 0000057d 00003025 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844ed4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844edc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 570 + VFD_INDEX_MAX: 573 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 570 +11844ee4: 0000: 00032242 0000023a 0000023d 00000000 0000023a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844ef8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12326 + :0,12325,12814,12326 +11844f00: 0000: 0000057f 00003026 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 118 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[118] register values +!+ 00003025 CP_SCRATCH_REG5: 12325 + :0,12325,12814,12326 +!+ 00003026 CP_SCRATCH_REG7: 12326 + :0,12325,12814,12326 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000023a VFD_INDEX_MIN: 570 +!+ 0000023d VFD_INDEX_MAX: 573 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000023a VFD_INDEX_OFFSET: 570 +11844f08: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12327 + :0,12325,12814,12327 +11844f18: 0000: 0000057f 00003027 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12328 + :0,12328,12814,12327 +11844f20: 0000: 0000057d 00003028 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844f28: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844f30: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 574 + VFD_INDEX_MAX: 577 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 574 +11844f38: 0000: 00032242 0000023e 00000241 00000000 0000023e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844f4c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12329 + :0,12328,12814,12329 +11844f54: 0000: 0000057f 00003029 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 119 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[119] register values +!+ 00003028 CP_SCRATCH_REG5: 12328 + :0,12328,12814,12329 +!+ 00003029 CP_SCRATCH_REG7: 12329 + :0,12328,12814,12329 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000023e VFD_INDEX_MIN: 574 +!+ 00000241 VFD_INDEX_MAX: 577 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000023e VFD_INDEX_OFFSET: 574 +11844f5c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12330 + :0,12328,12814,12330 +11844f6c: 0000: 0000057f 0000302a +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12331 + :0,12331,12814,12330 +11844f74: 0000: 0000057d 0000302b +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844f7c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844f84: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 578 + VFD_INDEX_MAX: 584 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 578 +11844f8c: 0000: 00032242 00000242 00000248 00000000 00000242 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844fa0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12332 + :0,12331,12814,12332 +11844fa8: 0000: 0000057f 0000302c +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 120 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[120] register values +!+ 0000302b CP_SCRATCH_REG5: 12331 + :0,12331,12814,12332 +!+ 0000302c CP_SCRATCH_REG7: 12332 + :0,12331,12814,12332 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000242 VFD_INDEX_MIN: 578 +!+ 00000248 VFD_INDEX_MAX: 584 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000242 VFD_INDEX_OFFSET: 578 +11844fb0: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12333 + :0,12331,12814,12333 +11844fc0: 0000: 0000057f 0000302d +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12334 + :0,12334,12814,12333 +11844fc8: 0000: 0000057d 0000302e +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11844fd0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11844fd8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 585 + VFD_INDEX_MAX: 588 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 585 +11844fe0: 0000: 00032242 00000249 0000024c 00000000 00000249 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11844ff4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12335 + :0,12334,12814,12335 +11844ffc: 0000: 0000057f 0000302f +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 121 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[121] register values +!+ 0000302e CP_SCRATCH_REG5: 12334 + :0,12334,12814,12335 +!+ 0000302f CP_SCRATCH_REG7: 12335 + :0,12334,12814,12335 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000249 VFD_INDEX_MIN: 585 +!+ 0000024c VFD_INDEX_MAX: 588 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000249 VFD_INDEX_OFFSET: 585 +11845004: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12336 + :0,12334,12814,12336 +11845014: 0000: 0000057f 00003030 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12337 + :0,12337,12814,12336 +1184501c: 0000: 0000057d 00003031 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845024: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184502c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 589 + VFD_INDEX_MAX: 595 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 589 +11845034: 0000: 00032242 0000024d 00000253 00000000 0000024d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845048: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12338 + :0,12337,12814,12338 +11845050: 0000: 0000057f 00003032 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 122 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[122] register values +!+ 00003031 CP_SCRATCH_REG5: 12337 + :0,12337,12814,12338 +!+ 00003032 CP_SCRATCH_REG7: 12338 + :0,12337,12814,12338 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000024d VFD_INDEX_MIN: 589 +!+ 00000253 VFD_INDEX_MAX: 595 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000024d VFD_INDEX_OFFSET: 589 +11845058: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12339 + :0,12337,12814,12339 +11845068: 0000: 0000057f 00003033 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12340 + :0,12340,12814,12339 +11845070: 0000: 0000057d 00003034 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845078: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845080: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 596 + VFD_INDEX_MAX: 599 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 596 +11845088: 0000: 00032242 00000254 00000257 00000000 00000254 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184509c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12341 + :0,12340,12814,12341 +118450a4: 0000: 0000057f 00003035 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 123 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[123] register values +!+ 00003034 CP_SCRATCH_REG5: 12340 + :0,12340,12814,12341 +!+ 00003035 CP_SCRATCH_REG7: 12341 + :0,12340,12814,12341 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000254 VFD_INDEX_MIN: 596 +!+ 00000257 VFD_INDEX_MAX: 599 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000254 VFD_INDEX_OFFSET: 596 +118450ac: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12342 + :0,12340,12814,12342 +118450bc: 0000: 0000057f 00003036 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12343 + :0,12343,12814,12342 +118450c4: 0000: 0000057d 00003037 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118450cc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118450d4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 600 + VFD_INDEX_MAX: 603 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 600 +118450dc: 0000: 00032242 00000258 0000025b 00000000 00000258 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118450f0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12344 + :0,12343,12814,12344 +118450f8: 0000: 0000057f 00003038 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 124 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[124] register values +!+ 00003037 CP_SCRATCH_REG5: 12343 + :0,12343,12814,12344 +!+ 00003038 CP_SCRATCH_REG7: 12344 + :0,12343,12814,12344 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000258 VFD_INDEX_MIN: 600 +!+ 0000025b VFD_INDEX_MAX: 603 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000258 VFD_INDEX_OFFSET: 600 +11845100: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12345 + :0,12343,12814,12345 +11845110: 0000: 0000057f 00003039 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12346 + :0,12346,12814,12345 +11845118: 0000: 0000057d 0000303a +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845120: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845128: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 604 + VFD_INDEX_MAX: 607 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 604 +11845130: 0000: 00032242 0000025c 0000025f 00000000 0000025c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845144: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12347 + :0,12346,12814,12347 +1184514c: 0000: 0000057f 0000303b +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 125 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[125] register values +!+ 0000303a CP_SCRATCH_REG5: 12346 + :0,12346,12814,12347 +!+ 0000303b CP_SCRATCH_REG7: 12347 + :0,12346,12814,12347 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000025c VFD_INDEX_MIN: 604 +!+ 0000025f VFD_INDEX_MAX: 607 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000025c VFD_INDEX_OFFSET: 604 +11845154: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12348 + :0,12346,12814,12348 +11845164: 0000: 0000057f 0000303c +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12349 + :0,12349,12814,12348 +1184516c: 0000: 0000057d 0000303d +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845174: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184517c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 608 + VFD_INDEX_MAX: 611 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 608 +11845184: 0000: 00032242 00000260 00000263 00000000 00000260 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845198: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12350 + :0,12349,12814,12350 +118451a0: 0000: 0000057f 0000303e +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 126 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[126] register values +!+ 0000303d CP_SCRATCH_REG5: 12349 + :0,12349,12814,12350 +!+ 0000303e CP_SCRATCH_REG7: 12350 + :0,12349,12814,12350 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000260 VFD_INDEX_MIN: 608 +!+ 00000263 VFD_INDEX_MAX: 611 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000260 VFD_INDEX_OFFSET: 608 +118451a8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12351 + :0,12349,12814,12351 +118451b8: 0000: 0000057f 0000303f +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12352 + :0,12352,12814,12351 +118451c0: 0000: 0000057d 00003040 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118451c8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118451d0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 612 + VFD_INDEX_MAX: 618 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 612 +118451d8: 0000: 00032242 00000264 0000026a 00000000 00000264 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118451ec: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12353 + :0,12352,12814,12353 +118451f4: 0000: 0000057f 00003041 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 127 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[127] register values +!+ 00003040 CP_SCRATCH_REG5: 12352 + :0,12352,12814,12353 +!+ 00003041 CP_SCRATCH_REG7: 12353 + :0,12352,12814,12353 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000264 VFD_INDEX_MIN: 612 +!+ 0000026a VFD_INDEX_MAX: 618 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000264 VFD_INDEX_OFFSET: 612 +118451fc: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12354 + :0,12352,12814,12354 +1184520c: 0000: 0000057f 00003042 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12355 + :0,12355,12814,12354 +11845214: 0000: 0000057d 00003043 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184521c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845224: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 619 + VFD_INDEX_MAX: 622 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 619 +1184522c: 0000: 00032242 0000026b 0000026e 00000000 0000026b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845240: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12356 + :0,12355,12814,12356 +11845248: 0000: 0000057f 00003044 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 128 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[128] register values +!+ 00003043 CP_SCRATCH_REG5: 12355 + :0,12355,12814,12356 +!+ 00003044 CP_SCRATCH_REG7: 12356 + :0,12355,12814,12356 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000026b VFD_INDEX_MIN: 619 +!+ 0000026e VFD_INDEX_MAX: 622 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000026b VFD_INDEX_OFFSET: 619 +11845250: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12357 + :0,12355,12814,12357 +11845260: 0000: 0000057f 00003045 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12358 + :0,12358,12814,12357 +11845268: 0000: 0000057d 00003046 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845270: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845278: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 623 + VFD_INDEX_MAX: 629 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 623 +11845280: 0000: 00032242 0000026f 00000275 00000000 0000026f +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845294: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12359 + :0,12358,12814,12359 +1184529c: 0000: 0000057f 00003047 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 129 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[129] register values +!+ 00003046 CP_SCRATCH_REG5: 12358 + :0,12358,12814,12359 +!+ 00003047 CP_SCRATCH_REG7: 12359 + :0,12358,12814,12359 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000026f VFD_INDEX_MIN: 623 +!+ 00000275 VFD_INDEX_MAX: 629 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000026f VFD_INDEX_OFFSET: 623 +118452a4: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12360 + :0,12358,12814,12360 +118452b4: 0000: 0000057f 00003048 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12361 + :0,12361,12814,12360 +118452bc: 0000: 0000057d 00003049 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118452c4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118452cc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 630 + VFD_INDEX_MAX: 633 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 630 +118452d4: 0000: 00032242 00000276 00000279 00000000 00000276 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118452e8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12362 + :0,12361,12814,12362 +118452f0: 0000: 0000057f 0000304a +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 130 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[130] register values +!+ 00003049 CP_SCRATCH_REG5: 12361 + :0,12361,12814,12362 +!+ 0000304a CP_SCRATCH_REG7: 12362 + :0,12361,12814,12362 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000276 VFD_INDEX_MIN: 630 +!+ 00000279 VFD_INDEX_MAX: 633 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000276 VFD_INDEX_OFFSET: 630 +118452f8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12363 + :0,12361,12814,12363 +11845308: 0000: 0000057f 0000304b +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12364 + :0,12364,12814,12363 +11845310: 0000: 0000057d 0000304c +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845318: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845320: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 634 + VFD_INDEX_MAX: 637 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 634 +11845328: 0000: 00032242 0000027a 0000027d 00000000 0000027a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184533c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12365 + :0,12364,12814,12365 +11845344: 0000: 0000057f 0000304d +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 131 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[131] register values +!+ 0000304c CP_SCRATCH_REG5: 12364 + :0,12364,12814,12365 +!+ 0000304d CP_SCRATCH_REG7: 12365 + :0,12364,12814,12365 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000027a VFD_INDEX_MIN: 634 +!+ 0000027d VFD_INDEX_MAX: 637 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000027a VFD_INDEX_OFFSET: 634 +1184534c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12366 + :0,12364,12814,12366 +1184535c: 0000: 0000057f 0000304e +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12367 + :0,12367,12814,12366 +11845364: 0000: 0000057d 0000304f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184536c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845374: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 638 + VFD_INDEX_MAX: 641 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 638 +1184537c: 0000: 00032242 0000027e 00000281 00000000 0000027e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845390: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12368 + :0,12367,12814,12368 +11845398: 0000: 0000057f 00003050 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 132 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[132] register values +!+ 0000304f CP_SCRATCH_REG5: 12367 + :0,12367,12814,12368 +!+ 00003050 CP_SCRATCH_REG7: 12368 + :0,12367,12814,12368 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000027e VFD_INDEX_MIN: 638 +!+ 00000281 VFD_INDEX_MAX: 641 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000027e VFD_INDEX_OFFSET: 638 +118453a0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12369 + :0,12367,12814,12369 +118453b0: 0000: 0000057f 00003051 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12370 + :0,12370,12814,12369 +118453b8: 0000: 0000057d 00003052 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118453c0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118453c8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 642 + VFD_INDEX_MAX: 645 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 642 +118453d0: 0000: 00032242 00000282 00000285 00000000 00000282 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118453e4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12371 + :0,12370,12814,12371 +118453ec: 0000: 0000057f 00003053 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 133 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[133] register values +!+ 00003052 CP_SCRATCH_REG5: 12370 + :0,12370,12814,12371 +!+ 00003053 CP_SCRATCH_REG7: 12371 + :0,12370,12814,12371 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000282 VFD_INDEX_MIN: 642 +!+ 00000285 VFD_INDEX_MAX: 645 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000282 VFD_INDEX_OFFSET: 642 +118453f4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12372 + :0,12370,12814,12372 +11845404: 0000: 0000057f 00003054 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12373 + :0,12373,12814,12372 +1184540c: 0000: 0000057d 00003055 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845414: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184541c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 646 + VFD_INDEX_MAX: 652 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 646 +11845424: 0000: 00032242 00000286 0000028c 00000000 00000286 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845438: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12374 + :0,12373,12814,12374 +11845440: 0000: 0000057f 00003056 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 134 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[134] register values +!+ 00003055 CP_SCRATCH_REG5: 12373 + :0,12373,12814,12374 +!+ 00003056 CP_SCRATCH_REG7: 12374 + :0,12373,12814,12374 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000286 VFD_INDEX_MIN: 646 +!+ 0000028c VFD_INDEX_MAX: 652 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000286 VFD_INDEX_OFFSET: 646 +11845448: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12375 + :0,12373,12814,12375 +11845458: 0000: 0000057f 00003057 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12376 + :0,12376,12814,12375 +11845460: 0000: 0000057d 00003058 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845468: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845470: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 653 + VFD_INDEX_MAX: 656 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 653 +11845478: 0000: 00032242 0000028d 00000290 00000000 0000028d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184548c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12377 + :0,12376,12814,12377 +11845494: 0000: 0000057f 00003059 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 135 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[135] register values +!+ 00003058 CP_SCRATCH_REG5: 12376 + :0,12376,12814,12377 +!+ 00003059 CP_SCRATCH_REG7: 12377 + :0,12376,12814,12377 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000028d VFD_INDEX_MIN: 653 +!+ 00000290 VFD_INDEX_MAX: 656 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000028d VFD_INDEX_OFFSET: 653 +1184549c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12378 + :0,12376,12814,12378 +118454ac: 0000: 0000057f 0000305a +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12379 + :0,12379,12814,12378 +118454b4: 0000: 0000057d 0000305b +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118454bc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118454c4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 657 + VFD_INDEX_MAX: 663 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 657 +118454cc: 0000: 00032242 00000291 00000297 00000000 00000291 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118454e0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12380 + :0,12379,12814,12380 +118454e8: 0000: 0000057f 0000305c +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 136 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[136] register values +!+ 0000305b CP_SCRATCH_REG5: 12379 + :0,12379,12814,12380 +!+ 0000305c CP_SCRATCH_REG7: 12380 + :0,12379,12814,12380 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000291 VFD_INDEX_MIN: 657 +!+ 00000297 VFD_INDEX_MAX: 663 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000291 VFD_INDEX_OFFSET: 657 +118454f0: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12381 + :0,12379,12814,12381 +11845500: 0000: 0000057f 0000305d +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12382 + :0,12382,12814,12381 +11845508: 0000: 0000057d 0000305e +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845510: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845518: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 664 + VFD_INDEX_MAX: 667 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 664 +11845520: 0000: 00032242 00000298 0000029b 00000000 00000298 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845534: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12383 + :0,12382,12814,12383 +1184553c: 0000: 0000057f 0000305f +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 137 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[137] register values +!+ 0000305e CP_SCRATCH_REG5: 12382 + :0,12382,12814,12383 +!+ 0000305f CP_SCRATCH_REG7: 12383 + :0,12382,12814,12383 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000298 VFD_INDEX_MIN: 664 +!+ 0000029b VFD_INDEX_MAX: 667 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000298 VFD_INDEX_OFFSET: 664 +11845544: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12384 + :0,12382,12814,12384 +11845554: 0000: 0000057f 00003060 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12385 + :0,12385,12814,12384 +1184555c: 0000: 0000057d 00003061 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845564: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184556c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 668 + VFD_INDEX_MAX: 671 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 668 +11845574: 0000: 00032242 0000029c 0000029f 00000000 0000029c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845588: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12386 + :0,12385,12814,12386 +11845590: 0000: 0000057f 00003062 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 138 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[138] register values +!+ 00003061 CP_SCRATCH_REG5: 12385 + :0,12385,12814,12386 +!+ 00003062 CP_SCRATCH_REG7: 12386 + :0,12385,12814,12386 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000029c VFD_INDEX_MIN: 668 +!+ 0000029f VFD_INDEX_MAX: 671 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000029c VFD_INDEX_OFFSET: 668 +11845598: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12387 + :0,12385,12814,12387 +118455a8: 0000: 0000057f 00003063 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12388 + :0,12388,12814,12387 +118455b0: 0000: 0000057d 00003064 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118455b8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118455c0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 672 + VFD_INDEX_MAX: 675 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 672 +118455c8: 0000: 00032242 000002a0 000002a3 00000000 000002a0 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118455dc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12389 + :0,12388,12814,12389 +118455e4: 0000: 0000057f 00003065 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 139 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[139] register values +!+ 00003064 CP_SCRATCH_REG5: 12388 + :0,12388,12814,12389 +!+ 00003065 CP_SCRATCH_REG7: 12389 + :0,12388,12814,12389 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000002a0 VFD_INDEX_MIN: 672 +!+ 000002a3 VFD_INDEX_MAX: 675 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000002a0 VFD_INDEX_OFFSET: 672 +118455ec: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12390 + :0,12388,12814,12390 +118455fc: 0000: 0000057f 00003066 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12391 + :0,12391,12814,12390 +11845604: 0000: 0000057d 00003067 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184560c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845614: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 676 + VFD_INDEX_MAX: 679 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 676 +1184561c: 0000: 00032242 000002a4 000002a7 00000000 000002a4 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845630: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12392 + :0,12391,12814,12392 +11845638: 0000: 0000057f 00003068 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 140 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[140] register values +!+ 00003067 CP_SCRATCH_REG5: 12391 + :0,12391,12814,12392 +!+ 00003068 CP_SCRATCH_REG7: 12392 + :0,12391,12814,12392 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000002a4 VFD_INDEX_MIN: 676 +!+ 000002a7 VFD_INDEX_MAX: 679 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000002a4 VFD_INDEX_OFFSET: 676 +11845640: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12393 + :0,12391,12814,12393 +11845650: 0000: 0000057f 00003069 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12394 + :0,12394,12814,12393 +11845658: 0000: 0000057d 0000306a +t0 write UCHE_CACHE_INVALIDATE0_REG (0ea0) +NEEDS WFI: UCHE_CACHE_INVALIDATE0_REG (ea0) + UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 } +NEEDS WFI: UCHE_CACHE_INVALIDATE1_REG (ea1) + UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE } +11845660: 0000: 00010ea0 00000000 90000000 +t3 opcode: CP_LOAD_STATE (30) (43 dwords) + { DST_OFF = 0 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 20 } + { STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 } +11845678: 1.462840 -0.071177 0.534908 0.533864 0.331812 1.652796 -0.230062 -0.229613 +11845698: 0.866025 -0.513030 -0.815389 -0.813798 4.650000 -2.336977 20.181894 22.140564 +118456b8: 0.844571 -0.041094 -0.533864 -14.142904 0.191572 0.954242 0.229613 5.856975 +118456d8: 0.500000 -0.296198 0.813798 16.275953 0.000000 0.000000 0.000000 1.000000 +118456f8: 5.000000 5.000000 10.000000 1.000000 0.000000 0.800000 0.200000 1.000000 +11845678: 0000: 3fbb3e57 bd91c539 3f08efbb 3f08ab54 3ea9e347 3fd38ecf be6b956f be6b1fc2 +11845698: 0020: 3f5db3d7 bf0355f2 bf50bd50 bf50550b 4094cccc c0159107 41a17485 41b11fe0 +118456b8: 0040: 3f5835cf bd285238 bf08ab54 c1624956 3e442b67 3f744935 3e6b1fc2 40bb6c57 +118456d8: 0060: 3f000000 be97a747 3f50550b 41823527 00000000 00000000 00000000 3f800000 +118456f8: 0080: 40a00000 40a00000 41200000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 +1184566c: 0000: c0293000 05200000 00000001 3fbb3e57 bd91c539 3f08efbb 3f08ab54 3ea9e347 +1184568c: 0020: 3fd38ecf be6b956f be6b1fc2 3f5db3d7 bf0355f2 bf50bd50 bf50550b 4094cccc +118456ac: 0040: c0159107 41a17485 41b11fe0 3f5835cf bd285238 bf08ab54 c1624956 3e442b67 +118456cc: 0060: 3f744935 3e6b1fc2 40bb6c57 3f000000 be97a747 3f50550b 41823527 00000000 +118456ec: 0080: 00000000 00000000 3f800000 40a00000 40a00000 41200000 3f800000 00000000 +1184570c: 00a0: 3f4ccccd 3e4ccccd 3f800000 +t0 write UCHE_CACHE_INVALIDATE0_REG (0ea0) +NEEDS WFI: UCHE_CACHE_INVALIDATE0_REG (ea0) + UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 } +NEEDS WFI: UCHE_CACHE_INVALIDATE1_REG (ea1) + UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE } +11845718: 0000: 00010ea0 00000000 90000000 +t3 opcode: CP_LOAD_STATE (30) (7 dwords) + { DST_OFF = 20 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 2 } + { STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 } +11845730: 0.000000 0.000000 0.000000 0.000000 +11845730: 0000: 00000000 00000000 00000000 00000000 +11845724: 0000: c0053000 00a00014 00000001 00000000 00000000 00000000 00000000 +t0 write VFD_FETCH[0].INSTR_0 (2246) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT | INDEXCODE = 0 | STEPRATE = 1 } + VFD_FETCH[0].INSTR_1: 0x127ee000 +11845740: 0000: 00012246 01020c0b 127ee000 +t0 write VFD_DECODE[0].INSTR (2266) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } +1184574c: 0000: 00002266 6c00009f +t0 write VFD_FETCH[0x1].INSTR_0 (2248) + VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | INDEXCODE = 1 | STEPRATE = 1 } + VFD_FETCH[0x1].INSTR_1: 0x127ee00c +11845754: 0000: 00012248 01040c0b 127ee00c +t0 write VFD_DECODE[0x1].INSTR (2267) + VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +11845760: 0000: 00002267 2c00409f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845768: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845770: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 0 + VFD_INDEX_MAX: 6 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 0 +11845778: 0000: 00032242 00000000 00000006 00000000 00000000 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184578c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12395 + :0,12394,12814,12395 +11845794: 0000: 0000057f 0000306b +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 141 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[141] register values +!+ 0000306a CP_SCRATCH_REG5: 12394 + :0,12394,12814,12395 +!+ 0000306b CP_SCRATCH_REG7: 12395 + :0,12394,12814,12395 + + 00000000 UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 } + + 90000000 UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE } + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000000 VFD_INDEX_MIN: 0 +!+ 00000006 VFD_INDEX_MAX: 6 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000000 VFD_INDEX_OFFSET: 0 + + 01020c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT | INDEXCODE = 0 | STEPRATE = 1 } +!+ 127ee000 VFD_FETCH[0].INSTR_1: 0x127ee000 + + 01040c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | INDEXCODE = 1 | STEPRATE = 1 } +!+ 127ee00c VFD_FETCH[0x1].INSTR_1: 0x127ee00c + + 6c00009f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } + + 2c00409f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +1184579c: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12396 + :0,12394,12814,12396 +118457ac: 0000: 0000057f 0000306c +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12397 + :0,12397,12814,12396 +118457b4: 0000: 0000057d 0000306d +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118457bc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118457c4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 7 + VFD_INDEX_MAX: 10 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 7 +118457cc: 0000: 00032242 00000007 0000000a 00000000 00000007 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118457e0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12398 + :0,12397,12814,12398 +118457e8: 0000: 0000057f 0000306e +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 142 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[142] register values +!+ 0000306d CP_SCRATCH_REG5: 12397 + :0,12397,12814,12398 +!+ 0000306e CP_SCRATCH_REG7: 12398 + :0,12397,12814,12398 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000007 VFD_INDEX_MIN: 7 +!+ 0000000a VFD_INDEX_MAX: 10 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000007 VFD_INDEX_OFFSET: 7 +118457f0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12399 + :0,12397,12814,12399 +11845800: 0000: 0000057f 0000306f +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12400 + :0,12400,12814,12399 +11845808: 0000: 0000057d 00003070 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845810: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845818: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 11 + VFD_INDEX_MAX: 17 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 11 +11845820: 0000: 00032242 0000000b 00000011 00000000 0000000b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845834: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12401 + :0,12400,12814,12401 +1184583c: 0000: 0000057f 00003071 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 143 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[143] register values +!+ 00003070 CP_SCRATCH_REG5: 12400 + :0,12400,12814,12401 +!+ 00003071 CP_SCRATCH_REG7: 12401 + :0,12400,12814,12401 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000000b VFD_INDEX_MIN: 11 +!+ 00000011 VFD_INDEX_MAX: 17 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000000b VFD_INDEX_OFFSET: 11 +11845844: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12402 + :0,12400,12814,12402 +11845854: 0000: 0000057f 00003072 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12403 + :0,12403,12814,12402 +1184585c: 0000: 0000057d 00003073 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845864: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184586c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 18 + VFD_INDEX_MAX: 21 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 18 +11845874: 0000: 00032242 00000012 00000015 00000000 00000012 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845888: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12404 + :0,12403,12814,12404 +11845890: 0000: 0000057f 00003074 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 144 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[144] register values +!+ 00003073 CP_SCRATCH_REG5: 12403 + :0,12403,12814,12404 +!+ 00003074 CP_SCRATCH_REG7: 12404 + :0,12403,12814,12404 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000012 VFD_INDEX_MIN: 18 +!+ 00000015 VFD_INDEX_MAX: 21 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000012 VFD_INDEX_OFFSET: 18 +11845898: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12405 + :0,12403,12814,12405 +118458a8: 0000: 0000057f 00003075 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12406 + :0,12406,12814,12405 +118458b0: 0000: 0000057d 00003076 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118458b8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118458c0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 22 + VFD_INDEX_MAX: 25 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 22 +118458c8: 0000: 00032242 00000016 00000019 00000000 00000016 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118458dc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12407 + :0,12406,12814,12407 +118458e4: 0000: 0000057f 00003077 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 145 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[145] register values +!+ 00003076 CP_SCRATCH_REG5: 12406 + :0,12406,12814,12407 +!+ 00003077 CP_SCRATCH_REG7: 12407 + :0,12406,12814,12407 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000016 VFD_INDEX_MIN: 22 +!+ 00000019 VFD_INDEX_MAX: 25 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000016 VFD_INDEX_OFFSET: 22 +118458ec: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12408 + :0,12406,12814,12408 +118458fc: 0000: 0000057f 00003078 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12409 + :0,12409,12814,12408 +11845904: 0000: 0000057d 00003079 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184590c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845914: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 26 + VFD_INDEX_MAX: 29 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 26 +1184591c: 0000: 00032242 0000001a 0000001d 00000000 0000001a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845930: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12410 + :0,12409,12814,12410 +11845938: 0000: 0000057f 0000307a +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 146 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[146] register values +!+ 00003079 CP_SCRATCH_REG5: 12409 + :0,12409,12814,12410 +!+ 0000307a CP_SCRATCH_REG7: 12410 + :0,12409,12814,12410 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000001a VFD_INDEX_MIN: 26 +!+ 0000001d VFD_INDEX_MAX: 29 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000001a VFD_INDEX_OFFSET: 26 +11845940: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12411 + :0,12409,12814,12411 +11845950: 0000: 0000057f 0000307b +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12412 + :0,12412,12814,12411 +11845958: 0000: 0000057d 0000307c +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845960: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845968: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 30 + VFD_INDEX_MAX: 33 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 30 +11845970: 0000: 00032242 0000001e 00000021 00000000 0000001e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845984: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12413 + :0,12412,12814,12413 +1184598c: 0000: 0000057f 0000307d +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 147 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[147] register values +!+ 0000307c CP_SCRATCH_REG5: 12412 + :0,12412,12814,12413 +!+ 0000307d CP_SCRATCH_REG7: 12413 + :0,12412,12814,12413 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000001e VFD_INDEX_MIN: 30 +!+ 00000021 VFD_INDEX_MAX: 33 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000001e VFD_INDEX_OFFSET: 30 +11845994: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12414 + :0,12412,12814,12414 +118459a4: 0000: 0000057f 0000307e +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12415 + :0,12415,12814,12414 +118459ac: 0000: 0000057d 0000307f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118459b4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118459bc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 34 + VFD_INDEX_MAX: 40 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 34 +118459c4: 0000: 00032242 00000022 00000028 00000000 00000022 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118459d8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12416 + :0,12415,12814,12416 +118459e0: 0000: 0000057f 00003080 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 148 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[148] register values +!+ 0000307f CP_SCRATCH_REG5: 12415 + :0,12415,12814,12416 +!+ 00003080 CP_SCRATCH_REG7: 12416 + :0,12415,12814,12416 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000022 VFD_INDEX_MIN: 34 +!+ 00000028 VFD_INDEX_MAX: 40 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000022 VFD_INDEX_OFFSET: 34 +118459e8: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12417 + :0,12415,12814,12417 +118459f8: 0000: 0000057f 00003081 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12418 + :0,12418,12814,12417 +11845a00: 0000: 0000057d 00003082 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845a08: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845a10: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 41 + VFD_INDEX_MAX: 44 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 41 +11845a18: 0000: 00032242 00000029 0000002c 00000000 00000029 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845a2c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12419 + :0,12418,12814,12419 +11845a34: 0000: 0000057f 00003083 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 149 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[149] register values +!+ 00003082 CP_SCRATCH_REG5: 12418 + :0,12418,12814,12419 +!+ 00003083 CP_SCRATCH_REG7: 12419 + :0,12418,12814,12419 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000029 VFD_INDEX_MIN: 41 +!+ 0000002c VFD_INDEX_MAX: 44 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000029 VFD_INDEX_OFFSET: 41 +11845a3c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12420 + :0,12418,12814,12420 +11845a4c: 0000: 0000057f 00003084 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12421 + :0,12421,12814,12420 +11845a54: 0000: 0000057d 00003085 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845a5c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845a64: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 45 + VFD_INDEX_MAX: 51 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 45 +11845a6c: 0000: 00032242 0000002d 00000033 00000000 0000002d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845a80: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12422 + :0,12421,12814,12422 +11845a88: 0000: 0000057f 00003086 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 150 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[150] register values +!+ 00003085 CP_SCRATCH_REG5: 12421 + :0,12421,12814,12422 +!+ 00003086 CP_SCRATCH_REG7: 12422 + :0,12421,12814,12422 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000002d VFD_INDEX_MIN: 45 +!+ 00000033 VFD_INDEX_MAX: 51 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000002d VFD_INDEX_OFFSET: 45 +11845a90: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12423 + :0,12421,12814,12423 +11845aa0: 0000: 0000057f 00003087 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12424 + :0,12424,12814,12423 +11845aa8: 0000: 0000057d 00003088 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845ab0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845ab8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 52 + VFD_INDEX_MAX: 55 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 52 +11845ac0: 0000: 00032242 00000034 00000037 00000000 00000034 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845ad4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12425 + :0,12424,12814,12425 +11845adc: 0000: 0000057f 00003089 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 151 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[151] register values +!+ 00003088 CP_SCRATCH_REG5: 12424 + :0,12424,12814,12425 +!+ 00003089 CP_SCRATCH_REG7: 12425 + :0,12424,12814,12425 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000034 VFD_INDEX_MIN: 52 +!+ 00000037 VFD_INDEX_MAX: 55 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000034 VFD_INDEX_OFFSET: 52 +11845ae4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12426 + :0,12424,12814,12426 +11845af4: 0000: 0000057f 0000308a +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12427 + :0,12427,12814,12426 +11845afc: 0000: 0000057d 0000308b +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845b04: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845b0c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 56 + VFD_INDEX_MAX: 59 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 56 +11845b14: 0000: 00032242 00000038 0000003b 00000000 00000038 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845b28: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12428 + :0,12427,12814,12428 +11845b30: 0000: 0000057f 0000308c +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 152 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[152] register values +!+ 0000308b CP_SCRATCH_REG5: 12427 + :0,12427,12814,12428 +!+ 0000308c CP_SCRATCH_REG7: 12428 + :0,12427,12814,12428 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000038 VFD_INDEX_MIN: 56 +!+ 0000003b VFD_INDEX_MAX: 59 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000038 VFD_INDEX_OFFSET: 56 +11845b38: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12429 + :0,12427,12814,12429 +11845b48: 0000: 0000057f 0000308d +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12430 + :0,12430,12814,12429 +11845b50: 0000: 0000057d 0000308e +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845b58: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845b60: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 60 + VFD_INDEX_MAX: 63 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 60 +11845b68: 0000: 00032242 0000003c 0000003f 00000000 0000003c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845b7c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12431 + :0,12430,12814,12431 +11845b84: 0000: 0000057f 0000308f +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 153 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[153] register values +!+ 0000308e CP_SCRATCH_REG5: 12430 + :0,12430,12814,12431 +!+ 0000308f CP_SCRATCH_REG7: 12431 + :0,12430,12814,12431 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000003c VFD_INDEX_MIN: 60 +!+ 0000003f VFD_INDEX_MAX: 63 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000003c VFD_INDEX_OFFSET: 60 +11845b8c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12432 + :0,12430,12814,12432 +11845b9c: 0000: 0000057f 00003090 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12433 + :0,12433,12814,12432 +11845ba4: 0000: 0000057d 00003091 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845bac: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845bb4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 64 + VFD_INDEX_MAX: 67 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 64 +11845bbc: 0000: 00032242 00000040 00000043 00000000 00000040 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845bd0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12434 + :0,12433,12814,12434 +11845bd8: 0000: 0000057f 00003092 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 154 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[154] register values +!+ 00003091 CP_SCRATCH_REG5: 12433 + :0,12433,12814,12434 +!+ 00003092 CP_SCRATCH_REG7: 12434 + :0,12433,12814,12434 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000040 VFD_INDEX_MIN: 64 +!+ 00000043 VFD_INDEX_MAX: 67 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000040 VFD_INDEX_OFFSET: 64 +11845be0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12435 + :0,12433,12814,12435 +11845bf0: 0000: 0000057f 00003093 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12436 + :0,12436,12814,12435 +11845bf8: 0000: 0000057d 00003094 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845c00: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845c08: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 68 + VFD_INDEX_MAX: 74 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 68 +11845c10: 0000: 00032242 00000044 0000004a 00000000 00000044 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845c24: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12437 + :0,12436,12814,12437 +11845c2c: 0000: 0000057f 00003095 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 155 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[155] register values +!+ 00003094 CP_SCRATCH_REG5: 12436 + :0,12436,12814,12437 +!+ 00003095 CP_SCRATCH_REG7: 12437 + :0,12436,12814,12437 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000044 VFD_INDEX_MIN: 68 +!+ 0000004a VFD_INDEX_MAX: 74 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000044 VFD_INDEX_OFFSET: 68 +11845c34: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12438 + :0,12436,12814,12438 +11845c44: 0000: 0000057f 00003096 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12439 + :0,12439,12814,12438 +11845c4c: 0000: 0000057d 00003097 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845c54: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845c5c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 75 + VFD_INDEX_MAX: 78 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 75 +11845c64: 0000: 00032242 0000004b 0000004e 00000000 0000004b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845c78: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12440 + :0,12439,12814,12440 +11845c80: 0000: 0000057f 00003098 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 156 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[156] register values +!+ 00003097 CP_SCRATCH_REG5: 12439 + :0,12439,12814,12440 +!+ 00003098 CP_SCRATCH_REG7: 12440 + :0,12439,12814,12440 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000004b VFD_INDEX_MIN: 75 +!+ 0000004e VFD_INDEX_MAX: 78 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000004b VFD_INDEX_OFFSET: 75 +11845c88: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12441 + :0,12439,12814,12441 +11845c98: 0000: 0000057f 00003099 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12442 + :0,12442,12814,12441 +11845ca0: 0000: 0000057d 0000309a +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845ca8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845cb0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 79 + VFD_INDEX_MAX: 85 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 79 +11845cb8: 0000: 00032242 0000004f 00000055 00000000 0000004f +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845ccc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12443 + :0,12442,12814,12443 +11845cd4: 0000: 0000057f 0000309b +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 157 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[157] register values +!+ 0000309a CP_SCRATCH_REG5: 12442 + :0,12442,12814,12443 +!+ 0000309b CP_SCRATCH_REG7: 12443 + :0,12442,12814,12443 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000004f VFD_INDEX_MIN: 79 +!+ 00000055 VFD_INDEX_MAX: 85 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000004f VFD_INDEX_OFFSET: 79 +11845cdc: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12444 + :0,12442,12814,12444 +11845cec: 0000: 0000057f 0000309c +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12445 + :0,12445,12814,12444 +11845cf4: 0000: 0000057d 0000309d +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845cfc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845d04: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 86 + VFD_INDEX_MAX: 89 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 86 +11845d0c: 0000: 00032242 00000056 00000059 00000000 00000056 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845d20: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12446 + :0,12445,12814,12446 +11845d28: 0000: 0000057f 0000309e +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 158 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[158] register values +!+ 0000309d CP_SCRATCH_REG5: 12445 + :0,12445,12814,12446 +!+ 0000309e CP_SCRATCH_REG7: 12446 + :0,12445,12814,12446 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000056 VFD_INDEX_MIN: 86 +!+ 00000059 VFD_INDEX_MAX: 89 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000056 VFD_INDEX_OFFSET: 86 +11845d30: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12447 + :0,12445,12814,12447 +11845d40: 0000: 0000057f 0000309f +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12448 + :0,12448,12814,12447 +11845d48: 0000: 0000057d 000030a0 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845d50: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845d58: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 90 + VFD_INDEX_MAX: 93 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 90 +11845d60: 0000: 00032242 0000005a 0000005d 00000000 0000005a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845d74: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12449 + :0,12448,12814,12449 +11845d7c: 0000: 0000057f 000030a1 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 159 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[159] register values +!+ 000030a0 CP_SCRATCH_REG5: 12448 + :0,12448,12814,12449 +!+ 000030a1 CP_SCRATCH_REG7: 12449 + :0,12448,12814,12449 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000005a VFD_INDEX_MIN: 90 +!+ 0000005d VFD_INDEX_MAX: 93 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000005a VFD_INDEX_OFFSET: 90 +11845d84: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12450 + :0,12448,12814,12450 +11845d94: 0000: 0000057f 000030a2 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12451 + :0,12451,12814,12450 +11845d9c: 0000: 0000057d 000030a3 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845da4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845dac: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 94 + VFD_INDEX_MAX: 97 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 94 +11845db4: 0000: 00032242 0000005e 00000061 00000000 0000005e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845dc8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12452 + :0,12451,12814,12452 +11845dd0: 0000: 0000057f 000030a4 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 160 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[160] register values +!+ 000030a3 CP_SCRATCH_REG5: 12451 + :0,12451,12814,12452 +!+ 000030a4 CP_SCRATCH_REG7: 12452 + :0,12451,12814,12452 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000005e VFD_INDEX_MIN: 94 +!+ 00000061 VFD_INDEX_MAX: 97 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000005e VFD_INDEX_OFFSET: 94 +11845dd8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12453 + :0,12451,12814,12453 +11845de8: 0000: 0000057f 000030a5 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12454 + :0,12454,12814,12453 +11845df0: 0000: 0000057d 000030a6 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845df8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845e00: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 98 + VFD_INDEX_MAX: 101 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 98 +11845e08: 0000: 00032242 00000062 00000065 00000000 00000062 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845e1c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12455 + :0,12454,12814,12455 +11845e24: 0000: 0000057f 000030a7 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 161 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[161] register values +!+ 000030a6 CP_SCRATCH_REG5: 12454 + :0,12454,12814,12455 +!+ 000030a7 CP_SCRATCH_REG7: 12455 + :0,12454,12814,12455 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000062 VFD_INDEX_MIN: 98 +!+ 00000065 VFD_INDEX_MAX: 101 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000062 VFD_INDEX_OFFSET: 98 +11845e2c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12456 + :0,12454,12814,12456 +11845e3c: 0000: 0000057f 000030a8 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12457 + :0,12457,12814,12456 +11845e44: 0000: 0000057d 000030a9 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845e4c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845e54: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 102 + VFD_INDEX_MAX: 108 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 102 +11845e5c: 0000: 00032242 00000066 0000006c 00000000 00000066 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845e70: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12458 + :0,12457,12814,12458 +11845e78: 0000: 0000057f 000030aa +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 162 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[162] register values +!+ 000030a9 CP_SCRATCH_REG5: 12457 + :0,12457,12814,12458 +!+ 000030aa CP_SCRATCH_REG7: 12458 + :0,12457,12814,12458 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000066 VFD_INDEX_MIN: 102 +!+ 0000006c VFD_INDEX_MAX: 108 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000066 VFD_INDEX_OFFSET: 102 +11845e80: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12459 + :0,12457,12814,12459 +11845e90: 0000: 0000057f 000030ab +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12460 + :0,12460,12814,12459 +11845e98: 0000: 0000057d 000030ac +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845ea0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845ea8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 109 + VFD_INDEX_MAX: 112 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 109 +11845eb0: 0000: 00032242 0000006d 00000070 00000000 0000006d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845ec4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12461 + :0,12460,12814,12461 +11845ecc: 0000: 0000057f 000030ad +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 163 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[163] register values +!+ 000030ac CP_SCRATCH_REG5: 12460 + :0,12460,12814,12461 +!+ 000030ad CP_SCRATCH_REG7: 12461 + :0,12460,12814,12461 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000006d VFD_INDEX_MIN: 109 +!+ 00000070 VFD_INDEX_MAX: 112 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000006d VFD_INDEX_OFFSET: 109 +11845ed4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12462 + :0,12460,12814,12462 +11845ee4: 0000: 0000057f 000030ae +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12463 + :0,12463,12814,12462 +11845eec: 0000: 0000057d 000030af +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845ef4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845efc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 113 + VFD_INDEX_MAX: 119 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 113 +11845f04: 0000: 00032242 00000071 00000077 00000000 00000071 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845f18: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12464 + :0,12463,12814,12464 +11845f20: 0000: 0000057f 000030b0 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 164 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[164] register values +!+ 000030af CP_SCRATCH_REG5: 12463 + :0,12463,12814,12464 +!+ 000030b0 CP_SCRATCH_REG7: 12464 + :0,12463,12814,12464 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000071 VFD_INDEX_MIN: 113 +!+ 00000077 VFD_INDEX_MAX: 119 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000071 VFD_INDEX_OFFSET: 113 +11845f28: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12465 + :0,12463,12814,12465 +11845f38: 0000: 0000057f 000030b1 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12466 + :0,12466,12814,12465 +11845f40: 0000: 0000057d 000030b2 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845f48: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845f50: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 120 + VFD_INDEX_MAX: 123 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 120 +11845f58: 0000: 00032242 00000078 0000007b 00000000 00000078 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845f6c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12467 + :0,12466,12814,12467 +11845f74: 0000: 0000057f 000030b3 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 165 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[165] register values +!+ 000030b2 CP_SCRATCH_REG5: 12466 + :0,12466,12814,12467 +!+ 000030b3 CP_SCRATCH_REG7: 12467 + :0,12466,12814,12467 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000078 VFD_INDEX_MIN: 120 +!+ 0000007b VFD_INDEX_MAX: 123 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000078 VFD_INDEX_OFFSET: 120 +11845f7c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12468 + :0,12466,12814,12468 +11845f8c: 0000: 0000057f 000030b4 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12469 + :0,12469,12814,12468 +11845f94: 0000: 0000057d 000030b5 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845f9c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845fa4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 124 + VFD_INDEX_MAX: 127 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 124 +11845fac: 0000: 00032242 0000007c 0000007f 00000000 0000007c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11845fc0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12470 + :0,12469,12814,12470 +11845fc8: 0000: 0000057f 000030b6 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 166 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[166] register values +!+ 000030b5 CP_SCRATCH_REG5: 12469 + :0,12469,12814,12470 +!+ 000030b6 CP_SCRATCH_REG7: 12470 + :0,12469,12814,12470 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000007c VFD_INDEX_MIN: 124 +!+ 0000007f VFD_INDEX_MAX: 127 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000007c VFD_INDEX_OFFSET: 124 +11845fd0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12471 + :0,12469,12814,12471 +11845fe0: 0000: 0000057f 000030b7 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12472 + :0,12472,12814,12471 +11845fe8: 0000: 0000057d 000030b8 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11845ff0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11845ff8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 128 + VFD_INDEX_MAX: 131 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 128 +11846000: 0000: 00032242 00000080 00000083 00000000 00000080 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846014: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12473 + :0,12472,12814,12473 +1184601c: 0000: 0000057f 000030b9 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 167 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[167] register values +!+ 000030b8 CP_SCRATCH_REG5: 12472 + :0,12472,12814,12473 +!+ 000030b9 CP_SCRATCH_REG7: 12473 + :0,12472,12814,12473 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000080 VFD_INDEX_MIN: 128 +!+ 00000083 VFD_INDEX_MAX: 131 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000080 VFD_INDEX_OFFSET: 128 +11846024: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12474 + :0,12472,12814,12474 +11846034: 0000: 0000057f 000030ba +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12475 + :0,12475,12814,12474 +1184603c: 0000: 0000057d 000030bb +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846044: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184604c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 132 + VFD_INDEX_MAX: 135 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 132 +11846054: 0000: 00032242 00000084 00000087 00000000 00000084 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846068: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12476 + :0,12475,12814,12476 +11846070: 0000: 0000057f 000030bc +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 168 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[168] register values +!+ 000030bb CP_SCRATCH_REG5: 12475 + :0,12475,12814,12476 +!+ 000030bc CP_SCRATCH_REG7: 12476 + :0,12475,12814,12476 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000084 VFD_INDEX_MIN: 132 +!+ 00000087 VFD_INDEX_MAX: 135 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000084 VFD_INDEX_OFFSET: 132 +11846078: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12477 + :0,12475,12814,12477 +11846088: 0000: 0000057f 000030bd +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12478 + :0,12478,12814,12477 +11846090: 0000: 0000057d 000030be +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846098: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118460a0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 136 + VFD_INDEX_MAX: 142 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 136 +118460a8: 0000: 00032242 00000088 0000008e 00000000 00000088 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118460bc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12479 + :0,12478,12814,12479 +118460c4: 0000: 0000057f 000030bf +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 169 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[169] register values +!+ 000030be CP_SCRATCH_REG5: 12478 + :0,12478,12814,12479 +!+ 000030bf CP_SCRATCH_REG7: 12479 + :0,12478,12814,12479 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000088 VFD_INDEX_MIN: 136 +!+ 0000008e VFD_INDEX_MAX: 142 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000088 VFD_INDEX_OFFSET: 136 +118460cc: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12480 + :0,12478,12814,12480 +118460dc: 0000: 0000057f 000030c0 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12481 + :0,12481,12814,12480 +118460e4: 0000: 0000057d 000030c1 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118460ec: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118460f4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 143 + VFD_INDEX_MAX: 146 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 143 +118460fc: 0000: 00032242 0000008f 00000092 00000000 0000008f +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846110: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12482 + :0,12481,12814,12482 +11846118: 0000: 0000057f 000030c2 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 170 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[170] register values +!+ 000030c1 CP_SCRATCH_REG5: 12481 + :0,12481,12814,12482 +!+ 000030c2 CP_SCRATCH_REG7: 12482 + :0,12481,12814,12482 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000008f VFD_INDEX_MIN: 143 +!+ 00000092 VFD_INDEX_MAX: 146 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000008f VFD_INDEX_OFFSET: 143 +11846120: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12483 + :0,12481,12814,12483 +11846130: 0000: 0000057f 000030c3 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12484 + :0,12484,12814,12483 +11846138: 0000: 0000057d 000030c4 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846140: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846148: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 147 + VFD_INDEX_MAX: 153 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 147 +11846150: 0000: 00032242 00000093 00000099 00000000 00000093 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846164: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12485 + :0,12484,12814,12485 +1184616c: 0000: 0000057f 000030c5 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 171 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[171] register values +!+ 000030c4 CP_SCRATCH_REG5: 12484 + :0,12484,12814,12485 +!+ 000030c5 CP_SCRATCH_REG7: 12485 + :0,12484,12814,12485 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000093 VFD_INDEX_MIN: 147 +!+ 00000099 VFD_INDEX_MAX: 153 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000093 VFD_INDEX_OFFSET: 147 +11846174: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12486 + :0,12484,12814,12486 +11846184: 0000: 0000057f 000030c6 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12487 + :0,12487,12814,12486 +1184618c: 0000: 0000057d 000030c7 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846194: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184619c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 154 + VFD_INDEX_MAX: 157 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 154 +118461a4: 0000: 00032242 0000009a 0000009d 00000000 0000009a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118461b8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12488 + :0,12487,12814,12488 +118461c0: 0000: 0000057f 000030c8 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 172 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[172] register values +!+ 000030c7 CP_SCRATCH_REG5: 12487 + :0,12487,12814,12488 +!+ 000030c8 CP_SCRATCH_REG7: 12488 + :0,12487,12814,12488 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000009a VFD_INDEX_MIN: 154 +!+ 0000009d VFD_INDEX_MAX: 157 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000009a VFD_INDEX_OFFSET: 154 +118461c8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12489 + :0,12487,12814,12489 +118461d8: 0000: 0000057f 000030c9 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12490 + :0,12490,12814,12489 +118461e0: 0000: 0000057d 000030ca +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118461e8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118461f0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 158 + VFD_INDEX_MAX: 161 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 158 +118461f8: 0000: 00032242 0000009e 000000a1 00000000 0000009e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184620c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12491 + :0,12490,12814,12491 +11846214: 0000: 0000057f 000030cb +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 173 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[173] register values +!+ 000030ca CP_SCRATCH_REG5: 12490 + :0,12490,12814,12491 +!+ 000030cb CP_SCRATCH_REG7: 12491 + :0,12490,12814,12491 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000009e VFD_INDEX_MIN: 158 +!+ 000000a1 VFD_INDEX_MAX: 161 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000009e VFD_INDEX_OFFSET: 158 +1184621c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12492 + :0,12490,12814,12492 +1184622c: 0000: 0000057f 000030cc +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12493 + :0,12493,12814,12492 +11846234: 0000: 0000057d 000030cd +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184623c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846244: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 162 + VFD_INDEX_MAX: 165 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 162 +1184624c: 0000: 00032242 000000a2 000000a5 00000000 000000a2 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846260: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12494 + :0,12493,12814,12494 +11846268: 0000: 0000057f 000030ce +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 174 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[174] register values +!+ 000030cd CP_SCRATCH_REG5: 12493 + :0,12493,12814,12494 +!+ 000030ce CP_SCRATCH_REG7: 12494 + :0,12493,12814,12494 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000a2 VFD_INDEX_MIN: 162 +!+ 000000a5 VFD_INDEX_MAX: 165 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000a2 VFD_INDEX_OFFSET: 162 +11846270: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12495 + :0,12493,12814,12495 +11846280: 0000: 0000057f 000030cf +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12496 + :0,12496,12814,12495 +11846288: 0000: 0000057d 000030d0 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846290: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846298: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 166 + VFD_INDEX_MAX: 169 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 166 +118462a0: 0000: 00032242 000000a6 000000a9 00000000 000000a6 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118462b4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12497 + :0,12496,12814,12497 +118462bc: 0000: 0000057f 000030d1 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 175 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[175] register values +!+ 000030d0 CP_SCRATCH_REG5: 12496 + :0,12496,12814,12497 +!+ 000030d1 CP_SCRATCH_REG7: 12497 + :0,12496,12814,12497 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000a6 VFD_INDEX_MIN: 166 +!+ 000000a9 VFD_INDEX_MAX: 169 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000a6 VFD_INDEX_OFFSET: 166 +118462c4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12498 + :0,12496,12814,12498 +118462d4: 0000: 0000057f 000030d2 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12499 + :0,12499,12814,12498 +118462dc: 0000: 0000057d 000030d3 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118462e4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118462ec: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 170 + VFD_INDEX_MAX: 176 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 170 +118462f4: 0000: 00032242 000000aa 000000b0 00000000 000000aa +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846308: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12500 + :0,12499,12814,12500 +11846310: 0000: 0000057f 000030d4 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 176 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[176] register values +!+ 000030d3 CP_SCRATCH_REG5: 12499 + :0,12499,12814,12500 +!+ 000030d4 CP_SCRATCH_REG7: 12500 + :0,12499,12814,12500 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000aa VFD_INDEX_MIN: 170 +!+ 000000b0 VFD_INDEX_MAX: 176 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000aa VFD_INDEX_OFFSET: 170 +11846318: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12501 + :0,12499,12814,12501 +11846328: 0000: 0000057f 000030d5 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12502 + :0,12502,12814,12501 +11846330: 0000: 0000057d 000030d6 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846338: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846340: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 177 + VFD_INDEX_MAX: 180 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 177 +11846348: 0000: 00032242 000000b1 000000b4 00000000 000000b1 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184635c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12503 + :0,12502,12814,12503 +11846364: 0000: 0000057f 000030d7 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 177 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[177] register values +!+ 000030d6 CP_SCRATCH_REG5: 12502 + :0,12502,12814,12503 +!+ 000030d7 CP_SCRATCH_REG7: 12503 + :0,12502,12814,12503 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000b1 VFD_INDEX_MIN: 177 +!+ 000000b4 VFD_INDEX_MAX: 180 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000b1 VFD_INDEX_OFFSET: 177 +1184636c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12504 + :0,12502,12814,12504 +1184637c: 0000: 0000057f 000030d8 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12505 + :0,12505,12814,12504 +11846384: 0000: 0000057d 000030d9 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184638c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846394: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 181 + VFD_INDEX_MAX: 187 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 181 +1184639c: 0000: 00032242 000000b5 000000bb 00000000 000000b5 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118463b0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12506 + :0,12505,12814,12506 +118463b8: 0000: 0000057f 000030da +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 178 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[178] register values +!+ 000030d9 CP_SCRATCH_REG5: 12505 + :0,12505,12814,12506 +!+ 000030da CP_SCRATCH_REG7: 12506 + :0,12505,12814,12506 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000b5 VFD_INDEX_MIN: 181 +!+ 000000bb VFD_INDEX_MAX: 187 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000b5 VFD_INDEX_OFFSET: 181 +118463c0: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12507 + :0,12505,12814,12507 +118463d0: 0000: 0000057f 000030db +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12508 + :0,12508,12814,12507 +118463d8: 0000: 0000057d 000030dc +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118463e0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118463e8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 188 + VFD_INDEX_MAX: 191 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 188 +118463f0: 0000: 00032242 000000bc 000000bf 00000000 000000bc +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846404: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12509 + :0,12508,12814,12509 +1184640c: 0000: 0000057f 000030dd +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 179 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[179] register values +!+ 000030dc CP_SCRATCH_REG5: 12508 + :0,12508,12814,12509 +!+ 000030dd CP_SCRATCH_REG7: 12509 + :0,12508,12814,12509 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000bc VFD_INDEX_MIN: 188 +!+ 000000bf VFD_INDEX_MAX: 191 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000bc VFD_INDEX_OFFSET: 188 +11846414: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12510 + :0,12508,12814,12510 +11846424: 0000: 0000057f 000030de +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12511 + :0,12511,12814,12510 +1184642c: 0000: 0000057d 000030df +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846434: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184643c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 192 + VFD_INDEX_MAX: 195 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 192 +11846444: 0000: 00032242 000000c0 000000c3 00000000 000000c0 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846458: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12512 + :0,12511,12814,12512 +11846460: 0000: 0000057f 000030e0 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 180 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[180] register values +!+ 000030df CP_SCRATCH_REG5: 12511 + :0,12511,12814,12512 +!+ 000030e0 CP_SCRATCH_REG7: 12512 + :0,12511,12814,12512 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000c0 VFD_INDEX_MIN: 192 +!+ 000000c3 VFD_INDEX_MAX: 195 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000c0 VFD_INDEX_OFFSET: 192 +11846468: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12513 + :0,12511,12814,12513 +11846478: 0000: 0000057f 000030e1 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12514 + :0,12514,12814,12513 +11846480: 0000: 0000057d 000030e2 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846488: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846490: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 196 + VFD_INDEX_MAX: 199 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 196 +11846498: 0000: 00032242 000000c4 000000c7 00000000 000000c4 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118464ac: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12515 + :0,12514,12814,12515 +118464b4: 0000: 0000057f 000030e3 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 181 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[181] register values +!+ 000030e2 CP_SCRATCH_REG5: 12514 + :0,12514,12814,12515 +!+ 000030e3 CP_SCRATCH_REG7: 12515 + :0,12514,12814,12515 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000c4 VFD_INDEX_MIN: 196 +!+ 000000c7 VFD_INDEX_MAX: 199 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000c4 VFD_INDEX_OFFSET: 196 +118464bc: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12516 + :0,12514,12814,12516 +118464cc: 0000: 0000057f 000030e4 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12517 + :0,12517,12814,12516 +118464d4: 0000: 0000057d 000030e5 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118464dc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118464e4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 200 + VFD_INDEX_MAX: 203 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 200 +118464ec: 0000: 00032242 000000c8 000000cb 00000000 000000c8 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846500: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12518 + :0,12517,12814,12518 +11846508: 0000: 0000057f 000030e6 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 182 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[182] register values +!+ 000030e5 CP_SCRATCH_REG5: 12517 + :0,12517,12814,12518 +!+ 000030e6 CP_SCRATCH_REG7: 12518 + :0,12517,12814,12518 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000c8 VFD_INDEX_MIN: 200 +!+ 000000cb VFD_INDEX_MAX: 203 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000c8 VFD_INDEX_OFFSET: 200 +11846510: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12519 + :0,12517,12814,12519 +11846520: 0000: 0000057f 000030e7 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12520 + :0,12520,12814,12519 +11846528: 0000: 0000057d 000030e8 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846530: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846538: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 204 + VFD_INDEX_MAX: 210 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 204 +11846540: 0000: 00032242 000000cc 000000d2 00000000 000000cc +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846554: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12521 + :0,12520,12814,12521 +1184655c: 0000: 0000057f 000030e9 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 183 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[183] register values +!+ 000030e8 CP_SCRATCH_REG5: 12520 + :0,12520,12814,12521 +!+ 000030e9 CP_SCRATCH_REG7: 12521 + :0,12520,12814,12521 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000cc VFD_INDEX_MIN: 204 +!+ 000000d2 VFD_INDEX_MAX: 210 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000cc VFD_INDEX_OFFSET: 204 +11846564: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12522 + :0,12520,12814,12522 +11846574: 0000: 0000057f 000030ea +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12523 + :0,12523,12814,12522 +1184657c: 0000: 0000057d 000030eb +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846584: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184658c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 211 + VFD_INDEX_MAX: 214 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 211 +11846594: 0000: 00032242 000000d3 000000d6 00000000 000000d3 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118465a8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12524 + :0,12523,12814,12524 +118465b0: 0000: 0000057f 000030ec +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 184 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[184] register values +!+ 000030eb CP_SCRATCH_REG5: 12523 + :0,12523,12814,12524 +!+ 000030ec CP_SCRATCH_REG7: 12524 + :0,12523,12814,12524 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000d3 VFD_INDEX_MIN: 211 +!+ 000000d6 VFD_INDEX_MAX: 214 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000d3 VFD_INDEX_OFFSET: 211 +118465b8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12525 + :0,12523,12814,12525 +118465c8: 0000: 0000057f 000030ed +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12526 + :0,12526,12814,12525 +118465d0: 0000: 0000057d 000030ee +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118465d8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118465e0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 215 + VFD_INDEX_MAX: 221 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 215 +118465e8: 0000: 00032242 000000d7 000000dd 00000000 000000d7 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118465fc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12527 + :0,12526,12814,12527 +11846604: 0000: 0000057f 000030ef +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 185 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[185] register values +!+ 000030ee CP_SCRATCH_REG5: 12526 + :0,12526,12814,12527 +!+ 000030ef CP_SCRATCH_REG7: 12527 + :0,12526,12814,12527 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000d7 VFD_INDEX_MIN: 215 +!+ 000000dd VFD_INDEX_MAX: 221 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000d7 VFD_INDEX_OFFSET: 215 +1184660c: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12528 + :0,12526,12814,12528 +1184661c: 0000: 0000057f 000030f0 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12529 + :0,12529,12814,12528 +11846624: 0000: 0000057d 000030f1 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184662c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846634: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 222 + VFD_INDEX_MAX: 225 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 222 +1184663c: 0000: 00032242 000000de 000000e1 00000000 000000de +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846650: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12530 + :0,12529,12814,12530 +11846658: 0000: 0000057f 000030f2 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 186 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[186] register values +!+ 000030f1 CP_SCRATCH_REG5: 12529 + :0,12529,12814,12530 +!+ 000030f2 CP_SCRATCH_REG7: 12530 + :0,12529,12814,12530 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000de VFD_INDEX_MIN: 222 +!+ 000000e1 VFD_INDEX_MAX: 225 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000de VFD_INDEX_OFFSET: 222 +11846660: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12531 + :0,12529,12814,12531 +11846670: 0000: 0000057f 000030f3 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12532 + :0,12532,12814,12531 +11846678: 0000: 0000057d 000030f4 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846680: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846688: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 226 + VFD_INDEX_MAX: 229 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 226 +11846690: 0000: 00032242 000000e2 000000e5 00000000 000000e2 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118466a4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12533 + :0,12532,12814,12533 +118466ac: 0000: 0000057f 000030f5 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 187 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[187] register values +!+ 000030f4 CP_SCRATCH_REG5: 12532 + :0,12532,12814,12533 +!+ 000030f5 CP_SCRATCH_REG7: 12533 + :0,12532,12814,12533 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000e2 VFD_INDEX_MIN: 226 +!+ 000000e5 VFD_INDEX_MAX: 229 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000e2 VFD_INDEX_OFFSET: 226 +118466b4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12534 + :0,12532,12814,12534 +118466c4: 0000: 0000057f 000030f6 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12535 + :0,12535,12814,12534 +118466cc: 0000: 0000057d 000030f7 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118466d4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118466dc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 230 + VFD_INDEX_MAX: 233 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 230 +118466e4: 0000: 00032242 000000e6 000000e9 00000000 000000e6 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118466f8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12536 + :0,12535,12814,12536 +11846700: 0000: 0000057f 000030f8 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 188 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[188] register values +!+ 000030f7 CP_SCRATCH_REG5: 12535 + :0,12535,12814,12536 +!+ 000030f8 CP_SCRATCH_REG7: 12536 + :0,12535,12814,12536 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000e6 VFD_INDEX_MIN: 230 +!+ 000000e9 VFD_INDEX_MAX: 233 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000e6 VFD_INDEX_OFFSET: 230 +11846708: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12537 + :0,12535,12814,12537 +11846718: 0000: 0000057f 000030f9 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12538 + :0,12538,12814,12537 +11846720: 0000: 0000057d 000030fa +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846728: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846730: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 234 + VFD_INDEX_MAX: 237 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 234 +11846738: 0000: 00032242 000000ea 000000ed 00000000 000000ea +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184674c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12539 + :0,12538,12814,12539 +11846754: 0000: 0000057f 000030fb +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 189 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[189] register values +!+ 000030fa CP_SCRATCH_REG5: 12538 + :0,12538,12814,12539 +!+ 000030fb CP_SCRATCH_REG7: 12539 + :0,12538,12814,12539 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000ea VFD_INDEX_MIN: 234 +!+ 000000ed VFD_INDEX_MAX: 237 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000ea VFD_INDEX_OFFSET: 234 +1184675c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12540 + :0,12538,12814,12540 +1184676c: 0000: 0000057f 000030fc +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12541 + :0,12541,12814,12540 +11846774: 0000: 0000057d 000030fd +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184677c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846784: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 238 + VFD_INDEX_MAX: 244 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 238 +1184678c: 0000: 00032242 000000ee 000000f4 00000000 000000ee +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118467a0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12542 + :0,12541,12814,12542 +118467a8: 0000: 0000057f 000030fe +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 190 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[190] register values +!+ 000030fd CP_SCRATCH_REG5: 12541 + :0,12541,12814,12542 +!+ 000030fe CP_SCRATCH_REG7: 12542 + :0,12541,12814,12542 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000ee VFD_INDEX_MIN: 238 +!+ 000000f4 VFD_INDEX_MAX: 244 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000ee VFD_INDEX_OFFSET: 238 +118467b0: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12543 + :0,12541,12814,12543 +118467c0: 0000: 0000057f 000030ff +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12544 + :0,12544,12814,12543 +118467c8: 0000: 0000057d 00003100 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118467d0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118467d8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 245 + VFD_INDEX_MAX: 248 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 245 +118467e0: 0000: 00032242 000000f5 000000f8 00000000 000000f5 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118467f4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12545 + :0,12544,12814,12545 +118467fc: 0000: 0000057f 00003101 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 191 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[191] register values +!+ 00003100 CP_SCRATCH_REG5: 12544 + :0,12544,12814,12545 +!+ 00003101 CP_SCRATCH_REG7: 12545 + :0,12544,12814,12545 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000f5 VFD_INDEX_MIN: 245 +!+ 000000f8 VFD_INDEX_MAX: 248 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000f5 VFD_INDEX_OFFSET: 245 +11846804: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12546 + :0,12544,12814,12546 +11846814: 0000: 0000057f 00003102 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12547 + :0,12547,12814,12546 +1184681c: 0000: 0000057d 00003103 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846824: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184682c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 249 + VFD_INDEX_MAX: 255 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 249 +11846834: 0000: 00032242 000000f9 000000ff 00000000 000000f9 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846848: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12548 + :0,12547,12814,12548 +11846850: 0000: 0000057f 00003104 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 192 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[192] register values +!+ 00003103 CP_SCRATCH_REG5: 12547 + :0,12547,12814,12548 +!+ 00003104 CP_SCRATCH_REG7: 12548 + :0,12547,12814,12548 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000f9 VFD_INDEX_MIN: 249 +!+ 000000ff VFD_INDEX_MAX: 255 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000f9 VFD_INDEX_OFFSET: 249 +11846858: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12549 + :0,12547,12814,12549 +11846868: 0000: 0000057f 00003105 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12550 + :0,12550,12814,12549 +11846870: 0000: 0000057d 00003106 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846878: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846880: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 256 + VFD_INDEX_MAX: 259 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 256 +11846888: 0000: 00032242 00000100 00000103 00000000 00000100 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184689c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12551 + :0,12550,12814,12551 +118468a4: 0000: 0000057f 00003107 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 193 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[193] register values +!+ 00003106 CP_SCRATCH_REG5: 12550 + :0,12550,12814,12551 +!+ 00003107 CP_SCRATCH_REG7: 12551 + :0,12550,12814,12551 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000100 VFD_INDEX_MIN: 256 +!+ 00000103 VFD_INDEX_MAX: 259 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000100 VFD_INDEX_OFFSET: 256 +118468ac: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12552 + :0,12550,12814,12552 +118468bc: 0000: 0000057f 00003108 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12553 + :0,12553,12814,12552 +118468c4: 0000: 0000057d 00003109 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118468cc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118468d4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 260 + VFD_INDEX_MAX: 263 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 260 +118468dc: 0000: 00032242 00000104 00000107 00000000 00000104 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118468f0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12554 + :0,12553,12814,12554 +118468f8: 0000: 0000057f 0000310a +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 194 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[194] register values +!+ 00003109 CP_SCRATCH_REG5: 12553 + :0,12553,12814,12554 +!+ 0000310a CP_SCRATCH_REG7: 12554 + :0,12553,12814,12554 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000104 VFD_INDEX_MIN: 260 +!+ 00000107 VFD_INDEX_MAX: 263 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000104 VFD_INDEX_OFFSET: 260 +11846900: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12555 + :0,12553,12814,12555 +11846910: 0000: 0000057f 0000310b +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12556 + :0,12556,12814,12555 +11846918: 0000: 0000057d 0000310c +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846920: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846928: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 264 + VFD_INDEX_MAX: 267 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 264 +11846930: 0000: 00032242 00000108 0000010b 00000000 00000108 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846944: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12557 + :0,12556,12814,12557 +1184694c: 0000: 0000057f 0000310d +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 195 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[195] register values +!+ 0000310c CP_SCRATCH_REG5: 12556 + :0,12556,12814,12557 +!+ 0000310d CP_SCRATCH_REG7: 12557 + :0,12556,12814,12557 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000108 VFD_INDEX_MIN: 264 +!+ 0000010b VFD_INDEX_MAX: 267 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000108 VFD_INDEX_OFFSET: 264 +11846954: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12558 + :0,12556,12814,12558 +11846964: 0000: 0000057f 0000310e +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12559 + :0,12559,12814,12558 +1184696c: 0000: 0000057d 0000310f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846974: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184697c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 268 + VFD_INDEX_MAX: 271 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 268 +11846984: 0000: 00032242 0000010c 0000010f 00000000 0000010c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846998: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12560 + :0,12559,12814,12560 +118469a0: 0000: 0000057f 00003110 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 196 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[196] register values +!+ 0000310f CP_SCRATCH_REG5: 12559 + :0,12559,12814,12560 +!+ 00003110 CP_SCRATCH_REG7: 12560 + :0,12559,12814,12560 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000010c VFD_INDEX_MIN: 268 +!+ 0000010f VFD_INDEX_MAX: 271 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000010c VFD_INDEX_OFFSET: 268 +118469a8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12561 + :0,12559,12814,12561 +118469b8: 0000: 0000057f 00003111 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12562 + :0,12562,12814,12561 +118469c0: 0000: 0000057d 00003112 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118469c8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118469d0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 272 + VFD_INDEX_MAX: 278 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 272 +118469d8: 0000: 00032242 00000110 00000116 00000000 00000110 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118469ec: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12563 + :0,12562,12814,12563 +118469f4: 0000: 0000057f 00003113 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 197 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[197] register values +!+ 00003112 CP_SCRATCH_REG5: 12562 + :0,12562,12814,12563 +!+ 00003113 CP_SCRATCH_REG7: 12563 + :0,12562,12814,12563 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000110 VFD_INDEX_MIN: 272 +!+ 00000116 VFD_INDEX_MAX: 278 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000110 VFD_INDEX_OFFSET: 272 +118469fc: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12564 + :0,12562,12814,12564 +11846a0c: 0000: 0000057f 00003114 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12565 + :0,12565,12814,12564 +11846a14: 0000: 0000057d 00003115 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846a1c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846a24: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 279 + VFD_INDEX_MAX: 282 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 279 +11846a2c: 0000: 00032242 00000117 0000011a 00000000 00000117 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846a40: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12566 + :0,12565,12814,12566 +11846a48: 0000: 0000057f 00003116 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 198 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[198] register values +!+ 00003115 CP_SCRATCH_REG5: 12565 + :0,12565,12814,12566 +!+ 00003116 CP_SCRATCH_REG7: 12566 + :0,12565,12814,12566 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000117 VFD_INDEX_MIN: 279 +!+ 0000011a VFD_INDEX_MAX: 282 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000117 VFD_INDEX_OFFSET: 279 +11846a50: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12567 + :0,12565,12814,12567 +11846a60: 0000: 0000057f 00003117 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12568 + :0,12568,12814,12567 +11846a68: 0000: 0000057d 00003118 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846a70: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846a78: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 283 + VFD_INDEX_MAX: 289 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 283 +11846a80: 0000: 00032242 0000011b 00000121 00000000 0000011b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846a94: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12569 + :0,12568,12814,12569 +11846a9c: 0000: 0000057f 00003119 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 199 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[199] register values +!+ 00003118 CP_SCRATCH_REG5: 12568 + :0,12568,12814,12569 +!+ 00003119 CP_SCRATCH_REG7: 12569 + :0,12568,12814,12569 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000011b VFD_INDEX_MIN: 283 +!+ 00000121 VFD_INDEX_MAX: 289 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000011b VFD_INDEX_OFFSET: 283 +11846aa4: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12570 + :0,12568,12814,12570 +11846ab4: 0000: 0000057f 0000311a +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12571 + :0,12571,12814,12570 +11846abc: 0000: 0000057d 0000311b +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846ac4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846acc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 290 + VFD_INDEX_MAX: 293 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 290 +11846ad4: 0000: 00032242 00000122 00000125 00000000 00000122 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846ae8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12572 + :0,12571,12814,12572 +11846af0: 0000: 0000057f 0000311c +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 200 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[200] register values +!+ 0000311b CP_SCRATCH_REG5: 12571 + :0,12571,12814,12572 +!+ 0000311c CP_SCRATCH_REG7: 12572 + :0,12571,12814,12572 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000122 VFD_INDEX_MIN: 290 +!+ 00000125 VFD_INDEX_MAX: 293 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000122 VFD_INDEX_OFFSET: 290 +11846af8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12573 + :0,12571,12814,12573 +11846b08: 0000: 0000057f 0000311d +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12574 + :0,12574,12814,12573 +11846b10: 0000: 0000057d 0000311e +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846b18: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846b20: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 294 + VFD_INDEX_MAX: 297 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 294 +11846b28: 0000: 00032242 00000126 00000129 00000000 00000126 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846b3c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12575 + :0,12574,12814,12575 +11846b44: 0000: 0000057f 0000311f +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 201 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[201] register values +!+ 0000311e CP_SCRATCH_REG5: 12574 + :0,12574,12814,12575 +!+ 0000311f CP_SCRATCH_REG7: 12575 + :0,12574,12814,12575 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000126 VFD_INDEX_MIN: 294 +!+ 00000129 VFD_INDEX_MAX: 297 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000126 VFD_INDEX_OFFSET: 294 +11846b4c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12576 + :0,12574,12814,12576 +11846b5c: 0000: 0000057f 00003120 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12577 + :0,12577,12814,12576 +11846b64: 0000: 0000057d 00003121 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846b6c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846b74: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 298 + VFD_INDEX_MAX: 301 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 298 +11846b7c: 0000: 00032242 0000012a 0000012d 00000000 0000012a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846b90: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12578 + :0,12577,12814,12578 +11846b98: 0000: 0000057f 00003122 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 202 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[202] register values +!+ 00003121 CP_SCRATCH_REG5: 12577 + :0,12577,12814,12578 +!+ 00003122 CP_SCRATCH_REG7: 12578 + :0,12577,12814,12578 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000012a VFD_INDEX_MIN: 298 +!+ 0000012d VFD_INDEX_MAX: 301 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000012a VFD_INDEX_OFFSET: 298 +11846ba0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12579 + :0,12577,12814,12579 +11846bb0: 0000: 0000057f 00003123 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12580 + :0,12580,12814,12579 +11846bb8: 0000: 0000057d 00003124 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846bc0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846bc8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 302 + VFD_INDEX_MAX: 305 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 302 +11846bd0: 0000: 00032242 0000012e 00000131 00000000 0000012e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846be4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12581 + :0,12580,12814,12581 +11846bec: 0000: 0000057f 00003125 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 203 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[203] register values +!+ 00003124 CP_SCRATCH_REG5: 12580 + :0,12580,12814,12581 +!+ 00003125 CP_SCRATCH_REG7: 12581 + :0,12580,12814,12581 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000012e VFD_INDEX_MIN: 302 +!+ 00000131 VFD_INDEX_MAX: 305 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000012e VFD_INDEX_OFFSET: 302 +11846bf4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12582 + :0,12580,12814,12582 +11846c04: 0000: 0000057f 00003126 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12583 + :0,12583,12814,12582 +11846c0c: 0000: 0000057d 00003127 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846c14: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846c1c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 306 + VFD_INDEX_MAX: 312 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 306 +11846c24: 0000: 00032242 00000132 00000138 00000000 00000132 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846c38: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12584 + :0,12583,12814,12584 +11846c40: 0000: 0000057f 00003128 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 204 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[204] register values +!+ 00003127 CP_SCRATCH_REG5: 12583 + :0,12583,12814,12584 +!+ 00003128 CP_SCRATCH_REG7: 12584 + :0,12583,12814,12584 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000132 VFD_INDEX_MIN: 306 +!+ 00000138 VFD_INDEX_MAX: 312 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000132 VFD_INDEX_OFFSET: 306 +11846c48: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12585 + :0,12583,12814,12585 +11846c58: 0000: 0000057f 00003129 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12586 + :0,12586,12814,12585 +11846c60: 0000: 0000057d 0000312a +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846c68: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846c70: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 313 + VFD_INDEX_MAX: 316 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 313 +11846c78: 0000: 00032242 00000139 0000013c 00000000 00000139 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846c8c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12587 + :0,12586,12814,12587 +11846c94: 0000: 0000057f 0000312b +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 205 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[205] register values +!+ 0000312a CP_SCRATCH_REG5: 12586 + :0,12586,12814,12587 +!+ 0000312b CP_SCRATCH_REG7: 12587 + :0,12586,12814,12587 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000139 VFD_INDEX_MIN: 313 +!+ 0000013c VFD_INDEX_MAX: 316 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000139 VFD_INDEX_OFFSET: 313 +11846c9c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12588 + :0,12586,12814,12588 +11846cac: 0000: 0000057f 0000312c +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12589 + :0,12589,12814,12588 +11846cb4: 0000: 0000057d 0000312d +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846cbc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846cc4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 317 + VFD_INDEX_MAX: 323 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 317 +11846ccc: 0000: 00032242 0000013d 00000143 00000000 0000013d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846ce0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12590 + :0,12589,12814,12590 +11846ce8: 0000: 0000057f 0000312e +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 206 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[206] register values +!+ 0000312d CP_SCRATCH_REG5: 12589 + :0,12589,12814,12590 +!+ 0000312e CP_SCRATCH_REG7: 12590 + :0,12589,12814,12590 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000013d VFD_INDEX_MIN: 317 +!+ 00000143 VFD_INDEX_MAX: 323 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000013d VFD_INDEX_OFFSET: 317 +11846cf0: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12591 + :0,12589,12814,12591 +11846d00: 0000: 0000057f 0000312f +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12592 + :0,12592,12814,12591 +11846d08: 0000: 0000057d 00003130 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846d10: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846d18: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 324 + VFD_INDEX_MAX: 327 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 324 +11846d20: 0000: 00032242 00000144 00000147 00000000 00000144 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846d34: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12593 + :0,12592,12814,12593 +11846d3c: 0000: 0000057f 00003131 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 207 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[207] register values +!+ 00003130 CP_SCRATCH_REG5: 12592 + :0,12592,12814,12593 +!+ 00003131 CP_SCRATCH_REG7: 12593 + :0,12592,12814,12593 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000144 VFD_INDEX_MIN: 324 +!+ 00000147 VFD_INDEX_MAX: 327 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000144 VFD_INDEX_OFFSET: 324 +11846d44: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12594 + :0,12592,12814,12594 +11846d54: 0000: 0000057f 00003132 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12595 + :0,12595,12814,12594 +11846d5c: 0000: 0000057d 00003133 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846d64: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846d6c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 328 + VFD_INDEX_MAX: 331 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 328 +11846d74: 0000: 00032242 00000148 0000014b 00000000 00000148 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846d88: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12596 + :0,12595,12814,12596 +11846d90: 0000: 0000057f 00003134 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 208 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[208] register values +!+ 00003133 CP_SCRATCH_REG5: 12595 + :0,12595,12814,12596 +!+ 00003134 CP_SCRATCH_REG7: 12596 + :0,12595,12814,12596 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000148 VFD_INDEX_MIN: 328 +!+ 0000014b VFD_INDEX_MAX: 331 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000148 VFD_INDEX_OFFSET: 328 +11846d98: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12597 + :0,12595,12814,12597 +11846da8: 0000: 0000057f 00003135 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12598 + :0,12598,12814,12597 +11846db0: 0000: 0000057d 00003136 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846db8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846dc0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 332 + VFD_INDEX_MAX: 335 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 332 +11846dc8: 0000: 00032242 0000014c 0000014f 00000000 0000014c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846ddc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12599 + :0,12598,12814,12599 +11846de4: 0000: 0000057f 00003137 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 209 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[209] register values +!+ 00003136 CP_SCRATCH_REG5: 12598 + :0,12598,12814,12599 +!+ 00003137 CP_SCRATCH_REG7: 12599 + :0,12598,12814,12599 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000014c VFD_INDEX_MIN: 332 +!+ 0000014f VFD_INDEX_MAX: 335 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000014c VFD_INDEX_OFFSET: 332 +11846dec: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12600 + :0,12598,12814,12600 +11846dfc: 0000: 0000057f 00003138 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12601 + :0,12601,12814,12600 +11846e04: 0000: 0000057d 00003139 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846e0c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846e14: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 336 + VFD_INDEX_MAX: 339 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 336 +11846e1c: 0000: 00032242 00000150 00000153 00000000 00000150 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846e30: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12602 + :0,12601,12814,12602 +11846e38: 0000: 0000057f 0000313a +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 210 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[210] register values +!+ 00003139 CP_SCRATCH_REG5: 12601 + :0,12601,12814,12602 +!+ 0000313a CP_SCRATCH_REG7: 12602 + :0,12601,12814,12602 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000150 VFD_INDEX_MIN: 336 +!+ 00000153 VFD_INDEX_MAX: 339 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000150 VFD_INDEX_OFFSET: 336 +11846e40: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12603 + :0,12601,12814,12603 +11846e50: 0000: 0000057f 0000313b +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12604 + :0,12604,12814,12603 +11846e58: 0000: 0000057d 0000313c +t0 write UCHE_CACHE_INVALIDATE0_REG (0ea0) +NEEDS WFI: UCHE_CACHE_INVALIDATE0_REG (ea0) + UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 } +NEEDS WFI: UCHE_CACHE_INVALIDATE1_REG (ea1) + UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE } +11846e60: 0000: 00010ea0 00000000 90000000 +t3 opcode: CP_LOAD_STATE (30) (43 dwords) + { DST_OFF = 0 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 20 } + { STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 } +11846e78: 1.314712 -0.523992 0.577600 0.576473 0.722172 1.569150 -0.073709 -0.073566 +11846e98: 0.866025 -0.513030 -0.815389 -0.813798 -4.650000 5.917686 15.138483 17.106993 +11846eb8: 0.759049 -0.302527 -0.576473 -6.790315 0.416946 0.905949 0.073566 -0.717395 +11846ed8: 0.500000 -0.296198 0.813798 16.275953 0.000000 0.000000 0.000000 1.000000 +11846ef8: 5.000000 5.000000 10.000000 1.000000 0.200000 0.200000 1.000000 1.000000 +11846e78: 0000: 3fa8487d bf062456 3f13dd9d 3f1393c1 3f38e03d 3fc8d9eb bd96f4f4 bd96a98c +11846e98: 0020: 3f5db3d7 bf0355f2 bf50bd50 bf50550b c094cccc 40bd5db0 4172373a 4188db1f +11846eb8: 0040: 3f425110 be9ae4ce bf1393c1 c0d94a42 3ed579f2 3f67ec4c 3d96a98c bf37a732 +11846ed8: 0060: 3f000000 be97a747 3f50550b 41823527 00000000 00000000 00000000 3f800000 +11846ef8: 0080: 40a00000 40a00000 41200000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 +11846e6c: 0000: c0293000 05200000 00000001 3fa8487d bf062456 3f13dd9d 3f1393c1 3f38e03d +11846e8c: 0020: 3fc8d9eb bd96f4f4 bd96a98c 3f5db3d7 bf0355f2 bf50bd50 bf50550b c094cccc +11846eac: 0040: 40bd5db0 4172373a 4188db1f 3f425110 be9ae4ce bf1393c1 c0d94a42 3ed579f2 +11846ecc: 0060: 3f67ec4c 3d96a98c bf37a732 3f000000 be97a747 3f50550b 41823527 00000000 +11846eec: 0080: 00000000 00000000 3f800000 40a00000 40a00000 41200000 3f800000 3e4ccccd +11846f0c: 00a0: 3e4ccccd 3f800000 3f800000 +t0 write UCHE_CACHE_INVALIDATE0_REG (0ea0) +NEEDS WFI: UCHE_CACHE_INVALIDATE0_REG (ea0) + UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 } +NEEDS WFI: UCHE_CACHE_INVALIDATE1_REG (ea1) + UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE } +11846f18: 0000: 00010ea0 00000000 90000000 +t3 opcode: CP_LOAD_STATE (30) (7 dwords) + { DST_OFF = 20 | STATE_SRC = SS_DIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 2 } + { STATE_TYPE = ST_CONSTANTS | EXT_SRC_ADDR = 0 } +11846f30: 0.000000 0.000000 0.000000 0.000000 +11846f30: 0000: 00000000 00000000 00000000 00000000 +11846f24: 0000: c0053000 00a00014 00000001 00000000 00000000 00000000 00000000 +t0 write VFD_FETCH[0].INSTR_0 (2246) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT | INDEXCODE = 0 | STEPRATE = 1 } + VFD_FETCH[0].INSTR_1: 0x127f0000 +11846f40: 0000: 00012246 01020c0b 127f0000 +t0 write VFD_DECODE[0].INSTR (2266) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } +11846f4c: 0000: 00002266 6c00009f +t0 write VFD_FETCH[0x1].INSTR_0 (2248) + VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | INDEXCODE = 1 | STEPRATE = 1 } + VFD_FETCH[0x1].INSTR_1: 0x127f000c +11846f54: 0000: 00012248 01040c0b 127f000c +t0 write VFD_DECODE[0x1].INSTR (2267) + VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +11846f60: 0000: 00002267 2c00409f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846f68: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846f70: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 0 + VFD_INDEX_MAX: 6 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 0 +11846f78: 0000: 00032242 00000000 00000006 00000000 00000000 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846f8c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12605 + :0,12604,12814,12605 +11846f94: 0000: 0000057f 0000313d +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 211 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[211] register values +!+ 0000313c CP_SCRATCH_REG5: 12604 + :0,12604,12814,12605 +!+ 0000313d CP_SCRATCH_REG7: 12605 + :0,12604,12814,12605 + + 00000000 UCHE_CACHE_INVALIDATE0_REG: { ADDR = 0 } + + 90000000 UCHE_CACHE_INVALIDATE1_REG: { ADDR = 0 | OPCODE = INVALIDATE | ENTIRE_CACHE } + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000000 VFD_INDEX_MIN: 0 +!+ 00000006 VFD_INDEX_MAX: 6 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000000 VFD_INDEX_OFFSET: 0 + + 01020c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT | INDEXCODE = 0 | STEPRATE = 1 } +!+ 127f0000 VFD_FETCH[0].INSTR_1: 0x127f0000 + + 01040c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | INDEXCODE = 1 | STEPRATE = 1 } +!+ 127f000c VFD_FETCH[0x1].INSTR_1: 0x127f000c + + 6c00009f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } + + 2c00409f VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r1.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +11846f9c: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12606 + :0,12604,12814,12606 +11846fac: 0000: 0000057f 0000313e +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12607 + :0,12607,12814,12606 +11846fb4: 0000: 0000057d 0000313f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11846fbc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11846fc4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 7 + VFD_INDEX_MAX: 10 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 7 +11846fcc: 0000: 00032242 00000007 0000000a 00000000 00000007 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11846fe0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12608 + :0,12607,12814,12608 +11846fe8: 0000: 0000057f 00003140 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 212 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[212] register values +!+ 0000313f CP_SCRATCH_REG5: 12607 + :0,12607,12814,12608 +!+ 00003140 CP_SCRATCH_REG7: 12608 + :0,12607,12814,12608 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000007 VFD_INDEX_MIN: 7 +!+ 0000000a VFD_INDEX_MAX: 10 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000007 VFD_INDEX_OFFSET: 7 +11846ff0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12609 + :0,12607,12814,12609 +11847000: 0000: 0000057f 00003141 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12610 + :0,12610,12814,12609 +11847008: 0000: 0000057d 00003142 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847010: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847018: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 11 + VFD_INDEX_MAX: 17 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 11 +11847020: 0000: 00032242 0000000b 00000011 00000000 0000000b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847034: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12611 + :0,12610,12814,12611 +1184703c: 0000: 0000057f 00003143 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 213 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[213] register values +!+ 00003142 CP_SCRATCH_REG5: 12610 + :0,12610,12814,12611 +!+ 00003143 CP_SCRATCH_REG7: 12611 + :0,12610,12814,12611 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000000b VFD_INDEX_MIN: 11 +!+ 00000011 VFD_INDEX_MAX: 17 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000000b VFD_INDEX_OFFSET: 11 +11847044: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12612 + :0,12610,12814,12612 +11847054: 0000: 0000057f 00003144 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12613 + :0,12613,12814,12612 +1184705c: 0000: 0000057d 00003145 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847064: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184706c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 18 + VFD_INDEX_MAX: 21 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 18 +11847074: 0000: 00032242 00000012 00000015 00000000 00000012 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847088: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12614 + :0,12613,12814,12614 +11847090: 0000: 0000057f 00003146 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 214 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[214] register values +!+ 00003145 CP_SCRATCH_REG5: 12613 + :0,12613,12814,12614 +!+ 00003146 CP_SCRATCH_REG7: 12614 + :0,12613,12814,12614 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000012 VFD_INDEX_MIN: 18 +!+ 00000015 VFD_INDEX_MAX: 21 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000012 VFD_INDEX_OFFSET: 18 +11847098: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12615 + :0,12613,12814,12615 +118470a8: 0000: 0000057f 00003147 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12616 + :0,12616,12814,12615 +118470b0: 0000: 0000057d 00003148 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118470b8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118470c0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 22 + VFD_INDEX_MAX: 25 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 22 +118470c8: 0000: 00032242 00000016 00000019 00000000 00000016 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118470dc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12617 + :0,12616,12814,12617 +118470e4: 0000: 0000057f 00003149 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 215 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[215] register values +!+ 00003148 CP_SCRATCH_REG5: 12616 + :0,12616,12814,12617 +!+ 00003149 CP_SCRATCH_REG7: 12617 + :0,12616,12814,12617 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000016 VFD_INDEX_MIN: 22 +!+ 00000019 VFD_INDEX_MAX: 25 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000016 VFD_INDEX_OFFSET: 22 +118470ec: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12618 + :0,12616,12814,12618 +118470fc: 0000: 0000057f 0000314a +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12619 + :0,12619,12814,12618 +11847104: 0000: 0000057d 0000314b +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184710c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847114: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 26 + VFD_INDEX_MAX: 29 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 26 +1184711c: 0000: 00032242 0000001a 0000001d 00000000 0000001a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847130: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12620 + :0,12619,12814,12620 +11847138: 0000: 0000057f 0000314c +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 216 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[216] register values +!+ 0000314b CP_SCRATCH_REG5: 12619 + :0,12619,12814,12620 +!+ 0000314c CP_SCRATCH_REG7: 12620 + :0,12619,12814,12620 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000001a VFD_INDEX_MIN: 26 +!+ 0000001d VFD_INDEX_MAX: 29 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000001a VFD_INDEX_OFFSET: 26 +11847140: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12621 + :0,12619,12814,12621 +11847150: 0000: 0000057f 0000314d +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12622 + :0,12622,12814,12621 +11847158: 0000: 0000057d 0000314e +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847160: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847168: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 30 + VFD_INDEX_MAX: 33 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 30 +11847170: 0000: 00032242 0000001e 00000021 00000000 0000001e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847184: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12623 + :0,12622,12814,12623 +1184718c: 0000: 0000057f 0000314f +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 217 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[217] register values +!+ 0000314e CP_SCRATCH_REG5: 12622 + :0,12622,12814,12623 +!+ 0000314f CP_SCRATCH_REG7: 12623 + :0,12622,12814,12623 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000001e VFD_INDEX_MIN: 30 +!+ 00000021 VFD_INDEX_MAX: 33 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000001e VFD_INDEX_OFFSET: 30 +11847194: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12624 + :0,12622,12814,12624 +118471a4: 0000: 0000057f 00003150 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12625 + :0,12625,12814,12624 +118471ac: 0000: 0000057d 00003151 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118471b4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118471bc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 34 + VFD_INDEX_MAX: 40 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 34 +118471c4: 0000: 00032242 00000022 00000028 00000000 00000022 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118471d8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12626 + :0,12625,12814,12626 +118471e0: 0000: 0000057f 00003152 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 218 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[218] register values +!+ 00003151 CP_SCRATCH_REG5: 12625 + :0,12625,12814,12626 +!+ 00003152 CP_SCRATCH_REG7: 12626 + :0,12625,12814,12626 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000022 VFD_INDEX_MIN: 34 +!+ 00000028 VFD_INDEX_MAX: 40 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000022 VFD_INDEX_OFFSET: 34 +118471e8: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12627 + :0,12625,12814,12627 +118471f8: 0000: 0000057f 00003153 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12628 + :0,12628,12814,12627 +11847200: 0000: 0000057d 00003154 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847208: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847210: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 41 + VFD_INDEX_MAX: 44 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 41 +11847218: 0000: 00032242 00000029 0000002c 00000000 00000029 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184722c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12629 + :0,12628,12814,12629 +11847234: 0000: 0000057f 00003155 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 219 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[219] register values +!+ 00003154 CP_SCRATCH_REG5: 12628 + :0,12628,12814,12629 +!+ 00003155 CP_SCRATCH_REG7: 12629 + :0,12628,12814,12629 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000029 VFD_INDEX_MIN: 41 +!+ 0000002c VFD_INDEX_MAX: 44 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000029 VFD_INDEX_OFFSET: 41 +1184723c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12630 + :0,12628,12814,12630 +1184724c: 0000: 0000057f 00003156 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12631 + :0,12631,12814,12630 +11847254: 0000: 0000057d 00003157 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184725c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847264: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 45 + VFD_INDEX_MAX: 51 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 45 +1184726c: 0000: 00032242 0000002d 00000033 00000000 0000002d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847280: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12632 + :0,12631,12814,12632 +11847288: 0000: 0000057f 00003158 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 220 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[220] register values +!+ 00003157 CP_SCRATCH_REG5: 12631 + :0,12631,12814,12632 +!+ 00003158 CP_SCRATCH_REG7: 12632 + :0,12631,12814,12632 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000002d VFD_INDEX_MIN: 45 +!+ 00000033 VFD_INDEX_MAX: 51 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000002d VFD_INDEX_OFFSET: 45 +11847290: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12633 + :0,12631,12814,12633 +118472a0: 0000: 0000057f 00003159 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12634 + :0,12634,12814,12633 +118472a8: 0000: 0000057d 0000315a +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118472b0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118472b8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 52 + VFD_INDEX_MAX: 55 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 52 +118472c0: 0000: 00032242 00000034 00000037 00000000 00000034 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118472d4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12635 + :0,12634,12814,12635 +118472dc: 0000: 0000057f 0000315b +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 221 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[221] register values +!+ 0000315a CP_SCRATCH_REG5: 12634 + :0,12634,12814,12635 +!+ 0000315b CP_SCRATCH_REG7: 12635 + :0,12634,12814,12635 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000034 VFD_INDEX_MIN: 52 +!+ 00000037 VFD_INDEX_MAX: 55 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000034 VFD_INDEX_OFFSET: 52 +118472e4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12636 + :0,12634,12814,12636 +118472f4: 0000: 0000057f 0000315c +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12637 + :0,12637,12814,12636 +118472fc: 0000: 0000057d 0000315d +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847304: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184730c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 56 + VFD_INDEX_MAX: 59 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 56 +11847314: 0000: 00032242 00000038 0000003b 00000000 00000038 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847328: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12638 + :0,12637,12814,12638 +11847330: 0000: 0000057f 0000315e +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 222 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[222] register values +!+ 0000315d CP_SCRATCH_REG5: 12637 + :0,12637,12814,12638 +!+ 0000315e CP_SCRATCH_REG7: 12638 + :0,12637,12814,12638 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000038 VFD_INDEX_MIN: 56 +!+ 0000003b VFD_INDEX_MAX: 59 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000038 VFD_INDEX_OFFSET: 56 +11847338: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12639 + :0,12637,12814,12639 +11847348: 0000: 0000057f 0000315f +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12640 + :0,12640,12814,12639 +11847350: 0000: 0000057d 00003160 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847358: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847360: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 60 + VFD_INDEX_MAX: 63 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 60 +11847368: 0000: 00032242 0000003c 0000003f 00000000 0000003c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184737c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12641 + :0,12640,12814,12641 +11847384: 0000: 0000057f 00003161 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 223 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[223] register values +!+ 00003160 CP_SCRATCH_REG5: 12640 + :0,12640,12814,12641 +!+ 00003161 CP_SCRATCH_REG7: 12641 + :0,12640,12814,12641 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000003c VFD_INDEX_MIN: 60 +!+ 0000003f VFD_INDEX_MAX: 63 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000003c VFD_INDEX_OFFSET: 60 +1184738c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12642 + :0,12640,12814,12642 +1184739c: 0000: 0000057f 00003162 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12643 + :0,12643,12814,12642 +118473a4: 0000: 0000057d 00003163 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118473ac: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118473b4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 64 + VFD_INDEX_MAX: 67 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 64 +118473bc: 0000: 00032242 00000040 00000043 00000000 00000040 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118473d0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12644 + :0,12643,12814,12644 +118473d8: 0000: 0000057f 00003164 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 224 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[224] register values +!+ 00003163 CP_SCRATCH_REG5: 12643 + :0,12643,12814,12644 +!+ 00003164 CP_SCRATCH_REG7: 12644 + :0,12643,12814,12644 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000040 VFD_INDEX_MIN: 64 +!+ 00000043 VFD_INDEX_MAX: 67 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000040 VFD_INDEX_OFFSET: 64 +118473e0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12645 + :0,12643,12814,12645 +118473f0: 0000: 0000057f 00003165 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12646 + :0,12646,12814,12645 +118473f8: 0000: 0000057d 00003166 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847400: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847408: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 68 + VFD_INDEX_MAX: 74 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 68 +11847410: 0000: 00032242 00000044 0000004a 00000000 00000044 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847424: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12647 + :0,12646,12814,12647 +1184742c: 0000: 0000057f 00003167 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 225 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[225] register values +!+ 00003166 CP_SCRATCH_REG5: 12646 + :0,12646,12814,12647 +!+ 00003167 CP_SCRATCH_REG7: 12647 + :0,12646,12814,12647 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000044 VFD_INDEX_MIN: 68 +!+ 0000004a VFD_INDEX_MAX: 74 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000044 VFD_INDEX_OFFSET: 68 +11847434: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12648 + :0,12646,12814,12648 +11847444: 0000: 0000057f 00003168 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12649 + :0,12649,12814,12648 +1184744c: 0000: 0000057d 00003169 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847454: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184745c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 75 + VFD_INDEX_MAX: 78 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 75 +11847464: 0000: 00032242 0000004b 0000004e 00000000 0000004b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847478: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12650 + :0,12649,12814,12650 +11847480: 0000: 0000057f 0000316a +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 226 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[226] register values +!+ 00003169 CP_SCRATCH_REG5: 12649 + :0,12649,12814,12650 +!+ 0000316a CP_SCRATCH_REG7: 12650 + :0,12649,12814,12650 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000004b VFD_INDEX_MIN: 75 +!+ 0000004e VFD_INDEX_MAX: 78 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000004b VFD_INDEX_OFFSET: 75 +11847488: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12651 + :0,12649,12814,12651 +11847498: 0000: 0000057f 0000316b +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12652 + :0,12652,12814,12651 +118474a0: 0000: 0000057d 0000316c +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118474a8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118474b0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 79 + VFD_INDEX_MAX: 85 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 79 +118474b8: 0000: 00032242 0000004f 00000055 00000000 0000004f +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118474cc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12653 + :0,12652,12814,12653 +118474d4: 0000: 0000057f 0000316d +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 227 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[227] register values +!+ 0000316c CP_SCRATCH_REG5: 12652 + :0,12652,12814,12653 +!+ 0000316d CP_SCRATCH_REG7: 12653 + :0,12652,12814,12653 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000004f VFD_INDEX_MIN: 79 +!+ 00000055 VFD_INDEX_MAX: 85 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000004f VFD_INDEX_OFFSET: 79 +118474dc: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12654 + :0,12652,12814,12654 +118474ec: 0000: 0000057f 0000316e +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12655 + :0,12655,12814,12654 +118474f4: 0000: 0000057d 0000316f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118474fc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847504: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 86 + VFD_INDEX_MAX: 89 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 86 +1184750c: 0000: 00032242 00000056 00000059 00000000 00000056 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847520: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12656 + :0,12655,12814,12656 +11847528: 0000: 0000057f 00003170 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 228 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[228] register values +!+ 0000316f CP_SCRATCH_REG5: 12655 + :0,12655,12814,12656 +!+ 00003170 CP_SCRATCH_REG7: 12656 + :0,12655,12814,12656 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000056 VFD_INDEX_MIN: 86 +!+ 00000059 VFD_INDEX_MAX: 89 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000056 VFD_INDEX_OFFSET: 86 +11847530: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12657 + :0,12655,12814,12657 +11847540: 0000: 0000057f 00003171 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12658 + :0,12658,12814,12657 +11847548: 0000: 0000057d 00003172 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847550: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847558: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 90 + VFD_INDEX_MAX: 93 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 90 +11847560: 0000: 00032242 0000005a 0000005d 00000000 0000005a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847574: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12659 + :0,12658,12814,12659 +1184757c: 0000: 0000057f 00003173 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 229 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[229] register values +!+ 00003172 CP_SCRATCH_REG5: 12658 + :0,12658,12814,12659 +!+ 00003173 CP_SCRATCH_REG7: 12659 + :0,12658,12814,12659 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000005a VFD_INDEX_MIN: 90 +!+ 0000005d VFD_INDEX_MAX: 93 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000005a VFD_INDEX_OFFSET: 90 +11847584: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12660 + :0,12658,12814,12660 +11847594: 0000: 0000057f 00003174 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12661 + :0,12661,12814,12660 +1184759c: 0000: 0000057d 00003175 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118475a4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118475ac: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 94 + VFD_INDEX_MAX: 97 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 94 +118475b4: 0000: 00032242 0000005e 00000061 00000000 0000005e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118475c8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12662 + :0,12661,12814,12662 +118475d0: 0000: 0000057f 00003176 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 230 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[230] register values +!+ 00003175 CP_SCRATCH_REG5: 12661 + :0,12661,12814,12662 +!+ 00003176 CP_SCRATCH_REG7: 12662 + :0,12661,12814,12662 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000005e VFD_INDEX_MIN: 94 +!+ 00000061 VFD_INDEX_MAX: 97 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000005e VFD_INDEX_OFFSET: 94 +118475d8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12663 + :0,12661,12814,12663 +118475e8: 0000: 0000057f 00003177 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12664 + :0,12664,12814,12663 +118475f0: 0000: 0000057d 00003178 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118475f8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847600: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 98 + VFD_INDEX_MAX: 101 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 98 +11847608: 0000: 00032242 00000062 00000065 00000000 00000062 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184761c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12665 + :0,12664,12814,12665 +11847624: 0000: 0000057f 00003179 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 231 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[231] register values +!+ 00003178 CP_SCRATCH_REG5: 12664 + :0,12664,12814,12665 +!+ 00003179 CP_SCRATCH_REG7: 12665 + :0,12664,12814,12665 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000062 VFD_INDEX_MIN: 98 +!+ 00000065 VFD_INDEX_MAX: 101 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000062 VFD_INDEX_OFFSET: 98 +1184762c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12666 + :0,12664,12814,12666 +1184763c: 0000: 0000057f 0000317a +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12667 + :0,12667,12814,12666 +11847644: 0000: 0000057d 0000317b +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184764c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847654: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 102 + VFD_INDEX_MAX: 108 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 102 +1184765c: 0000: 00032242 00000066 0000006c 00000000 00000066 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847670: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12668 + :0,12667,12814,12668 +11847678: 0000: 0000057f 0000317c +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 232 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[232] register values +!+ 0000317b CP_SCRATCH_REG5: 12667 + :0,12667,12814,12668 +!+ 0000317c CP_SCRATCH_REG7: 12668 + :0,12667,12814,12668 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000066 VFD_INDEX_MIN: 102 +!+ 0000006c VFD_INDEX_MAX: 108 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000066 VFD_INDEX_OFFSET: 102 +11847680: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12669 + :0,12667,12814,12669 +11847690: 0000: 0000057f 0000317d +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12670 + :0,12670,12814,12669 +11847698: 0000: 0000057d 0000317e +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118476a0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118476a8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 109 + VFD_INDEX_MAX: 112 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 109 +118476b0: 0000: 00032242 0000006d 00000070 00000000 0000006d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118476c4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12671 + :0,12670,12814,12671 +118476cc: 0000: 0000057f 0000317f +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 233 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[233] register values +!+ 0000317e CP_SCRATCH_REG5: 12670 + :0,12670,12814,12671 +!+ 0000317f CP_SCRATCH_REG7: 12671 + :0,12670,12814,12671 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000006d VFD_INDEX_MIN: 109 +!+ 00000070 VFD_INDEX_MAX: 112 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000006d VFD_INDEX_OFFSET: 109 +118476d4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12672 + :0,12670,12814,12672 +118476e4: 0000: 0000057f 00003180 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12673 + :0,12673,12814,12672 +118476ec: 0000: 0000057d 00003181 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118476f4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118476fc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 113 + VFD_INDEX_MAX: 119 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 113 +11847704: 0000: 00032242 00000071 00000077 00000000 00000071 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847718: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12674 + :0,12673,12814,12674 +11847720: 0000: 0000057f 00003182 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 234 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[234] register values +!+ 00003181 CP_SCRATCH_REG5: 12673 + :0,12673,12814,12674 +!+ 00003182 CP_SCRATCH_REG7: 12674 + :0,12673,12814,12674 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000071 VFD_INDEX_MIN: 113 +!+ 00000077 VFD_INDEX_MAX: 119 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000071 VFD_INDEX_OFFSET: 113 +11847728: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12675 + :0,12673,12814,12675 +11847738: 0000: 0000057f 00003183 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12676 + :0,12676,12814,12675 +11847740: 0000: 0000057d 00003184 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847748: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847750: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 120 + VFD_INDEX_MAX: 123 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 120 +11847758: 0000: 00032242 00000078 0000007b 00000000 00000078 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184776c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12677 + :0,12676,12814,12677 +11847774: 0000: 0000057f 00003185 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 235 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[235] register values +!+ 00003184 CP_SCRATCH_REG5: 12676 + :0,12676,12814,12677 +!+ 00003185 CP_SCRATCH_REG7: 12677 + :0,12676,12814,12677 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000078 VFD_INDEX_MIN: 120 +!+ 0000007b VFD_INDEX_MAX: 123 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000078 VFD_INDEX_OFFSET: 120 +1184777c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12678 + :0,12676,12814,12678 +1184778c: 0000: 0000057f 00003186 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12679 + :0,12679,12814,12678 +11847794: 0000: 0000057d 00003187 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184779c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118477a4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 124 + VFD_INDEX_MAX: 127 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 124 +118477ac: 0000: 00032242 0000007c 0000007f 00000000 0000007c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118477c0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12680 + :0,12679,12814,12680 +118477c8: 0000: 0000057f 00003188 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 236 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[236] register values +!+ 00003187 CP_SCRATCH_REG5: 12679 + :0,12679,12814,12680 +!+ 00003188 CP_SCRATCH_REG7: 12680 + :0,12679,12814,12680 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000007c VFD_INDEX_MIN: 124 +!+ 0000007f VFD_INDEX_MAX: 127 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000007c VFD_INDEX_OFFSET: 124 +118477d0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12681 + :0,12679,12814,12681 +118477e0: 0000: 0000057f 00003189 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12682 + :0,12682,12814,12681 +118477e8: 0000: 0000057d 0000318a +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118477f0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118477f8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 128 + VFD_INDEX_MAX: 131 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 128 +11847800: 0000: 00032242 00000080 00000083 00000000 00000080 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847814: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12683 + :0,12682,12814,12683 +1184781c: 0000: 0000057f 0000318b +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 237 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[237] register values +!+ 0000318a CP_SCRATCH_REG5: 12682 + :0,12682,12814,12683 +!+ 0000318b CP_SCRATCH_REG7: 12683 + :0,12682,12814,12683 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000080 VFD_INDEX_MIN: 128 +!+ 00000083 VFD_INDEX_MAX: 131 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000080 VFD_INDEX_OFFSET: 128 +11847824: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12684 + :0,12682,12814,12684 +11847834: 0000: 0000057f 0000318c +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12685 + :0,12685,12814,12684 +1184783c: 0000: 0000057d 0000318d +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847844: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184784c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 132 + VFD_INDEX_MAX: 135 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 132 +11847854: 0000: 00032242 00000084 00000087 00000000 00000084 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847868: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12686 + :0,12685,12814,12686 +11847870: 0000: 0000057f 0000318e +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 238 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[238] register values +!+ 0000318d CP_SCRATCH_REG5: 12685 + :0,12685,12814,12686 +!+ 0000318e CP_SCRATCH_REG7: 12686 + :0,12685,12814,12686 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000084 VFD_INDEX_MIN: 132 +!+ 00000087 VFD_INDEX_MAX: 135 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000084 VFD_INDEX_OFFSET: 132 +11847878: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12687 + :0,12685,12814,12687 +11847888: 0000: 0000057f 0000318f +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12688 + :0,12688,12814,12687 +11847890: 0000: 0000057d 00003190 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847898: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118478a0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 136 + VFD_INDEX_MAX: 142 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 136 +118478a8: 0000: 00032242 00000088 0000008e 00000000 00000088 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118478bc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12689 + :0,12688,12814,12689 +118478c4: 0000: 0000057f 00003191 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 239 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[239] register values +!+ 00003190 CP_SCRATCH_REG5: 12688 + :0,12688,12814,12689 +!+ 00003191 CP_SCRATCH_REG7: 12689 + :0,12688,12814,12689 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000088 VFD_INDEX_MIN: 136 +!+ 0000008e VFD_INDEX_MAX: 142 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000088 VFD_INDEX_OFFSET: 136 +118478cc: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12690 + :0,12688,12814,12690 +118478dc: 0000: 0000057f 00003192 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12691 + :0,12691,12814,12690 +118478e4: 0000: 0000057d 00003193 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118478ec: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118478f4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 143 + VFD_INDEX_MAX: 146 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 143 +118478fc: 0000: 00032242 0000008f 00000092 00000000 0000008f +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847910: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12692 + :0,12691,12814,12692 +11847918: 0000: 0000057f 00003194 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 240 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[240] register values +!+ 00003193 CP_SCRATCH_REG5: 12691 + :0,12691,12814,12692 +!+ 00003194 CP_SCRATCH_REG7: 12692 + :0,12691,12814,12692 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000008f VFD_INDEX_MIN: 143 +!+ 00000092 VFD_INDEX_MAX: 146 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000008f VFD_INDEX_OFFSET: 143 +11847920: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12693 + :0,12691,12814,12693 +11847930: 0000: 0000057f 00003195 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12694 + :0,12694,12814,12693 +11847938: 0000: 0000057d 00003196 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847940: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847948: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 147 + VFD_INDEX_MAX: 153 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 147 +11847950: 0000: 00032242 00000093 00000099 00000000 00000093 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847964: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12695 + :0,12694,12814,12695 +1184796c: 0000: 0000057f 00003197 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 241 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[241] register values +!+ 00003196 CP_SCRATCH_REG5: 12694 + :0,12694,12814,12695 +!+ 00003197 CP_SCRATCH_REG7: 12695 + :0,12694,12814,12695 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000093 VFD_INDEX_MIN: 147 +!+ 00000099 VFD_INDEX_MAX: 153 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000093 VFD_INDEX_OFFSET: 147 +11847974: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12696 + :0,12694,12814,12696 +11847984: 0000: 0000057f 00003198 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12697 + :0,12697,12814,12696 +1184798c: 0000: 0000057d 00003199 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847994: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184799c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 154 + VFD_INDEX_MAX: 157 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 154 +118479a4: 0000: 00032242 0000009a 0000009d 00000000 0000009a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118479b8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12698 + :0,12697,12814,12698 +118479c0: 0000: 0000057f 0000319a +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 242 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[242] register values +!+ 00003199 CP_SCRATCH_REG5: 12697 + :0,12697,12814,12698 +!+ 0000319a CP_SCRATCH_REG7: 12698 + :0,12697,12814,12698 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000009a VFD_INDEX_MIN: 154 +!+ 0000009d VFD_INDEX_MAX: 157 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000009a VFD_INDEX_OFFSET: 154 +118479c8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12699 + :0,12697,12814,12699 +118479d8: 0000: 0000057f 0000319b +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12700 + :0,12700,12814,12699 +118479e0: 0000: 0000057d 0000319c +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118479e8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118479f0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 158 + VFD_INDEX_MAX: 161 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 158 +118479f8: 0000: 00032242 0000009e 000000a1 00000000 0000009e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847a0c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12701 + :0,12700,12814,12701 +11847a14: 0000: 0000057f 0000319d +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 243 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[243] register values +!+ 0000319c CP_SCRATCH_REG5: 12700 + :0,12700,12814,12701 +!+ 0000319d CP_SCRATCH_REG7: 12701 + :0,12700,12814,12701 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000009e VFD_INDEX_MIN: 158 +!+ 000000a1 VFD_INDEX_MAX: 161 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000009e VFD_INDEX_OFFSET: 158 +11847a1c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12702 + :0,12700,12814,12702 +11847a2c: 0000: 0000057f 0000319e +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12703 + :0,12703,12814,12702 +11847a34: 0000: 0000057d 0000319f +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847a3c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847a44: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 162 + VFD_INDEX_MAX: 165 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 162 +11847a4c: 0000: 00032242 000000a2 000000a5 00000000 000000a2 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847a60: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12704 + :0,12703,12814,12704 +11847a68: 0000: 0000057f 000031a0 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 244 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[244] register values +!+ 0000319f CP_SCRATCH_REG5: 12703 + :0,12703,12814,12704 +!+ 000031a0 CP_SCRATCH_REG7: 12704 + :0,12703,12814,12704 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000a2 VFD_INDEX_MIN: 162 +!+ 000000a5 VFD_INDEX_MAX: 165 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000a2 VFD_INDEX_OFFSET: 162 +11847a70: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12705 + :0,12703,12814,12705 +11847a80: 0000: 0000057f 000031a1 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12706 + :0,12706,12814,12705 +11847a88: 0000: 0000057d 000031a2 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847a90: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847a98: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 166 + VFD_INDEX_MAX: 169 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 166 +11847aa0: 0000: 00032242 000000a6 000000a9 00000000 000000a6 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847ab4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12707 + :0,12706,12814,12707 +11847abc: 0000: 0000057f 000031a3 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 245 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[245] register values +!+ 000031a2 CP_SCRATCH_REG5: 12706 + :0,12706,12814,12707 +!+ 000031a3 CP_SCRATCH_REG7: 12707 + :0,12706,12814,12707 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000a6 VFD_INDEX_MIN: 166 +!+ 000000a9 VFD_INDEX_MAX: 169 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000a6 VFD_INDEX_OFFSET: 166 +11847ac4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12708 + :0,12706,12814,12708 +11847ad4: 0000: 0000057f 000031a4 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12709 + :0,12709,12814,12708 +11847adc: 0000: 0000057d 000031a5 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847ae4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847aec: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 170 + VFD_INDEX_MAX: 176 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 170 +11847af4: 0000: 00032242 000000aa 000000b0 00000000 000000aa +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847b08: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12710 + :0,12709,12814,12710 +11847b10: 0000: 0000057f 000031a6 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 246 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[246] register values +!+ 000031a5 CP_SCRATCH_REG5: 12709 + :0,12709,12814,12710 +!+ 000031a6 CP_SCRATCH_REG7: 12710 + :0,12709,12814,12710 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000aa VFD_INDEX_MIN: 170 +!+ 000000b0 VFD_INDEX_MAX: 176 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000aa VFD_INDEX_OFFSET: 170 +11847b18: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12711 + :0,12709,12814,12711 +11847b28: 0000: 0000057f 000031a7 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12712 + :0,12712,12814,12711 +11847b30: 0000: 0000057d 000031a8 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847b38: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847b40: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 177 + VFD_INDEX_MAX: 180 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 177 +11847b48: 0000: 00032242 000000b1 000000b4 00000000 000000b1 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847b5c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12713 + :0,12712,12814,12713 +11847b64: 0000: 0000057f 000031a9 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 247 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[247] register values +!+ 000031a8 CP_SCRATCH_REG5: 12712 + :0,12712,12814,12713 +!+ 000031a9 CP_SCRATCH_REG7: 12713 + :0,12712,12814,12713 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000b1 VFD_INDEX_MIN: 177 +!+ 000000b4 VFD_INDEX_MAX: 180 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000b1 VFD_INDEX_OFFSET: 177 +11847b6c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12714 + :0,12712,12814,12714 +11847b7c: 0000: 0000057f 000031aa +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12715 + :0,12715,12814,12714 +11847b84: 0000: 0000057d 000031ab +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847b8c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847b94: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 181 + VFD_INDEX_MAX: 187 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 181 +11847b9c: 0000: 00032242 000000b5 000000bb 00000000 000000b5 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847bb0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12716 + :0,12715,12814,12716 +11847bb8: 0000: 0000057f 000031ac +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 248 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[248] register values +!+ 000031ab CP_SCRATCH_REG5: 12715 + :0,12715,12814,12716 +!+ 000031ac CP_SCRATCH_REG7: 12716 + :0,12715,12814,12716 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000b5 VFD_INDEX_MIN: 181 +!+ 000000bb VFD_INDEX_MAX: 187 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000b5 VFD_INDEX_OFFSET: 181 +11847bc0: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12717 + :0,12715,12814,12717 +11847bd0: 0000: 0000057f 000031ad +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12718 + :0,12718,12814,12717 +11847bd8: 0000: 0000057d 000031ae +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847be0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847be8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 188 + VFD_INDEX_MAX: 191 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 188 +11847bf0: 0000: 00032242 000000bc 000000bf 00000000 000000bc +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847c04: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12719 + :0,12718,12814,12719 +11847c0c: 0000: 0000057f 000031af +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 249 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[249] register values +!+ 000031ae CP_SCRATCH_REG5: 12718 + :0,12718,12814,12719 +!+ 000031af CP_SCRATCH_REG7: 12719 + :0,12718,12814,12719 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000bc VFD_INDEX_MIN: 188 +!+ 000000bf VFD_INDEX_MAX: 191 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000bc VFD_INDEX_OFFSET: 188 +11847c14: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12720 + :0,12718,12814,12720 +11847c24: 0000: 0000057f 000031b0 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12721 + :0,12721,12814,12720 +11847c2c: 0000: 0000057d 000031b1 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847c34: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847c3c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 192 + VFD_INDEX_MAX: 195 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 192 +11847c44: 0000: 00032242 000000c0 000000c3 00000000 000000c0 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847c58: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12722 + :0,12721,12814,12722 +11847c60: 0000: 0000057f 000031b2 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 250 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[250] register values +!+ 000031b1 CP_SCRATCH_REG5: 12721 + :0,12721,12814,12722 +!+ 000031b2 CP_SCRATCH_REG7: 12722 + :0,12721,12814,12722 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000c0 VFD_INDEX_MIN: 192 +!+ 000000c3 VFD_INDEX_MAX: 195 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000c0 VFD_INDEX_OFFSET: 192 +11847c68: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12723 + :0,12721,12814,12723 +11847c78: 0000: 0000057f 000031b3 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12724 + :0,12724,12814,12723 +11847c80: 0000: 0000057d 000031b4 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847c88: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847c90: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 196 + VFD_INDEX_MAX: 199 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 196 +11847c98: 0000: 00032242 000000c4 000000c7 00000000 000000c4 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847cac: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12725 + :0,12724,12814,12725 +11847cb4: 0000: 0000057f 000031b5 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 251 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[251] register values +!+ 000031b4 CP_SCRATCH_REG5: 12724 + :0,12724,12814,12725 +!+ 000031b5 CP_SCRATCH_REG7: 12725 + :0,12724,12814,12725 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000c4 VFD_INDEX_MIN: 196 +!+ 000000c7 VFD_INDEX_MAX: 199 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000c4 VFD_INDEX_OFFSET: 196 +11847cbc: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12726 + :0,12724,12814,12726 +11847ccc: 0000: 0000057f 000031b6 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12727 + :0,12727,12814,12726 +11847cd4: 0000: 0000057d 000031b7 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847cdc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847ce4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 200 + VFD_INDEX_MAX: 203 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 200 +11847cec: 0000: 00032242 000000c8 000000cb 00000000 000000c8 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847d00: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12728 + :0,12727,12814,12728 +11847d08: 0000: 0000057f 000031b8 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 252 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[252] register values +!+ 000031b7 CP_SCRATCH_REG5: 12727 + :0,12727,12814,12728 +!+ 000031b8 CP_SCRATCH_REG7: 12728 + :0,12727,12814,12728 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000c8 VFD_INDEX_MIN: 200 +!+ 000000cb VFD_INDEX_MAX: 203 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000c8 VFD_INDEX_OFFSET: 200 +11847d10: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12729 + :0,12727,12814,12729 +11847d20: 0000: 0000057f 000031b9 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12730 + :0,12730,12814,12729 +11847d28: 0000: 0000057d 000031ba +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847d30: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847d38: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 204 + VFD_INDEX_MAX: 210 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 204 +11847d40: 0000: 00032242 000000cc 000000d2 00000000 000000cc +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847d54: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12731 + :0,12730,12814,12731 +11847d5c: 0000: 0000057f 000031bb +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 253 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[253] register values +!+ 000031ba CP_SCRATCH_REG5: 12730 + :0,12730,12814,12731 +!+ 000031bb CP_SCRATCH_REG7: 12731 + :0,12730,12814,12731 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000cc VFD_INDEX_MIN: 204 +!+ 000000d2 VFD_INDEX_MAX: 210 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000cc VFD_INDEX_OFFSET: 204 +11847d64: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12732 + :0,12730,12814,12732 +11847d74: 0000: 0000057f 000031bc +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12733 + :0,12733,12814,12732 +11847d7c: 0000: 0000057d 000031bd +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847d84: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847d8c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 211 + VFD_INDEX_MAX: 214 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 211 +11847d94: 0000: 00032242 000000d3 000000d6 00000000 000000d3 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847da8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12734 + :0,12733,12814,12734 +11847db0: 0000: 0000057f 000031be +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 254 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[254] register values +!+ 000031bd CP_SCRATCH_REG5: 12733 + :0,12733,12814,12734 +!+ 000031be CP_SCRATCH_REG7: 12734 + :0,12733,12814,12734 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000d3 VFD_INDEX_MIN: 211 +!+ 000000d6 VFD_INDEX_MAX: 214 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000d3 VFD_INDEX_OFFSET: 211 +11847db8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12735 + :0,12733,12814,12735 +11847dc8: 0000: 0000057f 000031bf +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12736 + :0,12736,12814,12735 +11847dd0: 0000: 0000057d 000031c0 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847dd8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847de0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 215 + VFD_INDEX_MAX: 221 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 215 +11847de8: 0000: 00032242 000000d7 000000dd 00000000 000000d7 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847dfc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12737 + :0,12736,12814,12737 +11847e04: 0000: 0000057f 000031c1 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 255 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[255] register values +!+ 000031c0 CP_SCRATCH_REG5: 12736 + :0,12736,12814,12737 +!+ 000031c1 CP_SCRATCH_REG7: 12737 + :0,12736,12814,12737 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000d7 VFD_INDEX_MIN: 215 +!+ 000000dd VFD_INDEX_MAX: 221 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000d7 VFD_INDEX_OFFSET: 215 +11847e0c: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12738 + :0,12736,12814,12738 +11847e1c: 0000: 0000057f 000031c2 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12739 + :0,12739,12814,12738 +11847e24: 0000: 0000057d 000031c3 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847e2c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847e34: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 222 + VFD_INDEX_MAX: 225 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 222 +11847e3c: 0000: 00032242 000000de 000000e1 00000000 000000de +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847e50: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12740 + :0,12739,12814,12740 +11847e58: 0000: 0000057f 000031c4 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 256 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[256] register values +!+ 000031c3 CP_SCRATCH_REG5: 12739 + :0,12739,12814,12740 +!+ 000031c4 CP_SCRATCH_REG7: 12740 + :0,12739,12814,12740 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000de VFD_INDEX_MIN: 222 +!+ 000000e1 VFD_INDEX_MAX: 225 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000de VFD_INDEX_OFFSET: 222 +11847e60: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12741 + :0,12739,12814,12741 +11847e70: 0000: 0000057f 000031c5 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12742 + :0,12742,12814,12741 +11847e78: 0000: 0000057d 000031c6 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847e80: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847e88: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 226 + VFD_INDEX_MAX: 229 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 226 +11847e90: 0000: 00032242 000000e2 000000e5 00000000 000000e2 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847ea4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12743 + :0,12742,12814,12743 +11847eac: 0000: 0000057f 000031c7 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 257 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[257] register values +!+ 000031c6 CP_SCRATCH_REG5: 12742 + :0,12742,12814,12743 +!+ 000031c7 CP_SCRATCH_REG7: 12743 + :0,12742,12814,12743 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000e2 VFD_INDEX_MIN: 226 +!+ 000000e5 VFD_INDEX_MAX: 229 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000e2 VFD_INDEX_OFFSET: 226 +11847eb4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12744 + :0,12742,12814,12744 +11847ec4: 0000: 0000057f 000031c8 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12745 + :0,12745,12814,12744 +11847ecc: 0000: 0000057d 000031c9 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847ed4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847edc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 230 + VFD_INDEX_MAX: 233 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 230 +11847ee4: 0000: 00032242 000000e6 000000e9 00000000 000000e6 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847ef8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12746 + :0,12745,12814,12746 +11847f00: 0000: 0000057f 000031ca +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 258 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[258] register values +!+ 000031c9 CP_SCRATCH_REG5: 12745 + :0,12745,12814,12746 +!+ 000031ca CP_SCRATCH_REG7: 12746 + :0,12745,12814,12746 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000e6 VFD_INDEX_MIN: 230 +!+ 000000e9 VFD_INDEX_MAX: 233 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000e6 VFD_INDEX_OFFSET: 230 +11847f08: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12747 + :0,12745,12814,12747 +11847f18: 0000: 0000057f 000031cb +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12748 + :0,12748,12814,12747 +11847f20: 0000: 0000057d 000031cc +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847f28: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847f30: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 234 + VFD_INDEX_MAX: 237 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 234 +11847f38: 0000: 00032242 000000ea 000000ed 00000000 000000ea +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847f4c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12749 + :0,12748,12814,12749 +11847f54: 0000: 0000057f 000031cd +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 259 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[259] register values +!+ 000031cc CP_SCRATCH_REG5: 12748 + :0,12748,12814,12749 +!+ 000031cd CP_SCRATCH_REG7: 12749 + :0,12748,12814,12749 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000ea VFD_INDEX_MIN: 234 +!+ 000000ed VFD_INDEX_MAX: 237 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000ea VFD_INDEX_OFFSET: 234 +11847f5c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12750 + :0,12748,12814,12750 +11847f6c: 0000: 0000057f 000031ce +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12751 + :0,12751,12814,12750 +11847f74: 0000: 0000057d 000031cf +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847f7c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847f84: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 238 + VFD_INDEX_MAX: 244 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 238 +11847f8c: 0000: 00032242 000000ee 000000f4 00000000 000000ee +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847fa0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12752 + :0,12751,12814,12752 +11847fa8: 0000: 0000057f 000031d0 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 260 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[260] register values +!+ 000031cf CP_SCRATCH_REG5: 12751 + :0,12751,12814,12752 +!+ 000031d0 CP_SCRATCH_REG7: 12752 + :0,12751,12814,12752 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000ee VFD_INDEX_MIN: 238 +!+ 000000f4 VFD_INDEX_MAX: 244 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000ee VFD_INDEX_OFFSET: 238 +11847fb0: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12753 + :0,12751,12814,12753 +11847fc0: 0000: 0000057f 000031d1 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12754 + :0,12754,12814,12753 +11847fc8: 0000: 0000057d 000031d2 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11847fd0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11847fd8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 245 + VFD_INDEX_MAX: 248 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 245 +11847fe0: 0000: 00032242 000000f5 000000f8 00000000 000000f5 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11847ff4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12755 + :0,12754,12814,12755 +11847ffc: 0000: 0000057f 000031d3 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 261 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[261] register values +!+ 000031d2 CP_SCRATCH_REG5: 12754 + :0,12754,12814,12755 +!+ 000031d3 CP_SCRATCH_REG7: 12755 + :0,12754,12814,12755 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000f5 VFD_INDEX_MIN: 245 +!+ 000000f8 VFD_INDEX_MAX: 248 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000f5 VFD_INDEX_OFFSET: 245 +11848004: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12756 + :0,12754,12814,12756 +11848014: 0000: 0000057f 000031d4 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12757 + :0,12757,12814,12756 +1184801c: 0000: 0000057d 000031d5 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11848024: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184802c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 249 + VFD_INDEX_MAX: 255 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 249 +11848034: 0000: 00032242 000000f9 000000ff 00000000 000000f9 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11848048: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12758 + :0,12757,12814,12758 +11848050: 0000: 0000057f 000031d6 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 262 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[262] register values +!+ 000031d5 CP_SCRATCH_REG5: 12757 + :0,12757,12814,12758 +!+ 000031d6 CP_SCRATCH_REG7: 12758 + :0,12757,12814,12758 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 000000f9 VFD_INDEX_MIN: 249 +!+ 000000ff VFD_INDEX_MAX: 255 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 000000f9 VFD_INDEX_OFFSET: 249 +11848058: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12759 + :0,12757,12814,12759 +11848068: 0000: 0000057f 000031d7 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12760 + :0,12760,12814,12759 +11848070: 0000: 0000057d 000031d8 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11848078: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11848080: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 256 + VFD_INDEX_MAX: 259 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 256 +11848088: 0000: 00032242 00000100 00000103 00000000 00000100 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184809c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12761 + :0,12760,12814,12761 +118480a4: 0000: 0000057f 000031d9 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 263 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[263] register values +!+ 000031d8 CP_SCRATCH_REG5: 12760 + :0,12760,12814,12761 +!+ 000031d9 CP_SCRATCH_REG7: 12761 + :0,12760,12814,12761 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000100 VFD_INDEX_MIN: 256 +!+ 00000103 VFD_INDEX_MAX: 259 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000100 VFD_INDEX_OFFSET: 256 +118480ac: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12762 + :0,12760,12814,12762 +118480bc: 0000: 0000057f 000031da +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12763 + :0,12763,12814,12762 +118480c4: 0000: 0000057d 000031db +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118480cc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118480d4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 260 + VFD_INDEX_MAX: 263 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 260 +118480dc: 0000: 00032242 00000104 00000107 00000000 00000104 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118480f0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12764 + :0,12763,12814,12764 +118480f8: 0000: 0000057f 000031dc +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 264 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[264] register values +!+ 000031db CP_SCRATCH_REG5: 12763 + :0,12763,12814,12764 +!+ 000031dc CP_SCRATCH_REG7: 12764 + :0,12763,12814,12764 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000104 VFD_INDEX_MIN: 260 +!+ 00000107 VFD_INDEX_MAX: 263 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000104 VFD_INDEX_OFFSET: 260 +11848100: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12765 + :0,12763,12814,12765 +11848110: 0000: 0000057f 000031dd +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12766 + :0,12766,12814,12765 +11848118: 0000: 0000057d 000031de +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11848120: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11848128: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 264 + VFD_INDEX_MAX: 267 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 264 +11848130: 0000: 00032242 00000108 0000010b 00000000 00000108 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11848144: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12767 + :0,12766,12814,12767 +1184814c: 0000: 0000057f 000031df +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 265 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[265] register values +!+ 000031de CP_SCRATCH_REG5: 12766 + :0,12766,12814,12767 +!+ 000031df CP_SCRATCH_REG7: 12767 + :0,12766,12814,12767 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000108 VFD_INDEX_MIN: 264 +!+ 0000010b VFD_INDEX_MAX: 267 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000108 VFD_INDEX_OFFSET: 264 +11848154: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12768 + :0,12766,12814,12768 +11848164: 0000: 0000057f 000031e0 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12769 + :0,12769,12814,12768 +1184816c: 0000: 0000057d 000031e1 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11848174: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184817c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 268 + VFD_INDEX_MAX: 271 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 268 +11848184: 0000: 00032242 0000010c 0000010f 00000000 0000010c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11848198: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12770 + :0,12769,12814,12770 +118481a0: 0000: 0000057f 000031e2 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 266 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[266] register values +!+ 000031e1 CP_SCRATCH_REG5: 12769 + :0,12769,12814,12770 +!+ 000031e2 CP_SCRATCH_REG7: 12770 + :0,12769,12814,12770 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000010c VFD_INDEX_MIN: 268 +!+ 0000010f VFD_INDEX_MAX: 271 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000010c VFD_INDEX_OFFSET: 268 +118481a8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12771 + :0,12769,12814,12771 +118481b8: 0000: 0000057f 000031e3 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12772 + :0,12772,12814,12771 +118481c0: 0000: 0000057d 000031e4 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118481c8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118481d0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 272 + VFD_INDEX_MAX: 278 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 272 +118481d8: 0000: 00032242 00000110 00000116 00000000 00000110 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118481ec: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12773 + :0,12772,12814,12773 +118481f4: 0000: 0000057f 000031e5 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 267 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[267] register values +!+ 000031e4 CP_SCRATCH_REG5: 12772 + :0,12772,12814,12773 +!+ 000031e5 CP_SCRATCH_REG7: 12773 + :0,12772,12814,12773 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000110 VFD_INDEX_MIN: 272 +!+ 00000116 VFD_INDEX_MAX: 278 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000110 VFD_INDEX_OFFSET: 272 +118481fc: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12774 + :0,12772,12814,12774 +1184820c: 0000: 0000057f 000031e6 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12775 + :0,12775,12814,12774 +11848214: 0000: 0000057d 000031e7 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184821c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11848224: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 279 + VFD_INDEX_MAX: 282 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 279 +1184822c: 0000: 00032242 00000117 0000011a 00000000 00000117 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11848240: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12776 + :0,12775,12814,12776 +11848248: 0000: 0000057f 000031e8 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 268 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[268] register values +!+ 000031e7 CP_SCRATCH_REG5: 12775 + :0,12775,12814,12776 +!+ 000031e8 CP_SCRATCH_REG7: 12776 + :0,12775,12814,12776 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000117 VFD_INDEX_MIN: 279 +!+ 0000011a VFD_INDEX_MAX: 282 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000117 VFD_INDEX_OFFSET: 279 +11848250: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12777 + :0,12775,12814,12777 +11848260: 0000: 0000057f 000031e9 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12778 + :0,12778,12814,12777 +11848268: 0000: 0000057d 000031ea +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11848270: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11848278: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 283 + VFD_INDEX_MAX: 289 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 283 +11848280: 0000: 00032242 0000011b 00000121 00000000 0000011b +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11848294: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12779 + :0,12778,12814,12779 +1184829c: 0000: 0000057f 000031eb +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 269 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[269] register values +!+ 000031ea CP_SCRATCH_REG5: 12778 + :0,12778,12814,12779 +!+ 000031eb CP_SCRATCH_REG7: 12779 + :0,12778,12814,12779 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000011b VFD_INDEX_MIN: 283 +!+ 00000121 VFD_INDEX_MAX: 289 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000011b VFD_INDEX_OFFSET: 283 +118482a4: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12780 + :0,12778,12814,12780 +118482b4: 0000: 0000057f 000031ec +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12781 + :0,12781,12814,12780 +118482bc: 0000: 0000057d 000031ed +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118482c4: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118482cc: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 290 + VFD_INDEX_MAX: 293 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 290 +118482d4: 0000: 00032242 00000122 00000125 00000000 00000122 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118482e8: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12782 + :0,12781,12814,12782 +118482f0: 0000: 0000057f 000031ee +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 270 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[270] register values +!+ 000031ed CP_SCRATCH_REG5: 12781 + :0,12781,12814,12782 +!+ 000031ee CP_SCRATCH_REG7: 12782 + :0,12781,12814,12782 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000122 VFD_INDEX_MIN: 290 +!+ 00000125 VFD_INDEX_MAX: 293 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000122 VFD_INDEX_OFFSET: 290 +118482f8: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12783 + :0,12781,12814,12783 +11848308: 0000: 0000057f 000031ef +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12784 + :0,12784,12814,12783 +11848310: 0000: 0000057d 000031f0 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11848318: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11848320: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 294 + VFD_INDEX_MAX: 297 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 294 +11848328: 0000: 00032242 00000126 00000129 00000000 00000126 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184833c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12785 + :0,12784,12814,12785 +11848344: 0000: 0000057f 000031f1 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 271 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[271] register values +!+ 000031f0 CP_SCRATCH_REG5: 12784 + :0,12784,12814,12785 +!+ 000031f1 CP_SCRATCH_REG7: 12785 + :0,12784,12814,12785 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000126 VFD_INDEX_MIN: 294 +!+ 00000129 VFD_INDEX_MAX: 297 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000126 VFD_INDEX_OFFSET: 294 +1184834c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12786 + :0,12784,12814,12786 +1184835c: 0000: 0000057f 000031f2 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12787 + :0,12787,12814,12786 +11848364: 0000: 0000057d 000031f3 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184836c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11848374: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 298 + VFD_INDEX_MAX: 301 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 298 +1184837c: 0000: 00032242 0000012a 0000012d 00000000 0000012a +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11848390: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12788 + :0,12787,12814,12788 +11848398: 0000: 0000057f 000031f4 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 272 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[272] register values +!+ 000031f3 CP_SCRATCH_REG5: 12787 + :0,12787,12814,12788 +!+ 000031f4 CP_SCRATCH_REG7: 12788 + :0,12787,12814,12788 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000012a VFD_INDEX_MIN: 298 +!+ 0000012d VFD_INDEX_MAX: 301 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000012a VFD_INDEX_OFFSET: 298 +118483a0: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12789 + :0,12787,12814,12789 +118483b0: 0000: 0000057f 000031f5 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12790 + :0,12790,12814,12789 +118483b8: 0000: 0000057d 000031f6 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118483c0: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118483c8: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 302 + VFD_INDEX_MAX: 305 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 302 +118483d0: 0000: 00032242 0000012e 00000131 00000000 0000012e +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118483e4: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12791 + :0,12790,12814,12791 +118483ec: 0000: 0000057f 000031f7 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 273 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[273] register values +!+ 000031f6 CP_SCRATCH_REG5: 12790 + :0,12790,12814,12791 +!+ 000031f7 CP_SCRATCH_REG7: 12791 + :0,12790,12814,12791 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000012e VFD_INDEX_MIN: 302 +!+ 00000131 VFD_INDEX_MAX: 305 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000012e VFD_INDEX_OFFSET: 302 +118483f4: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12792 + :0,12790,12814,12792 +11848404: 0000: 0000057f 000031f8 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12793 + :0,12793,12814,12792 +1184840c: 0000: 0000057d 000031f9 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11848414: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184841c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 306 + VFD_INDEX_MAX: 312 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 306 +11848424: 0000: 00032242 00000132 00000138 00000000 00000132 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11848438: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12794 + :0,12793,12814,12794 +11848440: 0000: 0000057f 000031fa +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 274 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[274] register values +!+ 000031f9 CP_SCRATCH_REG5: 12793 + :0,12793,12814,12794 +!+ 000031fa CP_SCRATCH_REG7: 12794 + :0,12793,12814,12794 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000132 VFD_INDEX_MIN: 306 +!+ 00000138 VFD_INDEX_MAX: 312 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000132 VFD_INDEX_OFFSET: 306 +11848448: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12795 + :0,12793,12814,12795 +11848458: 0000: 0000057f 000031fb +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12796 + :0,12796,12814,12795 +11848460: 0000: 0000057d 000031fc +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11848468: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11848470: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 313 + VFD_INDEX_MAX: 316 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 313 +11848478: 0000: 00032242 00000139 0000013c 00000000 00000139 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +1184848c: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12797 + :0,12796,12814,12797 +11848494: 0000: 0000057f 000031fd +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 275 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[275] register values +!+ 000031fc CP_SCRATCH_REG5: 12796 + :0,12796,12814,12797 +!+ 000031fd CP_SCRATCH_REG7: 12797 + :0,12796,12814,12797 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000139 VFD_INDEX_MIN: 313 +!+ 0000013c VFD_INDEX_MAX: 316 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000139 VFD_INDEX_OFFSET: 313 +1184849c: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12798 + :0,12796,12814,12798 +118484ac: 0000: 0000057f 000031fe +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12799 + :0,12799,12814,12798 +118484b4: 0000: 0000057d 000031ff +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118484bc: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118484c4: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 317 + VFD_INDEX_MAX: 323 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 317 +118484cc: 0000: 00032242 0000013d 00000143 00000000 0000013d +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118484e0: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12800 + :0,12799,12814,12800 +118484e8: 0000: 0000057f 00003200 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 7 } + draw: 276 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 7 + draw[276] register values +!+ 000031ff CP_SCRATCH_REG5: 12799 + :0,12799,12814,12800 +!+ 00003200 CP_SCRATCH_REG7: 12800 + :0,12799,12814,12800 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000013d VFD_INDEX_MIN: 317 +!+ 00000143 VFD_INDEX_MAX: 323 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000013d VFD_INDEX_OFFSET: 317 +118484f0: 0000: c0022200 00000000 00004086 00000007 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12801 + :0,12799,12814,12801 +11848500: 0000: 0000057f 00003201 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12802 + :0,12802,12814,12801 +11848508: 0000: 0000057d 00003202 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11848510: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11848518: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 324 + VFD_INDEX_MAX: 327 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 324 +11848520: 0000: 00032242 00000144 00000147 00000000 00000144 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11848534: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12803 + :0,12802,12814,12803 +1184853c: 0000: 0000057f 00003203 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 277 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[277] register values +!+ 00003202 CP_SCRATCH_REG5: 12802 + :0,12802,12814,12803 +!+ 00003203 CP_SCRATCH_REG7: 12803 + :0,12802,12814,12803 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000144 VFD_INDEX_MIN: 324 +!+ 00000147 VFD_INDEX_MAX: 327 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000144 VFD_INDEX_OFFSET: 324 +11848544: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12804 + :0,12802,12814,12804 +11848554: 0000: 0000057f 00003204 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12805 + :0,12805,12814,12804 +1184855c: 0000: 0000057d 00003205 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +11848564: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +1184856c: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 328 + VFD_INDEX_MAX: 331 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 328 +11848574: 0000: 00032242 00000148 0000014b 00000000 00000148 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11848588: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12806 + :0,12805,12814,12806 +11848590: 0000: 0000057f 00003206 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 278 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[278] register values +!+ 00003205 CP_SCRATCH_REG5: 12805 + :0,12805,12814,12806 +!+ 00003206 CP_SCRATCH_REG7: 12806 + :0,12805,12814,12806 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000148 VFD_INDEX_MIN: 328 +!+ 0000014b VFD_INDEX_MAX: 331 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000148 VFD_INDEX_OFFSET: 328 +11848598: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12807 + :0,12805,12814,12807 +118485a8: 0000: 0000057f 00003207 +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12808 + :0,12808,12814,12807 +118485b0: 0000: 0000057d 00003208 +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +118485b8: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +118485c0: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 332 + VFD_INDEX_MAX: 335 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 332 +118485c8: 0000: 00032242 0000014c 0000014f 00000000 0000014c +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +118485dc: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12809 + :0,12808,12814,12809 +118485e4: 0000: 0000057f 00003209 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 279 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[279] register values +!+ 00003208 CP_SCRATCH_REG5: 12808 + :0,12808,12814,12809 +!+ 00003209 CP_SCRATCH_REG7: 12809 + :0,12808,12814,12809 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 0000014c VFD_INDEX_MIN: 332 +!+ 0000014f VFD_INDEX_MAX: 335 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 0000014c VFD_INDEX_OFFSET: 332 +118485ec: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12810 + :0,12808,12814,12810 +118485fc: 0000: 0000057f 0000320a +t0 write CP_SCRATCH_REG5 (057d) +NEEDS WFI: CP_SCRATCH_REG5 (57d) + CP_SCRATCH_REG5: 12811 + :0,12811,12814,12810 +11848604: 0000: 0000057d 0000320b +t0 write PC_VERTEX_REUSE_BLOCK_CNTL (21ea) + PC_VERTEX_REUSE_BLOCK_CNTL: 0xb +1184860c: 0000: 000021ea 0000000b +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +11848614: 0000: c0002600 00000000 +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 336 + VFD_INDEX_MAX: 339 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 336 +1184861c: 0000: 00032242 00000150 00000153 00000000 00000150 +t0 write PC_RESTART_INDEX (21ed) + PC_RESTART_INDEX: 0xffffffff +11848630: 0000: 000021ed ffffffff +t0 write CP_SCRATCH_REG7 (057f) + CP_SCRATCH_REG7: 12812 + :0,12811,12814,12812 +11848638: 0000: 0000057f 0000320c +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 4 } + draw: 280 + prim_type: DI_PT_TRISTRIP (6) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 4 + draw[280] register values +!+ 0000320b CP_SCRATCH_REG5: 12811 + :0,12811,12814,12812 +!+ 0000320c CP_SCRATCH_REG7: 12812 + :0,12811,12814,12812 + + 0000000b PC_VERTEX_REUSE_BLOCK_CNTL: 0xb + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 00000150 VFD_INDEX_MIN: 336 +!+ 00000153 VFD_INDEX_MAX: 339 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000150 VFD_INDEX_OFFSET: 336 +11848640: 0000: c0022200 00000000 00004086 00000004 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12813 + :0,12811,12814,12813 +11848650: 0000: 0000057f 0000320d +11848920: 0000: c0013700 11842370 000018ba +t0 write CP_SCRATCH_REG6 (057e) +NEEDS WFI: CP_SCRATCH_REG6 (57e) + CP_SCRATCH_REG6: 12815 + :0,12811,12815,12813 +1184892c: 0000: 0000057e 0000320f +t0 write RB_DEPTH_CONTROL (2100) + RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } +11848934: 0000: 00002100 00000000 +t0 write RB_STENCIL_CONTROL (2104) + RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } +1184893c: 0000: 00002104 00000000 +t0 write RB_STENCILREFMASK (2108) + RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } + RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } +11848944: 0000: 00012108 ffff0000 ffff0000 +t0 write GRAS_SU_MODE_CONTROL (2070) + GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } +11848950: 0000: 00002070 00000000 +t0 write GRAS_CL_CLIP_CNTL (2040) + GRAS_CL_CLIP_CNTL: { NUM_USER_CLIP_PLANES = 0 } +11848958: 0000: 00002040 00000000 +t0 write GRAS_CL_VPORT_XOFFSET (2048) + GRAS_CL_VPORT_XOFFSET: 149.500000 + GRAS_CL_VPORT_XSCALE: 150.000000 + GRAS_CL_VPORT_YOFFSET: 149.500000 + GRAS_CL_VPORT_YSCALE: -150.000000 + GRAS_CL_VPORT_ZOFFSET: 0.000000 + GRAS_CL_VPORT_ZSCALE: 1.000000 +11848960: 0000: 00052048 43158000 43160000 43158000 c3160000 00000000 3f800000 +t0 write RB_MODE_CONTROL (20c0) + RB_MODE_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE } +1184897c: 0000: 000020c0 00008200 +t3 opcode: CP_REG_RMW (21) (4 dwords) + { DST_REG = 0x20c1 | ROTATE = 0 } + { SRC0 = 12272 } + { SRC1 = 4096 } + rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00001000) +NEEDS WFI: rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00001000) +11848984: 0000: c0022100 000020c1 00002ff0 00001000 +t0 write GRAS_SC_CONTROL (2072) + GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0x1 } +11848994: 0000: 00002072 00001020 +t0 write PC_PRIM_VTX_CNTL (21ec) + PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 0 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } +1184899c: 0000: 000021ec 02000240 +t0 write GRAS_SC_WINDOW_SCISSOR_TL (2079) + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } + GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } +118489a4: 0000: 00012079 00000000 012b012b +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 0 + VFD_INDEX_MAX: 2 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 0 +118489b0: 0000: 00032242 00000000 00000002 00000000 00000000 +t0 write HLSQ_CONTROL_0_REG (2200) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x } + HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 } + HLSQ_CONTROL_3_REG: { IJPERSPCENTERREGID = r0.x | IJNONPERSPCENTERREGID = r0.x | IJPERSPCENTROIDREGID = r0.x | IJNONPERSPCENTROIDREGID = r0.x } + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 1 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 1 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 1 } +118489c4: 0000: 00052200 20000210 00000100 7c000000 00000000 01000000 01080001 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 } +118489e0: 0000: 000022c0 00500000 +t0 write SP_VS_LENGTH_REG (22df) + SP_VS_LENGTH_REG: { SHADERLENGTH = 1 } +118489e8: 0000: 000022df 00000001 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 1 } + SP_VS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 } + SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } +118489f0: 0000: 000222c4 01200402 04000000 0000fc00 +t0 write SP_FS_LENGTH_REG (22ff) + SP_FS_LENGTH_REG: { SHADERLENGTH = 1 } +11848a00: 0000: 000022ff 00000001 +t0 write SP_FS_CTRL_REG0 (22e0) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 0 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 1 } + SP_FS_CTRL_REG1: { CONSTLENGTH = 1 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 0 | HALFPRECVAROFFSET = 63 } +11848a08: 0000: 000122e0 01340012 3f000001 +t0 write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8) + SP_FS_FLAT_SHAD_MODE_REG_0: 0 + SP_FS_FLAT_SHAD_MODE_REG_1: 0 +11848a14: 0000: 000122e8 00000000 00000000 +t0 write SP_FS_OUTPUT_REG (22ec) + SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x } +11848a20: 0000: 000022ec 00000000 +t0 write SP_FS_MRT[0].REG (22f0) + SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION } + SP_FS_MRT[0x1].REG: { REGID = r0.x } + SP_FS_MRT[0x2].REG: { REGID = r0.x } + SP_FS_MRT[0x3].REG: { REGID = r0.x } +11848a28: 0000: 000322f0 00000100 00000000 00000000 00000000 +t0 write VPC_ATTR (2280) + VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | LMSIZE = 1 } + VPC_PACK: { NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } +11848a3c: 0000: 00012280 10001000 00000000 +t0 write VPC_VARYING_INTERP[0].MODE (2282) + VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } +11848a48: 0000: 00032282 00000000 00000000 00000000 00000000 +t0 write VPC_VARYING_PS_REPL[0].MODE (2286) + VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } +11848a5c: 0000: 00032286 00000000 00000000 00000000 00000000 +t0 write VFD_VS_THREADING_THRESHOLD (227e) + VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x } +11848a70: 0000: 0000227e 0000fc0f +t3 opcode: CP_LOAD_STATE (30) (3 dwords) + { DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e2000 } +11848a78: 0000: c0013000 00640000 117e2000 +t0 write VFD_PERFCOUNTER0_SELECT (0e44) +NEEDS WFI: VFD_PERFCOUNTER0_SELECT (e44) + VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED +11848a84: 0000: 00000e44 00000000 +t3 opcode: CP_LOAD_STATE (30) (3 dwords) + { DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_FRAG_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e1000 } +11848a8c: 0000: c0013000 00740000 117e1000 +t0 write VFD_PERFCOUNTER0_SELECT (0e44) +NEEDS WFI: VFD_PERFCOUNTER0_SELECT (e44) + VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED +11848a98: 0000: 00000e44 00000000 +t0 write VFD_CONTROL_0 (2240) + VFD_CONTROL_0: { TOTALATTRTOVS = 4 | PACKETSIZE = 2 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 } + VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x } +11848aa0: 0000: 00012240 08480004 fcfc0001 +t0 write VFD_FETCH[0].INSTR_0 (2246) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 | INDEXCODE = 0 | STEPRATE = 1 } + VFD_FETCH[0].INSTR_1: 0x127e9000 +11848aac: 0000: 00012246 0100060b 127e9000 +t0 write VFD_DECODE[0].INSTR (2266) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +11848ab8: 0000: 00002266 2c00009f +t0 write RB_COPY_CONTROL (20ec) + RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0x40000 } + RB_COPY_DEST_BASE: { BASE = 0x12839000 } + RB_COPY_DEST_PITCH: { PITCH = 640 } + RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE } +11848ac0: 0000: 000320ec 00040050 0941c800 00000014 0003c030 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12816 + :0,12811,12815,12816 +11848ad4: 0000: 0000057f 00003210 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 2 } + draw: 1 + prim_type: DI_PT_RECTLIST (8) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 2 + draw[281] register values +!+ 0000320f CP_SCRATCH_REG6: 12815 + :0,12811,12815,12816 +!+ 00003210 CP_SCRATCH_REG7: 12816 + :0,12811,12815,12816 + + 00000000 VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED +!+ 00000000 GRAS_CL_CLIP_CNTL: { NUM_USER_CLIP_PLANES = 0 } + + 43158000 GRAS_CL_VPORT_XOFFSET: 149.500000 + + 43160000 GRAS_CL_VPORT_XSCALE: 150.000000 + + 43158000 GRAS_CL_VPORT_YOFFSET: 149.500000 + + c3160000 GRAS_CL_VPORT_YSCALE: -150.000000 +!+ 00000000 GRAS_CL_VPORT_ZOFFSET: 0.000000 +!+ 3f800000 GRAS_CL_VPORT_ZSCALE: 1.000000 +!+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } +!+ 00001020 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0x1 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } + + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } +!+ 00008200 RB_MODE_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE } +!+ 00003050 RB_RENDER_CONTROL: { BIN_WIDTH = 160 | DISABLE_COLOR_PIPE | ENABLE_GMEM | COORD_MASK = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } +!+ 00040050 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0x40000 } +!+ 0941c800 RB_COPY_DEST_BASE: { BASE = 0x12839000 } +!+ 00000014 RB_COPY_DEST_PITCH: { PITCH = 640 } +!+ 0003c030 RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE } +!+ 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } +!+ ffff0000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } +!+ ffff0000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } +!+ 02000240 PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 0 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } + + 20000210 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE } + + 00000100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x } + + 7c000000 HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 } + + 00000000 HLSQ_CONTROL_3_REG: { IJPERSPCENTERREGID = r0.x | IJNONPERSPCENTERREGID = r0.x | IJPERSPCENTROIDREGID = r0.x | IJNONPERSPCENTROIDREGID = r0.x } +!+ 01000000 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 1 } +!+ 01080001 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 1 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 1 } +!+ 08480004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | PACKETSIZE = 2 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 } + + fcfc0001 VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x } +!+ 00000000 VFD_INDEX_MIN: 0 +!+ 00000002 VFD_INDEX_MAX: 2 + + 00000000 VFD_INSTANCEID_OFFSET: 0 +!+ 00000000 VFD_INDEX_OFFSET: 0 +!+ 0100060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 | INDEXCODE = 0 | STEPRATE = 1 } +!+ 127e9000 VFD_FETCH[0].INSTR_1: 0x127e9000 +!+ 2c00009f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } + + 0000fc0f VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x } +!+ 10001000 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | LMSIZE = 1 } +!+ 00000000 VPC_PACK: { NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } + + 00000000 VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00500000 SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 } +!+ 01200402 SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 1 } +!+ 04000000 SP_VS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 } +!+ 0000fc00 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } +!+ 00000001 SP_VS_LENGTH_REG: { SHADERLENGTH = 1 } +!+ 01340012 SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 0 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 1 } +!+ 3f000001 SP_FS_CTRL_REG1: { CONSTLENGTH = 1 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 0 | HALFPRECVAROFFSET = 63 } + + 00000000 SP_FS_FLAT_SHAD_MODE_REG_0: 0 + + 00000000 SP_FS_FLAT_SHAD_MODE_REG_1: 0 + + 00000000 SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x } +!+ 00000100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION } + + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x } + + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x } + + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x } +!+ 00000001 SP_FS_LENGTH_REG: { SHADERLENGTH = 1 } +11848adc: 0000: c0022200 00000000 00004088 00000002 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12817 + :0,12811,12815,12817 +11848aec: 0000: 0000057f 00003211 +t0 write RB_COPY_CONTROL (20ec) + RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 } + RB_COPY_DEST_BASE: { BASE = 0x12869000 } + RB_COPY_DEST_PITCH: { PITCH = 1280 } + RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE } +11848af4: 0000: 000320ec 00000010 09434800 00000028 0003c120 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12818 + :0,12811,12815,12818 +11848b08: 0000: 0000057f 00003212 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 2 } + draw: 2 + prim_type: DI_PT_RECTLIST (8) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 2 + draw[282] register values +!+ 00003212 CP_SCRATCH_REG7: 12818 + :0,12811,12815,12818 +!+ 00000010 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 } +!+ 09434800 RB_COPY_DEST_BASE: { BASE = 0x12869000 } +!+ 00000028 RB_COPY_DEST_PITCH: { PITCH = 1280 } +!+ 0003c120 RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE } +11848b10: 0000: c0022200 00000000 00004088 00000002 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12819 + :0,12811,12815,12819 +11848b20: 0000: 0000057f 00003213 +t0 write RB_MODE_CONTROL (20c0) + RB_MODE_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE } +11848b28: 0000: 000020c0 00008000 +t0 write GRAS_SC_CONTROL (2072) + GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0 } +11848b30: 0000: 00002072 00000000 +t0 write RB_DEPTH_INFO (2102) + RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_16 | DEPTH_BASE = 0x40000 } + RB_DEPTH_PITCH: 320 +11848b38: 0000: 00012102 00020000 00000028 +t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) +NEEDS WFI: RB_FRAME_BUFFER_DIMENSION (ce0) + RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 } +11848b44: 0000: 00000ce0 004b012c +t0 write RB_MODE_CONTROL (20c0) + RB_MODE_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE } +11848b4c: 0000: 000020c0 00008000 +t3 opcode: (null) (4c) (4 dwords) +11848b54: 0000: c0024c00 00000000 000000a0 012b012b +t0 write RB_MRT[0].BUF_INFO (20c5) + RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 640 } + RB_MRT[0].BUF_BASE: { COLOR_BUF_BASE = 0 } +11848b64: 0000: 000120c5 00280488 00000000 +t0 write SP_FS_IMAGE_OUTPUT[0].REG (22f4) + SP_FS_IMAGE_OUTPUT[0].REG: { MRTFORMAT = RB_R8G8B8A8_UNORM } +11848b70: 0000: 000022f4 00000008 +t0 write RB_MRT[0x1].BUF_INFO (20c9) + RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x1].BUF_BASE: { COLOR_BUF_BASE = 0 } +11848b78: 0000: 000120c9 00000080 00000000 +t0 write SP_FS_IMAGE_OUTPUT[0x1].REG (22f5) + SP_FS_IMAGE_OUTPUT[0x1].REG: { MRTFORMAT = RB_R5G6B5_UNORM } +11848b84: 0000: 000022f5 00000000 +t0 write RB_MRT[0x2].BUF_INFO (20cd) + RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x2].BUF_BASE: { COLOR_BUF_BASE = 0 } +11848b8c: 0000: 000120cd 00000080 00000000 +t0 write SP_FS_IMAGE_OUTPUT[0x2].REG (22f6) + SP_FS_IMAGE_OUTPUT[0x2].REG: { MRTFORMAT = RB_R5G6B5_UNORM } +11848b98: 0000: 000022f6 00000000 +t0 write RB_MRT[0x3].BUF_INFO (20d1) + RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x3].BUF_BASE: { COLOR_BUF_BASE = 0 } +11848ba0: 0000: 000120d1 00000080 00000000 +t0 write SP_FS_IMAGE_OUTPUT[0x3].REG (22f7) + SP_FS_IMAGE_OUTPUT[0x3].REG: { MRTFORMAT = RB_R5G6B5_UNORM } +11848bac: 0000: 000022f7 00000000 +t3 opcode: CP_REG_RMW (21) (4 dwords) + { DST_REG = 0x20c1 | ROTATE = 0 } + { SRC0 = 4294955023 } + { SRC1 = 8272 } + rmw (RB_RENDER_CONTROL & 0xffffd00f) | 0x00002050) +NEEDS WFI: rmw (RB_RENDER_CONTROL & 0xffffd00f) | 0x00002050) +11848bb4: 0000: c0022100 000020c1 ffffd00f 00002050 +t0 write RB_WINDOW_OFFSET (210e) + RB_WINDOW_OFFSET: { X = 160 | Y = 0 } +11848bc4: 0000: 0000210e 000000a0 +t0 write GRAS_SC_SCREEN_SCISSOR_TL (2074) + GRAS_SC_SCREEN_SCISSOR_TL: { X = 160 | Y = 0 } + GRAS_SC_SCREEN_SCISSOR_BR: { X = 299 | Y = 299 } +11848bcc: 0000: 00012074 000000a0 012b012b +t0 write CP_SCRATCH_REG6 (057e) +NEEDS WFI: CP_SCRATCH_REG6 (57e) + CP_SCRATCH_REG6: 12820 + :0,12811,12820,12819 +11848bd8: 0000: 0000057e 00003214 +t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords) + ibaddr:11842370 + ibsize:000018ba +11848be0: 0000: c0013700 11842370 000018ba +t0 write CP_SCRATCH_REG6 (057e) +NEEDS WFI: CP_SCRATCH_REG6 (57e) + CP_SCRATCH_REG6: 12821 + :0,12811,12821,12819 +11848bec: 0000: 0000057e 00003215 +t0 write RB_DEPTH_CONTROL (2100) + RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } +11848bf4: 0000: 00002100 00000000 +t0 write RB_STENCIL_CONTROL (2104) + RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } +11848bfc: 0000: 00002104 00000000 +t0 write RB_STENCILREFMASK (2108) + RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } + RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } +11848c04: 0000: 00012108 ffff0000 ffff0000 +t0 write GRAS_SU_MODE_CONTROL (2070) + GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } +11848c10: 0000: 00002070 00000000 +t0 write GRAS_CL_CLIP_CNTL (2040) + GRAS_CL_CLIP_CNTL: { NUM_USER_CLIP_PLANES = 0 } +11848c18: 0000: 00002040 00000000 +t0 write GRAS_CL_VPORT_XOFFSET (2048) + GRAS_CL_VPORT_XOFFSET: 149.500000 + GRAS_CL_VPORT_XSCALE: 150.000000 + GRAS_CL_VPORT_YOFFSET: 149.500000 + GRAS_CL_VPORT_YSCALE: -150.000000 + GRAS_CL_VPORT_ZOFFSET: 0.000000 + GRAS_CL_VPORT_ZSCALE: 1.000000 +11848c20: 0000: 00052048 43158000 43160000 43158000 c3160000 00000000 3f800000 +t0 write RB_MODE_CONTROL (20c0) + RB_MODE_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE } +11848c3c: 0000: 000020c0 00008200 +t3 opcode: CP_REG_RMW (21) (4 dwords) + { DST_REG = 0x20c1 | ROTATE = 0 } + { SRC0 = 12272 } + { SRC1 = 4096 } + rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00001000) +NEEDS WFI: rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00001000) +11848c44: 0000: c0022100 000020c1 00002ff0 00001000 +t0 write GRAS_SC_CONTROL (2072) + GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0x1 } +11848c54: 0000: 00002072 00001020 +t0 write PC_PRIM_VTX_CNTL (21ec) + PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 0 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } +11848c5c: 0000: 000021ec 02000240 +t0 write GRAS_SC_WINDOW_SCISSOR_TL (2079) + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } + GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } +11848c64: 0000: 00012079 00000000 012b012b +t0 write VFD_INDEX_MIN (2242) + VFD_INDEX_MIN: 0 + VFD_INDEX_MAX: 2 + VFD_INSTANCEID_OFFSET: 0 + VFD_INDEX_OFFSET: 0 +11848c70: 0000: 00032242 00000000 00000002 00000000 00000000 +t0 write HLSQ_CONTROL_0_REG (2200) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x } + HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 } + HLSQ_CONTROL_3_REG: { IJPERSPCENTERREGID = r0.x | IJNONPERSPCENTERREGID = r0.x | IJPERSPCENTROIDREGID = r0.x | IJNONPERSPCENTROIDREGID = r0.x } + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 1 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 1 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 1 } +11848c84: 0000: 00052200 20000210 00000100 7c000000 00000000 01000000 01080001 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 } +11848ca0: 0000: 000022c0 00500000 +t0 write SP_VS_LENGTH_REG (22df) + SP_VS_LENGTH_REG: { SHADERLENGTH = 1 } +11848ca8: 0000: 000022df 00000001 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 1 } + SP_VS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 } + SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } +11848cb0: 0000: 000222c4 01200402 04000000 0000fc00 +t0 write SP_FS_LENGTH_REG (22ff) + SP_FS_LENGTH_REG: { SHADERLENGTH = 1 } +11848cc0: 0000: 000022ff 00000001 +t0 write SP_FS_CTRL_REG0 (22e0) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 0 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 1 } + SP_FS_CTRL_REG1: { CONSTLENGTH = 1 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 0 | HALFPRECVAROFFSET = 63 } +11848cc8: 0000: 000122e0 01340012 3f000001 +t0 write SP_FS_FLAT_SHAD_MODE_REG_0 (22e8) + SP_FS_FLAT_SHAD_MODE_REG_0: 0 + SP_FS_FLAT_SHAD_MODE_REG_1: 0 +11848cd4: 0000: 000122e8 00000000 00000000 +t0 write SP_FS_OUTPUT_REG (22ec) + SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x } +11848ce0: 0000: 000022ec 00000000 +t0 write SP_FS_MRT[0].REG (22f0) + SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION } + SP_FS_MRT[0x1].REG: { REGID = r0.x } + SP_FS_MRT[0x2].REG: { REGID = r0.x } + SP_FS_MRT[0x3].REG: { REGID = r0.x } +11848ce8: 0000: 000322f0 00000100 00000000 00000000 00000000 +t0 write VPC_ATTR (2280) + VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | LMSIZE = 1 } + VPC_PACK: { NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } +11848cfc: 0000: 00012280 10001000 00000000 +t0 write VPC_VARYING_INTERP[0].MODE (2282) + VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } +11848d08: 0000: 00032282 00000000 00000000 00000000 00000000 +t0 write VPC_VARYING_PS_REPL[0].MODE (2286) + VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } +11848d1c: 0000: 00032286 00000000 00000000 00000000 00000000 +t0 write VFD_VS_THREADING_THRESHOLD (227e) + VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x } +11848d30: 0000: 0000227e 0000fc0f +t3 opcode: CP_LOAD_STATE (30) (3 dwords) + { DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_VERT_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e2000 } +11848d38: 0000: c0013000 00640000 117e2000 +t0 write VFD_PERFCOUNTER0_SELECT (0e44) +NEEDS WFI: VFD_PERFCOUNTER0_SELECT (e44) + VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED +11848d44: 0000: 00000e44 00000000 +t3 opcode: CP_LOAD_STATE (30) (3 dwords) + { DST_OFF = 0 | STATE_SRC = SS_INDIRECT | STATE_BLOCK = SB_FRAG_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST_SHADER | EXT_SRC_ADDR = 0x117e1000 } +11848d4c: 0000: c0013000 00740000 117e1000 +t0 write VFD_PERFCOUNTER0_SELECT (0e44) +NEEDS WFI: VFD_PERFCOUNTER0_SELECT (e44) + VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED +11848d58: 0000: 00000e44 00000000 +t0 write VFD_CONTROL_0 (2240) + VFD_CONTROL_0: { TOTALATTRTOVS = 4 | PACKETSIZE = 2 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 } + VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x } +11848d60: 0000: 00012240 08480004 fcfc0001 +t0 write VFD_FETCH[0].INSTR_0 (2246) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 | INDEXCODE = 0 | STEPRATE = 1 } + VFD_FETCH[0].INSTR_1: 0x127e9000 +11848d6c: 0000: 00012246 0100060b 127e9000 +t0 write VFD_DECODE[0].INSTR (2266) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +11848d78: 0000: 00002266 2c00009f +t0 write RB_COPY_CONTROL (20ec) + RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0x40000 } + RB_COPY_DEST_BASE: { BASE = 0x12839000 } + RB_COPY_DEST_PITCH: { PITCH = 640 } + RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE } +11848d80: 0000: 000320ec 00040050 0941c800 00000014 0003c030 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12822 + :0,12811,12821,12822 +11848d94: 0000: 0000057f 00003216 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 2 } + draw: 3 + prim_type: DI_PT_RECTLIST (8) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 2 + draw[283] register values +!+ 00003215 CP_SCRATCH_REG6: 12821 + :0,12811,12821,12822 +!+ 00003216 CP_SCRATCH_REG7: 12822 + :0,12811,12821,12822 + + 004b012c RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 } + + 00000000 VFD_PERFCOUNTER0_SELECT: VFD_PERF_UCHE_BYTE_FETCHED + + 00000000 GRAS_CL_CLIP_CNTL: { NUM_USER_CLIP_PLANES = 0 } + + 43158000 GRAS_CL_VPORT_XOFFSET: 149.500000 + + 43160000 GRAS_CL_VPORT_XSCALE: 150.000000 + + 43158000 GRAS_CL_VPORT_YOFFSET: 149.500000 + + c3160000 GRAS_CL_VPORT_YSCALE: -150.000000 + + 00000000 GRAS_CL_VPORT_ZOFFSET: 0.000000 + + 3f800000 GRAS_CL_VPORT_ZSCALE: 1.000000 + + 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } + + 00001020 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0x1 } +!+ 000000a0 GRAS_SC_SCREEN_SCISSOR_TL: { X = 160 | Y = 0 } +!+ 012b012b GRAS_SC_SCREEN_SCISSOR_BR: { X = 299 | Y = 299 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } + + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + + 00008200 RB_MODE_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE } + + 00003050 RB_RENDER_CONTROL: { BIN_WIDTH = 160 | DISABLE_COLOR_PIPE | ENABLE_GMEM | COORD_MASK = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } + + 00280488 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 640 } + + 00000000 RB_MRT[0].BUF_BASE: { COLOR_BUF_BASE = 0 } + + 00000080 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x1].BUF_BASE: { COLOR_BUF_BASE = 0 } + + 00000080 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x2].BUF_BASE: { COLOR_BUF_BASE = 0 } + + 00000080 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = RB_R5G6B5_UNORM | COLOR_TILE_MODE = TILE_32X32 | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x3].BUF_BASE: { COLOR_BUF_BASE = 0 } +!+ 00040050 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_DEPTH_STENCIL | FASTCLEAR = 0 | GMEM_BASE = 0x40000 } +!+ 0941c800 RB_COPY_DEST_BASE: { BASE = 0x12839000 } +!+ 00000014 RB_COPY_DEST_PITCH: { PITCH = 640 } +!+ 0003c030 RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE } + + 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + + 00020000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_16 | DEPTH_BASE = 0x40000 } + + 00000028 RB_DEPTH_PITCH: 320 + + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + + ffff0000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } + + ffff0000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } +!+ 000000a0 RB_WINDOW_OFFSET: { X = 160 | Y = 0 } + + 02000240 PC_PRIM_VTX_CNTL: { STRIDE_IN_VPC = 0 | POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES | PROVOKING_VTX_LAST } + + 20000210 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | SPSHADERRESTART | CYCLETIMEOUTLIMITVPC = 0 | CONSTMODE = 0 | SPCONSTFULLUPDATE } + + 00000100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | FRAGCOORDXYREGID = r0.x | FRAGCOORDZWREGID = r0.x } + + 7c000000 HLSQ_CONTROL_2_REG: { FACENESSREGID = r0.x | COVVALUEREGID = r0.x | PRIMALLOCTHRESHOLD = 31 } + + 00000000 HLSQ_CONTROL_3_REG: { IJPERSPCENTERREGID = r0.x | IJNONPERSPCENTERREGID = r0.x | IJPERSPCENTROIDREGID = r0.x | IJNONPERSPCENTROIDREGID = r0.x } + + 01000000 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTSTARTOFFSET = 0 | INSTRLENGTH = 1 } + + 01080001 HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 1 | CONSTSTARTOFFSET = 128 | INSTRLENGTH = 1 } + + 08480004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | PACKETSIZE = 2 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 } + + fcfc0001 VFD_CONTROL_1: { MAXSTORAGE = 1 | MAXTHRESHOLD = 0 | MINTHRESHOLD = 0 | REGID4VTX = r63.x | REGID4INST = r63.x } + + 00000000 VFD_INDEX_MIN: 0 + + 00000002 VFD_INDEX_MAX: 2 + + 00000000 VFD_INSTANCEID_OFFSET: 0 + + 00000000 VFD_INDEX_OFFSET: 0 + + 0100060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 | INDEXCODE = 0 | STEPRATE = 1 } + + 127e9000 VFD_FETCH[0].INSTR_1: 0x127e9000 + + 2c00009f VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } + + 0000fc0f VFD_VS_THREADING_THRESHOLD: { REGID_THRESHOLD = 15 | REGID_VTXCNT = r63.x } + + 10001000 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | LMSIZE = 1 } + + 00000000 VPC_PACK: { NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } + + 00000000 VPC_VARYING_INTERP[0].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x1].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x2].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_INTERP[0x3].MODE: { C0 = SMOOTH | C1 = SMOOTH | C2 = SMOOTH | C3 = SMOOTH | C4 = SMOOTH | C5 = SMOOTH | C6 = SMOOTH | C7 = SMOOTH | C8 = SMOOTH | C9 = SMOOTH | CA = SMOOTH | CB = SMOOTH | CC = SMOOTH | CD = SMOOTH | CE = SMOOTH | CF = SMOOTH } + + 00000000 VPC_VARYING_PS_REPL[0].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: { C0 = 0 | C1 = 0 | C2 = 0 | C3 = 0 | C4 = 0 | C5 = 0 | C6 = 0 | C7 = 0 | C8 = 0 | C9 = 0 | CA = 0 | CB = 0 | CC = 0 | CD = 0 | CE = 0 | CF = 0 } + + 00500000 SP_SP_CTRL_REG: { CONSTMODE = 0 | SLEEPMODE = 1 | L0MODE = 1 } + + 01200402 SP_VS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE | LENGTH = 1 } + + 04000000 SP_VS_CTRL_REG1: { CONSTLENGTH = 0 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 4 } + + 0000fc00 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } + + 00000001 SP_VS_LENGTH_REG: { SHADERLENGTH = 1 } + + 01340012 SP_FS_CTRL_REG0: { THREADMODE = MULTI | INSTRBUFFERMODE = BUFFER | HALFREGFOOTPRINT = 1 | FULLREGFOOTPRINT = 0 | INOUTREGOVERLAP | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE | LENGTH = 1 } + + 3f000001 SP_FS_CTRL_REG1: { CONSTLENGTH = 1 | CONSTFOOTPRINT = 0 | INITIALOUTSTANDING = 0 | HALFPRECVAROFFSET = 63 } + + 00000000 SP_FS_FLAT_SHAD_MODE_REG_0: 0 + + 00000000 SP_FS_FLAT_SHAD_MODE_REG_1: 0 + + 00000000 SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r0.x } + + 00000100 SP_FS_MRT[0].REG: { REGID = r0.x | HALF_PRECISION } + + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x } + + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x } + + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x } + + 00000008 SP_FS_IMAGE_OUTPUT[0].REG: { MRTFORMAT = RB_R8G8B8A8_UNORM } + + 00000000 SP_FS_IMAGE_OUTPUT[0x1].REG: { MRTFORMAT = RB_R5G6B5_UNORM } + + 00000000 SP_FS_IMAGE_OUTPUT[0x2].REG: { MRTFORMAT = RB_R5G6B5_UNORM } + + 00000000 SP_FS_IMAGE_OUTPUT[0x3].REG: { MRTFORMAT = RB_R5G6B5_UNORM } + + 00000001 SP_FS_LENGTH_REG: { SHADERLENGTH = 1 } +11848d9c: 0000: c0022200 00000000 00004088 00000002 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12823 + :0,12811,12821,12823 +11848dac: 0000: 0000057f 00003217 +t0 write RB_COPY_CONTROL (20ec) + RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 } + RB_COPY_DEST_BASE: { BASE = 0x12869000 } + RB_COPY_DEST_PITCH: { PITCH = 1280 } + RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE } +11848db4: 0000: 000320ec 00000010 09434800 00000028 0003c120 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12824 + :0,12811,12821,12824 +11848dc8: 0000: 0000057f 00003218 +t3 opcode: CP_DRAW_INDX (22) (4 dwords) + { VIZ_QUERY = 0 } + { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX_SIZE_IGN | PRE_DRAW_INITIATOR_ENABLE | NUM_INSTANCES = 0 } + { NUM_INDICES = 2 } + draw: 4 + prim_type: DI_PT_RECTLIST (8) + source_select: DI_SRC_SEL_AUTO_INDEX (2) + num_indices: 2 + draw[284] register values +!+ 00003218 CP_SCRATCH_REG7: 12824 + :0,12811,12821,12824 +!+ 00000010 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 } +!+ 09434800 RB_COPY_DEST_BASE: { BASE = 0x12869000 } +!+ 00000028 RB_COPY_DEST_PITCH: { PITCH = 1280 } +!+ 0003c120 RB_COPY_DEST_INFO: { TILE = LINEAR | FORMAT = RB_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE } +11848dd0: 0000: c0022200 00000000 00004088 00000002 +t0 write CP_SCRATCH_REG7 (057f) +NEEDS WFI: CP_SCRATCH_REG7 (57f) + CP_SCRATCH_REG7: 12825 + :0,12811,12821,12825 +11848de0: 0000: 0000057f 00003219 +t0 write RB_MODE_CONTROL (20c0) + RB_MODE_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MRT = 0 | MARB_CACHE_SPLIT_MODE } +11848de8: 0000: 000020c0 00008000 +t0 write GRAS_SC_CONTROL (2072) + GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = MSAA_ONE | RASTER_MODE = 0 } +11848df0: 0000: 00002072 00000000 +############################################################ +vertices: 0 +cmd: es2gears/628: fence=277 +cmd: es2gears/628: fence=278 +cmd: es2gears/628: fence=279 +cmd: es2gears/628: fence=280 +cmd: es2gears/628: fence=281 +cmd: es2gears/628: fence=282 +cmd: es2gears/628: fence=283 +cmd: es2gears/628: fence=284 +cmd: es2gears/628: fence=285 +cmd: es2gears/628: fence=286 +cmd: es2gears/628: fence=287 +cmd: es2gears/628: fence=288 +cmd: es2gears/628: fence=289 +cmd: es2gears/628: fence=290 +cmd: es2gears/628: fence=291 +cmd: es2gears/628: fence=292 +cmd: es2gears/628: fence=293 +cmd: es2gears/628: fence=294 +cmd: es2gears/628: fence=295 +cmd: es2gears/628: fence=296 +cmd: es2gears/628: fence=297 +cmd: es2gears/628: fence=298 +cmd: es2gears/628: fence=299 +cmd: es2gears/628: fence=300 +cmd: es2gears/628: fence=301 +cmd: es2gears/628: fence=302 +cmd: es2gears/628: fence=303 +cmd: es2gears/628: fence=304 +cmd: es2gears/628: fence=305 +cmd: es2gears/628: fence=306 +cmd: es2gears/628: fence=307 +cmd: es2gears/628: fence=308 +cmd: es2gears/628: fence=309 +cmd: es2gears/628: fence=310 +cmd: es2gears/628: fence=311 +cmd: es2gears/628: fence=312 +cmd: es2gears/628: fence=313 +cmd: es2gears/628: fence=314 +cmd: es2gears/628: fence=315 +cmd: es2gears/628: fence=316 +cmd: es2gears/628: fence=317 +cmd: es2gears/628: fence=318 +cmd: es2gears/628: fence=319 +cmd: es2gears/628: fence=320 +cmd: es2gears/628: fence=321 +cmd: es2gears/628: fence=322 +cmd: es2gears/628: fence=323 +cmd: es2gears/628: fence=324 +cmd: es2gears/628: fence=325 +cmd: es2gears/628: fence=326 +cmd: es2gears/628: fence=327 +cmd: es2gears/628: fence=328 +cmd: es2gears/628: fence=329 +cmd: es2gears/628: fence=330 +cmd: es2gears/628: fence=331 +cmd: es2gears/628: fence=332 +cmd: es2gears/628: fence=333 +cmd: es2gears/628: fence=334 +cmd: es2gears/628: fence=335 +cmd: es2gears/628: fence=336 +cmd: es2gears/628: fence=337 +cmd: es2gears/628: fence=338 +cmd: es2gears/628: fence=339 diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log new file mode 100644 index 00000000000..798c0673438 --- /dev/null +++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log @@ -0,0 +1,7359 @@ +Reading src/freedreno/.gitlab-ci/traces/fd-clouds.rd.gz... +gpu_id: 630 +cmd: null_platform_t/2995: fence=1855 +############################################################ +cmdstream: 1023 dwords +t7 opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = CACHE_INVALIDATE } + event CACHE_INVALIDATE +0000000001d91000: 0000: 70460001 00000031 +t4 write HLSQ_INVALIDATE_CMD (bb08) + HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f } +0000000001d91008: 0000: 40bb0801 000fffff +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91010: 0000: 70268000 +t4 write RB_UNKNOWN_8E04 (8e04) + RB_UNKNOWN_8E04: 0 +0000000001d91014: 0000: 408e0401 00000000 +t4 write SP_UNKNOWN_AE04 (ae04) + SP_UNKNOWN_AE04: 0x8 +0000000001d9101c: 0000: 48ae0401 00000008 +t4 write SP_UNKNOWN_AE00 (ae00) + SP_UNKNOWN_AE00: 0 +0000000001d91024: 0000: 40ae0001 00000000 +t4 write SP_UNKNOWN_AE0F (ae0f) + SP_UNKNOWN_AE0F: 0x3f +0000000001d9102c: 0000: 40ae0f01 0000003f +t4 write SP_UNKNOWN_B605 (b605) + SP_UNKNOWN_B605: 0x44 +0000000001d91034: 0000: 40b60501 00000044 +t4 write SP_UNKNOWN_B600 (b600) + SP_UNKNOWN_B600: 0x100000 +0000000001d9103c: 0000: 40b60001 00100000 +t4 write HLSQ_UNKNOWN_BE00 (be00) + HLSQ_UNKNOWN_BE00: 0x80 +0000000001d91044: 0000: 48be0001 00000080 +t4 write HLSQ_UNKNOWN_BE01 (be01) + HLSQ_UNKNOWN_BE01: 0 +0000000001d9104c: 0000: 40be0101 00000000 +t4 write VPC_UNKNOWN_9600 (9600) + VPC_UNKNOWN_9600: 0 +0000000001d91054: 0000: 48960001 00000000 +t4 write GRAS_UNKNOWN_8600 (8600) + GRAS_UNKNOWN_8600: 0x880 +0000000001d9105c: 0000: 40860001 00000880 +t4 write HLSQ_UNKNOWN_BE04 (be04) + HLSQ_UNKNOWN_BE04: 0x80000 +0000000001d91064: 0000: 40be0401 00080000 +t4 write SP_UNKNOWN_AE03 (ae03) + SP_UNKNOWN_AE03: 0x1430 +0000000001d9106c: 0000: 40ae0301 00001430 +t4 write SP_IBO_COUNT (ab20) + SP_IBO_COUNT: 0 +0000000001d91074: 0000: 48ab2001 00000000 +t4 write SP_UNKNOWN_B182 (b182) + SP_UNKNOWN_B182: 0 +0000000001d9107c: 0000: 48b18201 00000000 +t4 write HLSQ_SHARED_CONSTS (bb11) + HLSQ_SHARED_CONSTS: { 0 } +0000000001d91084: 0000: 48bb1101 00000000 +t4 write UCHE_UNKNOWN_0E12 (0e12) + UCHE_UNKNOWN_0E12: 0x3200000 +0000000001d9108c: 0000: 400e1201 03200000 +t4 write UCHE_CLIENT_PF (0e19) + UCHE_CLIENT_PF: { PERFSEL = 0x4 } +0000000001d91094: 0000: 480e1901 00000004 +t4 write RB_UNKNOWN_8E01 (8e01) + RB_UNKNOWN_8E01: 0x1 +0000000001d9109c: 0000: 408e0101 00000001 +t4 write SP_UNKNOWN_AB00 (ab00) + SP_UNKNOWN_AB00: 0x5 +0000000001d910a4: 0000: 40ab0001 00000005 +t4 write VFD_ADD_OFFSET (a009) + VFD_ADD_OFFSET: { VERTEX } +0000000001d910ac: 0000: 48a00901 00000001 +t4 write RB_UNKNOWN_8811 (8811) + RB_UNKNOWN_8811: 0x1 +0000000001d910b4: 0000: 48881101 00000010 +t4 write PC_MODE_CNTL (9804) + PC_MODE_CNTL: 0x1f +0000000001d910bc: 0000: 48980401 0000001f +t4 write RB_SRGB_CNTL (880f) + RB_SRGB_CNTL: { 0 } +0000000001d910c4: 0000: 48880f01 00000000 +t4 write GRAS_UNKNOWN_8101 (8101) + GRAS_UNKNOWN_8101: 0 +0000000001d910cc: 0000: 40810101 00000000 +t4 write GRAS_SAMPLE_CNTL (8109) + GRAS_SAMPLE_CNTL: { 0 } +0000000001d910d4: 0000: 48810901 00000000 +t4 write GRAS_UNKNOWN_8110 (8110) + GRAS_UNKNOWN_8110: 0x2 +0000000001d910dc: 0000: 40811001 00000002 +t4 write RB_UNKNOWN_8818 (8818) + RB_UNKNOWN_8818: 0 +0000000001d910e4: 0000: 48881801 00000000 +t4 write RB_UNKNOWN_8819 (8819) + RB_UNKNOWN_8819: 0 +0000000001d910ec: 0000: 40881901 00000000 +t4 write RB_UNKNOWN_881A (881a) + RB_UNKNOWN_881A: 0 +0000000001d910f4: 0000: 40881a01 00000000 +t4 write RB_UNKNOWN_881B (881b) + RB_UNKNOWN_881B: 0 +0000000001d910fc: 0000: 48881b01 00000000 +t4 write RB_UNKNOWN_881C (881c) + RB_UNKNOWN_881C: 0 +0000000001d91104: 0000: 40881c01 00000000 +t4 write RB_UNKNOWN_881D (881d) + RB_UNKNOWN_881D: 0 +0000000001d9110c: 0000: 48881d01 00000000 +t4 write RB_UNKNOWN_881E (881e) + RB_UNKNOWN_881E: 0 +0000000001d91114: 0000: 48881e01 00000000 +t4 write RB_UNKNOWN_88F0 (88f0) + RB_UNKNOWN_88F0: 0 +0000000001d9111c: 0000: 4888f001 00000000 +t4 write VPC_POINT_COORD_INVERT (9236) + VPC_POINT_COORD_INVERT: { 0 } +0000000001d91124: 0000: 40923601 00000000 +t4 write VPC_UNKNOWN_9300 (9300) + VPC_UNKNOWN_9300: 0 +0000000001d9112c: 0000: 48930001 00000000 +t4 write VPC_SO_DISABLE (9306) + VPC_SO_DISABLE: { DISABLE } +0000000001d91134: 0000: 48930601 00000001 +t4 write PC_PRIMID_PASSTHRU (9806) + PC_PRIMID_PASSTHRU: FALSE +0000000001d9113c: 0000: 40980601 00000000 +t4 write 0x9990 (9990) + 0x9990: 00000000 +0000000001d91144: 0000: 48999001 00000000 +t4 write PC_UNKNOWN_9980 (9980) + PC_UNKNOWN_9980: 0 +0000000001d9114c: 0000: 40998001 00000000 +t4 write PC_UNKNOWN_9B07 (9b07) + PC_UNKNOWN_9B07: 0 +0000000001d91154: 0000: 489b0701 00000000 +t4 write SP_UNKNOWN_A81B (a81b) + SP_UNKNOWN_A81B: 0 +0000000001d9115c: 0000: 40a81b01 00000000 +t4 write SP_UNKNOWN_B183 (b183) + SP_UNKNOWN_B183: 0 +0000000001d91164: 0000: 40b18301 00000000 +t4 write GRAS_UNKNOWN_8099 (8099) + GRAS_UNKNOWN_8099: 0 +0000000001d9116c: 0000: 40809901 00000000 +t4 write GRAS_VS_LAYER_CNTL (809b) + GRAS_VS_LAYER_CNTL: { 0 } +0000000001d91174: 0000: 48809b01 00000000 +t4 write GRAS_UNKNOWN_80A0 (80a0) + GRAS_UNKNOWN_80A0: 0x2 +0000000001d9117c: 0000: 4080a001 00000002 +t4 write GRAS_UNKNOWN_80AF (80af) + GRAS_UNKNOWN_80AF: FALSE +0000000001d91184: 0000: 4080af01 00000000 +t4 write VPC_UNKNOWN_9210 (9210) + VPC_UNKNOWN_9210: 0 +0000000001d9118c: 0000: 48921001 00000000 +t4 write VPC_UNKNOWN_9211 (9211) + VPC_UNKNOWN_9211: 0 +0000000001d91194: 0000: 40921101 00000000 +t4 write VPC_UNKNOWN_9602 (9602) + VPC_UNKNOWN_9602: FALSE +0000000001d9119c: 0000: 40960201 00000000 +t4 write PC_POLYGON_MODE (9981) + PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } +0000000001d911a4: 0000: 48998101 00000003 +t4 write PC_UNKNOWN_9E72 (9e72) + PC_UNKNOWN_9E72: 0 +0000000001d911ac: 0000: 409e7201 00000000 +t4 write VPC_POLYGON_MODE (9108) + VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } +0000000001d911b4: 0000: 48910801 00000003 +t4 write SP_TP_SAMPLE_CONFIG (b304) + SP_TP_SAMPLE_CONFIG: { 0 } +0000000001d911bc: 0000: 48b30401 00000000 +t4 write SP_TP_UNKNOWN_B309 (b309) + SP_TP_UNKNOWN_B309: 0xa2 +0000000001d911c4: 0000: 40b30901 000000a2 +t4 write RB_SAMPLE_CONFIG (8804) + RB_SAMPLE_CONFIG: { 0 } +0000000001d911cc: 0000: 40880401 00000000 +t4 write GRAS_SAMPLE_CONFIG (80a4) + GRAS_SAMPLE_CONFIG: { 0 } +0000000001d911d4: 0000: 4880a401 00000000 +t4 write GRAS_SAMPLE_LOCATION_0 (80a5) + GRAS_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } +0000000001d911dc: 0000: 4080a501 00000000 +t4 write GRAS_SAMPLE_LOCATION_1 (80a6) + GRAS_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } +0000000001d911e4: 0000: 4080a601 00000000 +t4 write RB_SAMPLE_LOCATION_0 (8805) + RB_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } +0000000001d911ec: 0000: 48880501 00000000 +t4 write RB_SAMPLE_LOCATION_1 (8806) + RB_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } +0000000001d911f4: 0000: 48880601 00000000 +t4 write RB_Z_BOUNDS_MIN (8878) + RB_Z_BOUNDS_MIN: 0.000000 +0000000001d911fc: 0000: 48887801 00000000 +t4 write RB_Z_BOUNDS_MAX (8879) + RB_Z_BOUNDS_MAX: 0.000000 +0000000001d91204: 0000: 40887901 00000000 +t4 write HLSQ_CONTROL_5_REG (b986) + HLSQ_CONTROL_5_REG: 0xfc +0000000001d9120c: 0000: 48b98601 000000fc +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91214: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 4 + :0,0,0,4 +0000000001d91218: 0000: 48088a01 00000004 +t4 write VFD_MODE_CNTL (a007) + VFD_MODE_CNTL: { 0 } +0000000001d91220: 0000: 40a00701 00000000 +t4 write VFD_UNKNOWN_A008 (a008) + VFD_UNKNOWN_A008: 0 +0000000001d91228: 0000: 40a00801 00000000 +t4 write PC_MODE_CNTL (9804) + PC_MODE_CNTL: 0x1f +0000000001d91230: 0000: 48980401 0000001f +t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords) + { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } + { ADDR_LO = 0 } + { ADDR_HI = 0 } +0000000001d91238: 0000: 70438003 00040000 00000000 00000000 +t4 write VPC_SO_BUF_CNTL (9305) + VPC_SO_BUF_CNTL: { 0 } +0000000001d91248: 0000: 48930501 00000000 +t4 write GRAS_LRZ_CNTL (8100) + GRAS_LRZ_CNTL: { 0 } +0000000001d91250: 0000: 48810001 00000000 +t4 write RB_LRZ_CNTL (8898) + RB_LRZ_CNTL: { 0 } +0000000001d91258: 0000: 40889801 00000000 +t7 opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = LRZ_FLUSH } + event LRZ_FLUSH +0000000001d91260: 0000: 70460001 00000026 +t7 opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = CACHE_INVALIDATE } + event CACHE_INVALIDATE +0000000001d91268: 0000: 70460001 00000031 +t7 opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords) +0000000001d91270: 0000: 709d0001 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91278: 0000: 70268000 +t4 write RB_CCU_CNTL (8e07) + RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM | UNK2 } +0000000001d9127c: 0000: 408e0701 7c400004 +t4 write RB_DEPTH_BUFFER_INFO (8872) + RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } + RB_DEPTH_BUFFER_PITCH: 0 + RB_DEPTH_BUFFER_ARRAY_PITCH: 0 + RB_DEPTH_BUFFER_BASE_LO: 0 + RB_DEPTH_BUFFER_BASE_HI: 0 + RB_DEPTH_BUFFER_BASE_GMEM: 0 +0000000001d91284: 0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000 +t4 write GRAS_SU_DEPTH_BUFFER_INFO (8098) + GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } +0000000001d912a0: 0000: 48809801 00000000 +t4 write GRAS_LRZ_BUFFER_BASE_LO (8103) + GRAS_LRZ_BUFFER_BASE_LO: 0 + GRAS_LRZ_BUFFER_BASE_HI: 0 + GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0 + GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 +0000000001d912a8: 0000: 48810385 00000000 00000000 00000000 00000000 00000000 +t4 write RB_STENCIL_INFO (8881) + RB_STENCIL_INFO: { 0 } +0000000001d912c0: 0000: 48888101 00000000 +t4 write RB_MRT[0].BUF_INFO (8822) + RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WXYZ } + RB_MRT[0].PITCH: 8704 + RB_MRT[0].ARRAY_PITCH: 12533760 + RB_MRT[0].BASE_LO: 0x1125000 + RB_MRT[0].BASE_HI: 0 + RB_MRT[0].BASE_GMEM: 0 +0000000001d912c8: 0000: 48882286 00002031 00000088 0002fd00 01125000 00000000 00000000 +t4 write SP_FS_MRT[0].REG (a996) + SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM } +0000000001d912e4: 0000: 48a99601 00000031 +t4 write RB_MRT_FLAG_BUFFER[0].ADDR_LO (8903) + RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0 + RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 + RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } +0000000001d912ec: 0000: 40890383 00000000 00000000 00000000 +t4 write RB_SRGB_CNTL (880f) + RB_SRGB_CNTL: { 0 } +0000000001d912fc: 0000: 48880f01 00000000 +t4 write SP_SRGB_CNTL (a98a) + SP_SRGB_CNTL: { 0 } +0000000001d91304: 0000: 40a98a01 00000000 +t4 write RB_RENDER_COMPONENTS (880d) + RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } +0000000001d9130c: 0000: 40880d01 0000000f +t4 write SP_FS_RENDER_COMPONENTS (a98b) + SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } +0000000001d91314: 0000: 48a98b01 0000000f +t4 write GRAS_MAX_LAYER_INDEX (8004) + GRAS_MAX_LAYER_INDEX: 0 +0000000001d9131c: 0000: 48800401 00000000 +t4 write SP_TP_RAS_MSAA_CNTL (b300) + SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } + SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } +0000000001d91324: 0000: 40b30002 00000000 00000004 +t4 write GRAS_RAS_MSAA_CNTL (80a2) + GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } + GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } +0000000001d91330: 0000: 4880a202 00000000 00000004 +t4 write RB_RAS_MSAA_CNTL (8802) + RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } + RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } +0000000001d9133c: 0000: 40880202 00000000 00000004 +t4 write RB_MSAA_CNTL (88d5) + RB_MSAA_CNTL: { SAMPLES = MSAA_ONE } +0000000001d91348: 0000: 4088d501 00000000 +t4 write VPC_SO_DISABLE (9306) + VPC_SO_DISABLE: { 0 } +0000000001d91350: 0000: 48930601 00000000 +t4 write GRAS_BIN_CONTROL (80a1) + GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | BINNING_PASS | UNK22 = 0x18 } +0000000001d91358: 0000: 4880a101 06041e11 +t4 write RB_BIN_CONTROL (8800) + RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | BINNING_PASS | UNK22 = 0x18 } +0000000001d91360: 0000: 48880001 06041e11 +t4 write RB_BIN_CONTROL2 (88d3) + RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 } +0000000001d91368: 0000: 4088d301 00001e11 +t7 opcode: CP_REG_WRITE (6d) (4 dwords) + { TRACKER = TRACK_RENDER_CNTL } + RB_RENDER_CNTL: { UNK4 | BINNING | FLAG_MRTS = 0 } +0000000001d91370: 0000: 706d8003 00000002 00008801 00000090 +t4 write GRAS_SC_WINDOW_SCISSOR_TL (80f0) + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } + GRAS_SC_WINDOW_SCISSOR_BR: { X = 2159 | Y = 1439 } +0000000001d91380: 0000: 4080f002 00000000 059f086f +t4 write GRAS_2D_RESOLVE_CNTL_1 (840a) + GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 } + GRAS_2D_RESOLVE_CNTL_2: { X = 2159 | Y = 1439 } +0000000001d9138c: 0000: 48840a02 00000000 059f086f +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91398: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 9 + :0,0,0,9 +0000000001d9139c: 0000: 48088a01 00000009 +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = RM6_BINNING | MARKER = RM6_BINNING } +0000000001d913a4: 0000: 70e50001 00000002 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d913ac: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 10 + :0,0,0,10 +0000000001d913b0: 0000: 48088a01 0000000a +t7 opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords) +0000000001d913b8: 0000: 70640001 00000001 +t7 opcode: CP_SET_MODE (63) (2 dwords) +0000000001d913c0: 0000: 70e30001 00000001 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d913c8: 0000: 70268000 +t4 write VFD_MODE_CNTL (a007) + VFD_MODE_CNTL: { BINNING_PASS } +0000000001d913cc: 0000: 40a00701 00000001 +t4 write VSC_BIN_SIZE (0c02) + VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 } + VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x1d65800 + VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0 +0000000001d913d4: 0000: 400c0283 00001e11 01d65800 00000000 +t4 write VSC_BIN_COUNT (0c06) + VSC_BIN_COUNT: { NX = 4 | NY = 3 } +0000000001d913e4: 0000: 480c0601 00001808 +t4 write VSC_PIPE_CONFIG[0].REG (0c10) + VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0x1].REG: { X = 1 | Y = 0 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0x2].REG: { X = 2 | Y = 0 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0x3].REG: { X = 3 | Y = 0 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0x4].REG: { X = 0 | Y = 1 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0x5].REG: { X = 1 | Y = 1 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0x6].REG: { X = 2 | Y = 1 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0x7].REG: { X = 3 | Y = 1 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0x8].REG: { X = 0 | Y = 2 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0x9].REG: { X = 1 | Y = 2 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0xa].REG: { X = 2 | Y = 2 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0xb].REG: { X = 3 | Y = 2 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0xc].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0xd].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0xe].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0xf].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x10].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x11].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x12].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x13].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x14].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x15].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x16].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x17].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x18].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x19].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x1a].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x1b].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x1c].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x1d].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x1e].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x1f].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } +0000000001d913ec: 0000: 400c1020 04100000 04100001 04100002 04100003 04100400 04100401 04100402 +0000000001d9140c: 0020: 04100403 04100800 04100801 04100802 04100803 00000000 00000000 00000000 +* +t4 write VSC_PRIM_STRM_ADDRESS_LO (0c30) + VSC_PRIM_STRM_ADDRESS_LO: 0x1d67000 + VSC_PRIM_STRM_ADDRESS_HI: 0 + VSC_PRIM_STRM_PITCH: 0x1040 + VSC_PRIM_STRM_LIMIT: 0x28000 +0000000001d91470: 0000: 480c3004 01d67000 00000000 00001040 00028000 +t4 write VSC_DRAW_STRM_ADDRESS_LO (0c34) + VSC_DRAW_STRM_ADDRESS_LO: 0x1d5d000 + VSC_DRAW_STRM_ADDRESS_HI: 0 + VSC_DRAW_STRM_PITCH: 0x440 + VSC_DRAW_STRM_LIMIT: 0xa000 +0000000001d91484: 0000: 400c3404 01d5d000 00000000 00000440 0000a000 +t4 write PC_UNKNOWN_9805 (9805) + PC_UNKNOWN_9805: 0x1 +0000000001d91498: 0000: 40980501 00000001 +t4 write SP_UNKNOWN_A0F8 (a0f8) + SP_UNKNOWN_A0F8: 0x1 +0000000001d914a0: 0000: 40a0f801 00000001 +t7 opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = UNK_2C } + event UNK_2C +0000000001d914a8: 0000: 70460001 0000002c +t4 write RB_WINDOW_OFFSET (8890) + RB_WINDOW_OFFSET: { X = 0 | Y = 0 } +0000000001d914b0: 0000: 48889001 00000000 +t4 write SP_TP_WINDOW_OFFSET (b307) + SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } +0000000001d914b8: 0000: 48b30701 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d914c0: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 11 + :0,0,11,10 +0000000001d914c4: 0000: 48088901 0000000b +t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + ibaddr:0000000001d8f000 + ibsize:00000053 +t4 write VFD_INDEX_OFFSET (a00e) + VFD_INDEX_OFFSET: 0 +0000000001d8f000: 0000: 40a00e01 00000000 +t4 write VFD_INSTANCE_START_OFFSET (a00f) + VFD_INSTANCE_START_OFFSET: 0 +0000000001d8f008: 0000: 48a00f01 00000000 +t4 write PC_RESTART_INDEX (9803) + PC_RESTART_INDEX: 4294967295 +0000000001d8f010: 0000: 40980301 ffffffff +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d8f018: 0000: 70268000 +t4 write CP_SCRATCH[0x5].REG (0888) + CP_SCRATCH[0x5].REG: 1 + :0,1,11,10 +0000000001d8f01c: 0000: 40088801 00000001 +t4 write RB_STENCILREF (8887) + RB_STENCILREF: { REF = 0 | BFREF = 0 } +0000000001d8f024: 0000: 48888701 00000000 +t4 write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0) + GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 } + GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 2159 | Y = 1439 } +0000000001d8f02c: 0000: 4880b002 00000000 059f086f +t4 write GRAS_CL_VPORT[0].XOFFSET (8010) + GRAS_CL_VPORT[0].XOFFSET: 1080.000000 + GRAS_CL_VPORT[0].XSCALE: 1080.000000 + GRAS_CL_VPORT[0].YOFFSET: 720.000000 + GRAS_CL_VPORT[0].YSCALE: 720.000000 + GRAS_CL_VPORT[0].ZOFFSET: 0.500000 + GRAS_CL_VPORT[0].ZSCALE: 0.500000 +0000000001d8f038: 0000: 48801086 44870000 44870000 44340000 44340000 3f000000 3f000000 +t4 write GRAS_SC_VIEWPORT_SCISSOR[0].TL (80d0) + GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 } + GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 2159 | Y = 1439 } +0000000001d8f054: 0000: 4880d002 00000000 059f086f +t4 write GRAS_CL_GUARDBAND_CLIP_ADJ (8006) + GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 311 | VERT = 349 } +0000000001d8f060: 0000: 40800601 00057537 +t4 write RB_BLEND_CNTL (8865) + RB_BLEND_CNTL: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } +0000000001d8f068: 0000: 48886501 ffff0000 +t4 write RB_BLEND_RED_F32 (8860) + RB_BLEND_RED_F32: 0.000000 + RB_BLEND_GREEN_F32: 0.000000 + RB_BLEND_BLUE_F32: 0.000000 + RB_BLEND_ALPHA_F32: 0.000000 +0000000001d8f070: 0000: 48886004 00000000 00000000 00000000 00000000 +t7 opcode: CP_SET_DRAW_STATE (43) (40 dwords) + { COUNT = 12 | BINNING | GMEM | SYSMEM | GROUP_ID = 7 } + { ADDR_LO = 0x1116000 } + { ADDR_HI = 0 } + { COUNT = 9 | BINNING | GMEM | SYSMEM | GROUP_ID = 22 } + { ADDR_LO = 0x111e000 } + { ADDR_HI = 0 } + { COUNT = 21 | BINNING | GMEM | SYSMEM | GROUP_ID = 0 } + { ADDR_LO = 0x111f000 } + { ADDR_HI = 0 } + { COUNT = 192 | GMEM | SYSMEM | GROUP_ID = 1 } + { ADDR_LO = 0x1120000 } + { ADDR_HI = 0 } + { COUNT = 95 | BINNING | GROUP_ID = 2 } + { ADDR_LO = 0x1121000 } + { ADDR_HI = 0 } + { COUNT = 18 | GMEM | SYSMEM | GROUP_ID = 3 } + { ADDR_LO = 0x1122000 } + { ADDR_HI = 0 } + { COUNT = 14 | BINNING | GMEM | SYSMEM | GROUP_ID = 21 } + { ADDR_LO = 0x1123000 } + { ADDR_HI = 0 } + { COUNT = 5 | GMEM | SYSMEM | GROUP_ID = 4 } + { ADDR_LO = 0x1116030 } + { ADDR_HI = 0 } + { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 8 } + { ADDR_LO = 0 } + { ADDR_HI = 0 } + { COUNT = 20 | GMEM | SYSMEM | GROUP_ID = 12 } + { ADDR_LO = 0x1116050 } + { ADDR_HI = 0 } + { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 13 } + { ADDR_LO = 0 } + { ADDR_HI = 0 } + { COUNT = 36 | GMEM | SYSMEM | GROUP_ID = 23 } + { ADDR_LO = 0x1124000 } + { ADDR_HI = 0 } + { COUNT = 9 | GMEM | SYSMEM | GROUP_ID = 20 } + { ADDR_LO = 0x11160a0 } + { ADDR_HI = 0 } +0000000001d8f084: 0000: 70438027 0770000c 01116000 00000000 16700009 0111e000 00000000 00700015 +0000000001d8f0a4: 0020: 0111f000 00000000 016000c0 01120000 00000000 0210005f 01121000 00000000 +0000000001d8f0c4: 0040: 03600012 01122000 00000000 1570000e 01123000 00000000 04600005 01116030 +0000000001d8f0e4: 0060: 00000000 08720000 00000000 00000000 0c600014 01116050 00000000 0d720000 +0000000001d8f104: 0080: 00000000 00000000 17600024 01124000 00000000 14600009 011160a0 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d8f124: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 2 + :0,1,11,2 +0000000001d8f128: 0000: 48088a01 00000002 + group_id: 0 + count: 21 + addr: 000000000111f000 + flags: 0 + enable_mask: 0x7 +000000000111f000: 0000: 40bb0801 000000ff 48b80004 00000100 00000000 00000000 00000000 40bb1001 +000000000111f020: 0020: 00000108 48a82301 00000100 48a83b01 00000000 40a86301 00000000 48a89401 +000000000111f040: 0040: 00000000 48ab0401 00000100 48ab2001 00000000 +t4 write HLSQ_INVALIDATE_CMD (bb08) + HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 } +000000000111f000: 0000: 40bb0801 000000ff +t4 write HLSQ_VS_CNTL (b800) + HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED } + HLSQ_HS_CNTL: { CONSTLEN = 0 } + HLSQ_DS_CNTL: { CONSTLEN = 0 } + HLSQ_GS_CNTL: { CONSTLEN = 0 } +000000000111f008: 0000: 48b80004 00000100 00000000 00000000 00000000 +t4 write HLSQ_FS_CNTL (bb10) + HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED } +000000000111f01c: 0000: 40bb1001 00000108 +t4 write SP_VS_CONFIG (a823) + SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } +000000000111f024: 0000: 48a82301 00000100 +t4 write SP_HS_CONFIG (a83b) + SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } +000000000111f02c: 0000: 48a83b01 00000000 +t4 write SP_DS_CONFIG (a863) + SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } +000000000111f034: 0000: 40a86301 00000000 +t4 write SP_GS_CONFIG (a894) + SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } +000000000111f03c: 0000: 48a89401 00000000 +t4 write SP_FS_CONFIG (ab04) + SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } +000000000111f044: 0000: 48ab0401 00000100 +t4 write SP_IBO_COUNT (ab20) + SP_IBO_COUNT: 0 +000000000111f04c: 0000: 48ab2001 00000000 + group_id: 1 + count: 192 + addr: 0000000001120000 + flags: 0 + enable_mask: 0x6 + skipped! + + group_id: 2 + count: 95 + addr: 0000000001121000 + flags: 0 + enable_mask: 0x1 +0000000001121000: 0000: 40a83301 00000000 40a99e01 00007fc0 40a9a801 00000000 40ab0001 00000005 +0000000001121020: 0020: 40a98c01 fcfcfc00 40a80001 80100080 40a82401 00000001 48a81c02 01011000 +0000000001121040: 0040: 00000000 70328003 00620000 01011000 00000000 40921204 ffffffff ffffffff +0000000001121060: 0060: ffffffff ffffffff 40a80301 00000f00 48a81301 00000000 48a83101 00000000 +0000000001121080: 0080: 48a80201 00000001 40930401 ff00ff00 489b0101 00000004 409b0301 00000000 +00000000011210a0: 00a0: 40b98285 00000007 fcfcfcfc fcfcfcfc fcfcfcfc 000000fc 48b98001 00000001 +00000000011210c0: 00c0: 40a98001 81100080 48a98201 00000000 48910401 0000ffff 40800501 00000000 +00000000011210e0: 00e0: 48880902 00000000 00000000 40881001 00000000 40810101 00000000 48810901 +0000000001121100: 0100: 00000000 48a98e08 000000fc 000000fc 000000fc 000000fc 000000fc 000000fc +0000000001121120: 0120: 000000fc 000000fc 40930101 00ff0004 409b0601 00000000 40a87101 00000000 +0000000001121140: 0140: 48910101 00ffff00 48910701 00000000 40a00186 fcfcfcfc 0000fcfc fcfcfcfc +0000000001121160: 0160: 000000fc 0000fcfc 00000000 40887001 00000000 48809401 00000000 +t4 write SP_HS_UNKNOWN_A833 (a833) + SP_HS_UNKNOWN_A833: 0 +0000000001121000: 0000: 40a83301 00000000 +t4 write SP_FS_PREFETCH_CNTL (a99e) + SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } +0000000001121008: 0000: 40a99e01 00007fc0 +t4 write SP_UNKNOWN_A9A8 (a9a8) + SP_UNKNOWN_A9A8: 0 +0000000001121010: 0000: 40a9a801 00000000 +t4 write SP_UNKNOWN_AB00 (ab00) + SP_UNKNOWN_AB00: 0x5 +0000000001121018: 0000: 40ab0001 00000005 +t4 write SP_FS_OUTPUT_CNTL0 (a98c) + SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x } +0000000001121020: 0000: 40a98c01 fcfcfc00 +t4 write SP_VS_CTRL_REG0 (a800) + SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | MERGEDREGS } +0000000001121028: 0000: 40a80001 80100080 +t4 write SP_VS_INSTRLEN (a824) + SP_VS_INSTRLEN: 1 +0000000001121030: 0000: 40a82401 00000001 +t4 write SP_VS_OBJ_START_LO (a81c) + SP_VS_OBJ_START_LO: 0x1011000 base=1011000, offset=0, size=128 + SP_VS_OBJ_START_HI: 0 base=1011000, offset=0, size=128 +0000000001011000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 +* + :0:0000:0000[03000000x_00000000x] end + :0:0001:0001[00000000x_00000000x] nop + :0:0002:0002[00000000x_00000000x] nop + :0:0003:0003[00000000x_00000000x] nop + :0:0004:0004[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): (cnt=0, max=0) + - used (merged): (cnt=0, max=0) + - input (half): (cnt=0, max=0) + - input (full): (cnt=0, max=0) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): (cnt=0, max=0) (estimated) + - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full + - shaderdb: 0 (ss), 0 (sy) +0000000001121038: 0000: 48a81c02 01011000 00000000 +t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords) + { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 } + { EXT_SRC_ADDR = 0x1011000 } + { EXT_SRC_ADDR_HI = 0 } + :0:0000:0000[03000000x_00000000x] end + :0:0001:0001[00000000x_00000000x] nop + :0:0002:0002[00000000x_00000000x] nop + :0:0003:0003[00000000x_00000000x] nop + :0:0004:0004[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): (cnt=0, max=0) + - used (merged): (cnt=0, max=0) + - input (half): (cnt=0, max=0) + - input (full): (cnt=0, max=0) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): (cnt=0, max=0) (estimated) + - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full + - shaderdb: 0 (ss), 0 (sy) +0000000001121044: 0000: 70328003 00620000 01011000 00000000 +t4 write VPC_VAR[0].DISABLE (9212) + VPC_VAR[0].DISABLE: 0xffffffff + VPC_VAR[0x1].DISABLE: 0xffffffff + VPC_VAR[0x2].DISABLE: 0xffffffff + VPC_VAR[0x3].DISABLE: 0xffffffff +0000000001121054: 0000: 40921204 ffffffff ffffffff ffffffff ffffffff +t4 write SP_VS_OUT[0].REG (a803) + SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +0000000001121068: 0000: 40a80301 00000f00 +t4 write SP_VS_VPC_DST[0].REG (a813) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } +0000000001121070: 0000: 48a81301 00000000 +t4 write SP_HS_UNKNOWN_A831 (a831) + SP_HS_UNKNOWN_A831: 0 +0000000001121078: 0000: 48a83101 00000000 +t4 write SP_VS_PRIMITIVE_CNTL (a802) + SP_VS_PRIMITIVE_CNTL: { OUT = 1 } +0000000001121080: 0000: 48a80201 00000001 +t4 write VPC_CNTL_0 (9304) + VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | UNKLOC = 255 } +0000000001121088: 0000: 40930401 ff00ff00 +t4 write PC_VS_OUT_CNTL (9b01) + PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 4 | CLIP_MASK = 0 } +0000000001121090: 0000: 489b0101 00000004 +t4 write PC_PRIMITIVE_CNTL_3 (9b03) + PC_PRIMITIVE_CNTL_3: 0 +0000000001121098: 0000: 409b0301 00000000 +t4 write HLSQ_CONTROL_1_REG (b982) + HLSQ_CONTROL_1_REG: 0x7 + HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_5_REG: 0xfc +00000000011210a0: 0000: 40b98285 00000007 fcfcfcfc fcfcfcfc fcfcfcfc 000000fc +t4 write HLSQ_UNKNOWN_B980 (b980) + HLSQ_UNKNOWN_B980: 0x1 +00000000011210b8: 0000: 48b98001 00000001 +t4 write SP_FS_CTRL_REG0 (a980) + SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | MERGEDREGS | 0x1000000 } +00000000011210c0: 0000: 40a98001 81100080 +t4 write SP_UNKNOWN_A982 (a982) + SP_UNKNOWN_A982: 0 +00000000011210c8: 0000: 48a98201 00000000 +t4 write VPC_VS_LAYER_CNTL (9104) + VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } +00000000011210d0: 0000: 48910401 0000ffff +t4 write GRAS_CNTL (8005) + GRAS_CNTL: { COORD_MASK = 0 } +00000000011210d8: 0000: 40800501 00000000 +t4 write RB_RENDER_CONTROL0 (8809) + RB_RENDER_CONTROL0: { COORD_MASK = 0 } + RB_RENDER_CONTROL1: { 0 } +00000000011210e0: 0000: 48880902 00000000 00000000 +t4 write RB_SAMPLE_CNTL (8810) + RB_SAMPLE_CNTL: { 0 } +00000000011210ec: 0000: 40881001 00000000 +t4 write GRAS_UNKNOWN_8101 (8101) + GRAS_UNKNOWN_8101: 0 +00000000011210f4: 0000: 40810101 00000000 +t4 write GRAS_SAMPLE_CNTL (8109) + GRAS_SAMPLE_CNTL: { 0 } +00000000011210fc: 0000: 48810901 00000000 +t4 write SP_FS_OUTPUT[0].REG (a98e) + SP_FS_OUTPUT[0].REG: { REGID = r63.x } + SP_FS_OUTPUT[0x1].REG: { REGID = r63.x } + SP_FS_OUTPUT[0x2].REG: { REGID = r63.x } + SP_FS_OUTPUT[0x3].REG: { REGID = r63.x } + SP_FS_OUTPUT[0x4].REG: { REGID = r63.x } + SP_FS_OUTPUT[0x5].REG: { REGID = r63.x } + SP_FS_OUTPUT[0x6].REG: { REGID = r63.x } + SP_FS_OUTPUT[0x7].REG: { REGID = r63.x } +0000000001121104: 0000: 48a98e08 000000fc 000000fc 000000fc 000000fc 000000fc 000000fc 000000fc +0000000001121124: 0020: 000000fc +t4 write VPC_VS_PACK (9301) + VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 } +0000000001121128: 0000: 40930101 00ff0004 +t4 write PC_PRIMITIVE_CNTL_6 (9b06) + PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } +0000000001121130: 0000: 409b0601 00000000 +t4 write SP_GS_PRIM_SIZE (a871) + SP_GS_PRIM_SIZE: 0 +0000000001121138: 0000: 40a87101 00000000 +t4 write VPC_VS_CLIP_CNTL (9101) + VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } +0000000001121140: 0000: 48910101 00ffff00 +t4 write VPC_UNKNOWN_9107 (9107) + VPC_UNKNOWN_9107: 0 +0000000001121148: 0000: 48910701 00000000 +t4 write VFD_CONTROL_1 (a001) + VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | 0xfc000000 } + VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } + VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } + VFD_CONTROL_4: 0xfc + VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + VFD_CONTROL_6: { 0 } +0000000001121150: 0000: 40a00186 fcfcfcfc 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000 +t4 write RB_DEPTH_PLANE_CNTL (8870) + RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } +000000000112116c: 0000: 40887001 00000000 +t4 write GRAS_SU_DEPTH_PLANE_CNTL (8094) + GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } +0000000001121174: 0000: 48809401 00000000 + group_id: 3 + count: 18 + addr: 0000000001122000 + flags: 0 + enable_mask: 0x6 + skipped! + + group_id: 4 + count: 5 + addr: 0000000001116030 + flags: 0 + enable_mask: 0x6 + skipped! + + group_id: 7 + count: 12 + addr: 0000000001116000 + flags: 0 + enable_mask: 0x7 +0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c 48a09002 c7400000 00000001 +0000000001116020: 0020: 40a0d001 0000000f 48a00001 00000101 +t4 write VFD_FETCH[0].BASE (a010) + VFD_FETCH[0].BASE: 0x1016000 + VFD_FETCH[0].BASE+0x1: 0 + VFD_FETCH[0].SIZE: 1048576 + VFD_FETCH[0].STRIDE: 12 +0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c +t4 write VFD_DECODE[0].INSTR (a090) + VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } + VFD_DECODE[0].STEP_RATE: 0x1 +0000000001116014: 0000: 48a09002 c7400000 00000001 +t4 write VFD_DEST_CNTL[0].INSTR (a0d0) + VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } +0000000001116020: 0000: 40a0d001 0000000f +t4 write VFD_CONTROL_0 (a000) + VFD_CONTROL_0: { FETCH_CNT = 1 | DECODE_CNT = 1 } +0000000001116028: 0000: 48a00001 00000101 + group_id: 12 + count: 20 + addr: 0000000001116050 + flags: 0 + enable_mask: 0x6 + skipped! + + group_id: 20 + count: 9 + addr: 00000000011160a0 + flags: 0 + enable_mask: 0x6 + skipped! + + group_id: 21 + count: 14 + addr: 0000000001123000 + flags: 0 + enable_mask: 0x7 +0000000001123000: 0000: 40800002 00000080 00000000 40809001 00000014 48809102 00100010 00000010 +0000000001123020: 0020: 40809583 00000000 00000000 00000000 409b0001 00000002 +t4 write GRAS_CL_CNTL (8000) + GRAS_CL_CNTL: { VP_CLIP_CODE_IGNORE } + GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } +0000000001123000: 0000: 40800002 00000080 00000000 +t4 write GRAS_SU_CNTL (8090) + GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 } +000000000112300c: 0000: 40809001 00000014 +t4 write GRAS_SU_POINT_MINMAX (8091) + GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + GRAS_SU_POINT_SIZE: 1.000000 +0000000001123014: 0000: 48809102 00100010 00000010 +t4 write GRAS_SU_POLY_OFFSET_SCALE (8095) + GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000 +0000000001123020: 0000: 40809583 00000000 00000000 00000000 +t4 write PC_PRIMITIVE_CNTL_0 (9b00) + PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST } +0000000001123030: 0000: 409b0001 00000002 + group_id: 22 + count: 9 + addr: 000000000111e000 + flags: 0 + enable_mask: 0x7 +000000000111e000: 0000: 40886401 00000000 40888001 00000000 48887101 00000000 48888802 00000000 +* +t4 write RB_ALPHA_CONTROL (8864) + RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } +000000000111e000: 0000: 40886401 00000000 +t4 write RB_STENCIL_CONTROL (8880) + RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } +000000000111e008: 0000: 40888001 00000000 +t4 write RB_DEPTH_CNTL (8871) + RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER } +000000000111e010: 0000: 48887101 00000000 +t4 write RB_STENCILMASK (8888) + RB_STENCILMASK: { MASK = 0 | BFMASK = 0 } + RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 } +000000000111e018: 0000: 48888802 00000000 00000000 + group_id: 23 + count: 36 + addr: 0000000001124000 + flags: 0 + enable_mask: 0x6 + skipped! + +t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 4 } + mode: RM6_BINNING + skip_ib2: g=0, l=0 + draw[0] register values +!+ 00000001 CP_SCRATCH[0x5].REG: 1 + :0,1,11,2 +!+ 0000000b CP_SCRATCH[0x6].REG: 11 + :0,1,11,2 +!+ 00000002 CP_SCRATCH[0x7].REG: 2 + :0,1,11,2 +!+ 00001e11 VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 } +!+ 01d65800 VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x1d65800 + + 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0 +!+ 00001808 VSC_BIN_COUNT: { NX = 4 | NY = 3 } +!+ 04100000 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 } +!+ 04100001 VSC_PIPE_CONFIG[0x1].REG: { X = 1 | Y = 0 | W = 1 | H = 1 } +!+ 04100002 VSC_PIPE_CONFIG[0x2].REG: { X = 2 | Y = 0 | W = 1 | H = 1 } +!+ 04100003 VSC_PIPE_CONFIG[0x3].REG: { X = 3 | Y = 0 | W = 1 | H = 1 } +!+ 04100400 VSC_PIPE_CONFIG[0x4].REG: { X = 0 | Y = 1 | W = 1 | H = 1 } +!+ 04100401 VSC_PIPE_CONFIG[0x5].REG: { X = 1 | Y = 1 | W = 1 | H = 1 } +!+ 04100402 VSC_PIPE_CONFIG[0x6].REG: { X = 2 | Y = 1 | W = 1 | H = 1 } +!+ 04100403 VSC_PIPE_CONFIG[0x7].REG: { X = 3 | Y = 1 | W = 1 | H = 1 } +!+ 04100800 VSC_PIPE_CONFIG[0x8].REG: { X = 0 | Y = 2 | W = 1 | H = 1 } +!+ 04100801 VSC_PIPE_CONFIG[0x9].REG: { X = 1 | Y = 2 | W = 1 | H = 1 } +!+ 04100802 VSC_PIPE_CONFIG[0xa].REG: { X = 2 | Y = 2 | W = 1 | H = 1 } +!+ 04100803 VSC_PIPE_CONFIG[0xb].REG: { X = 3 | Y = 2 | W = 1 | H = 1 } + + 00000000 VSC_PIPE_CONFIG[0xc].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0xd].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0xe].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0xf].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x10].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x11].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x12].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x13].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x14].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x15].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x16].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x17].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x18].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x19].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x1a].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x1b].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x1c].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x1d].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x1e].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x1f].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } +!+ 01d67000 VSC_PRIM_STRM_ADDRESS_LO: 0x1d67000 + + 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0 +!+ 00001040 VSC_PRIM_STRM_PITCH: 0x1040 +!+ 00028000 VSC_PRIM_STRM_LIMIT: 0x28000 +!+ 01d5d000 VSC_DRAW_STRM_ADDRESS_LO: 0x1d5d000 + + 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0 +!+ 00000440 VSC_DRAW_STRM_PITCH: 0x440 +!+ 0000a000 VSC_DRAW_STRM_LIMIT: 0xa000 +!+ 03200000 UCHE_UNKNOWN_0E12: 0x3200000 +!+ 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 } +!+ 00000080 GRAS_CL_CNTL: { VP_CLIP_CODE_IGNORE } + + 00000000 GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } + + 00000000 GRAS_MAX_LAYER_INDEX: 0 + + 00000000 GRAS_CNTL: { COORD_MASK = 0 } +!+ 00057537 GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 311 | VERT = 349 } +!+ 44870000 GRAS_CL_VPORT[0].XOFFSET: 1080.000000 +!+ 44870000 GRAS_CL_VPORT[0].XSCALE: 1080.000000 +!+ 44340000 GRAS_CL_VPORT[0].YOFFSET: 720.000000 +!+ 44340000 GRAS_CL_VPORT[0].YSCALE: 720.000000 +!+ 3f000000 GRAS_CL_VPORT[0].ZOFFSET: 0.500000 +!+ 3f000000 GRAS_CL_VPORT[0].ZSCALE: 0.500000 +!+ 00000014 GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 } +!+ 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } +!+ 00000010 GRAS_SU_POINT_SIZE: 1.000000 + + 00000000 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } + + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000 + + 00000000 GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } + + 00000000 GRAS_UNKNOWN_8099: 0 + + 00000000 GRAS_VS_LAYER_CNTL: { 0 } +!+ 00000002 GRAS_UNKNOWN_80A0: 0x2 +!+ 06041e11 GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | BINNING_PASS | UNK22 = 0x18 } + + 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } +!+ 00000004 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } + + 00000000 GRAS_SAMPLE_CONFIG: { 0 } + + 00000000 GRAS_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + + 00000000 GRAS_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + + 00000000 GRAS_UNKNOWN_80AF: FALSE + + 00000000 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 } +!+ 059f086f GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 2159 | Y = 1439 } + + 00000000 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 } +!+ 059f086f GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 2159 | Y = 1439 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 059f086f GRAS_SC_WINDOW_SCISSOR_BR: { X = 2159 | Y = 1439 } + + 00000000 GRAS_LRZ_CNTL: { 0 } + + 00000000 GRAS_UNKNOWN_8101: 0 + + 00000000 GRAS_LRZ_BUFFER_BASE_LO: 0 + + 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0 + + 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0 + + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 + + 00000000 GRAS_SAMPLE_CNTL: { 0 } +!+ 00000002 GRAS_UNKNOWN_8110: 0x2 + + 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 } +!+ 059f086f GRAS_2D_RESOLVE_CNTL_2: { X = 2159 | Y = 1439 } +!+ 00000880 GRAS_UNKNOWN_8600: 0x880 +!+ 06041e11 RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | BINNING_PASS | UNK22 = 0x18 } +!+ 00000090 RB_RENDER_CNTL: { UNK4 | BINNING | FLAG_MRTS = 0 } + + 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } +!+ 00000004 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } + + 00000000 RB_SAMPLE_CONFIG: { 0 } + + 00000000 RB_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + + 00000000 RB_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + + 00000000 RB_RENDER_CONTROL0: { COORD_MASK = 0 } + + 00000000 RB_RENDER_CONTROL1: { 0 } +!+ 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } + + 00000000 RB_SRGB_CNTL: { 0 } + + 00000000 RB_SAMPLE_CNTL: { 0 } +!+ 00000010 RB_UNKNOWN_8811: 0x1 + + 00000000 RB_UNKNOWN_8818: 0 + + 00000000 RB_UNKNOWN_8819: 0 + + 00000000 RB_UNKNOWN_881A: 0 + + 00000000 RB_UNKNOWN_881B: 0 + + 00000000 RB_UNKNOWN_881C: 0 + + 00000000 RB_UNKNOWN_881D: 0 + + 00000000 RB_UNKNOWN_881E: 0 +!+ 00002031 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WXYZ } +!+ 00000088 RB_MRT[0].PITCH: 8704 +!+ 0002fd00 RB_MRT[0].ARRAY_PITCH: 12533760 +!+ 01125000 RB_MRT[0].BASE_LO: 0x1125000 + + 00000000 RB_MRT[0].BASE_HI: 0 + + 00000000 RB_MRT[0].BASE_GMEM: 0 + + 00000000 RB_BLEND_RED_F32: 0.000000 + + 00000000 RB_BLEND_GREEN_F32: 0.000000 + + 00000000 RB_BLEND_BLUE_F32: 0.000000 + + 00000000 RB_BLEND_ALPHA_F32: 0.000000 + + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } +!+ ffff0000 RB_BLEND_CNTL: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + + 00000000 RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } + + 00000000 RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER } + + 00000000 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } + + 00000000 RB_DEPTH_BUFFER_PITCH: 0 + + 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0 + + 00000000 RB_DEPTH_BUFFER_BASE_LO: 0 + + 00000000 RB_DEPTH_BUFFER_BASE_HI: 0 + + 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0 + + 00000000 RB_Z_BOUNDS_MIN: 0.000000 + + 00000000 RB_Z_BOUNDS_MAX: 0.000000 + + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + + 00000000 RB_STENCIL_INFO: { 0 } + + 00000000 RB_STENCILREF: { REF = 0 | BFREF = 0 } + + 00000000 RB_STENCILMASK: { MASK = 0 | BFMASK = 0 } + + 00000000 RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 } + + 00000000 RB_WINDOW_OFFSET: { X = 0 | Y = 0 } + + 00000000 RB_LRZ_CNTL: { 0 } +!+ 00001e11 RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 } + + 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE } + + 00000000 RB_UNKNOWN_88F0: 0 + + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0 + + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 + + 00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } +!+ 00000001 RB_UNKNOWN_8E01: 0x1 + + 00000000 RB_UNKNOWN_8E04: 0 +!+ 7c400004 RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM | UNK2 } +!+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } +!+ 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } + + 00000000 VPC_UNKNOWN_9107: 0 +!+ 00000003 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } + + 00000000 VPC_UNKNOWN_9210: 0 + + 00000000 VPC_UNKNOWN_9211: 0 +!+ ffffffff VPC_VAR[0].DISABLE: 0xffffffff +!+ ffffffff VPC_VAR[0x1].DISABLE: 0xffffffff +!+ ffffffff VPC_VAR[0x2].DISABLE: 0xffffffff +!+ ffffffff VPC_VAR[0x3].DISABLE: 0xffffffff + + 00000000 VPC_POINT_COORD_INVERT: { 0 } + + 00000000 VPC_UNKNOWN_9300: 0 +!+ 00ff0004 VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 } +!+ ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | UNKLOC = 255 } + + 00000000 VPC_SO_BUF_CNTL: { 0 } + + 00000000 VPC_SO_DISABLE: { 0 } + + 00000000 VPC_UNKNOWN_9600: 0 + + 00000000 VPC_UNKNOWN_9602: FALSE +!+ ffffffff PC_RESTART_INDEX: 4294967295 +!+ 0000001f PC_MODE_CNTL: 0x1f +!+ 00000001 PC_UNKNOWN_9805: 0x1 + + 00000000 PC_PRIMID_PASSTHRU: FALSE + + 00000000 PC_UNKNOWN_9980: 0 +!+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } + + 00000000 0x9990: 00000000 +!+ 00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST } +!+ 00000004 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 4 | CLIP_MASK = 0 } + + 00000000 PC_PRIMITIVE_CNTL_3: 0 + + 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } + + 00000000 PC_UNKNOWN_9B07: 0 + + 00000000 PC_UNKNOWN_9E72: 0 +!+ 00000101 VFD_CONTROL_0: { FETCH_CNT = 1 | DECODE_CNT = 1 } +!+ fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | 0xfc000000 } +!+ 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } +!+ fcfcfcfc VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } +!+ 000000fc VFD_CONTROL_4: 0xfc +!+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + + 00000000 VFD_CONTROL_6: { 0 } +!+ 00000001 VFD_MODE_CNTL: { BINNING_PASS } + + 00000000 VFD_UNKNOWN_A008: 0 +!+ 00000001 VFD_ADD_OFFSET: { VERTEX } + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 VFD_INSTANCE_START_OFFSET: 0 +!+ 01016000 VFD_FETCH[0].BASE: 0x1016000 + + 00000000 VFD_FETCH[0].BASE+0x1: 0 +!+ 00100000 VFD_FETCH[0].SIZE: 1048576 +!+ 0000000c VFD_FETCH[0].STRIDE: 12 +!+ c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } +!+ 00000001 VFD_DECODE[0].STEP_RATE: 0x1 +!+ 0000000f VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } +!+ 00000001 SP_UNKNOWN_A0F8: 0x1 +!+ 80100080 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | MERGEDREGS } +!+ 00000001 SP_VS_PRIMITIVE_CNTL: { OUT = 1 } +!+ 00000f00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + + 00000000 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } + + 00000000 SP_UNKNOWN_A81B: 0 +!+ 01011000 SP_VS_OBJ_START_LO: 0x1011000 base=1011000, offset=0, size=128 + + 00000000 SP_VS_OBJ_START_HI: 0 base=1011000, offset=0, size=128 +0000000001011000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 +* + :0:0000:0000[03000000x_00000000x] end + :0:0001:0001[00000000x_00000000x] nop + :0:0002:0002[00000000x_00000000x] nop + :0:0003:0003[00000000x_00000000x] nop + :0:0004:0004[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): (cnt=0, max=0) + - used (merged): (cnt=0, max=0) + - input (half): (cnt=0, max=0) + - input (full): (cnt=0, max=0) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): (cnt=0, max=0) (estimated) + - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full + - shaderdb: 0 (ss), 0 (sy) +!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } +!+ 00000001 SP_VS_INSTRLEN: 1 + + 00000000 SP_HS_UNKNOWN_A831: 0 + + 00000000 SP_HS_UNKNOWN_A833: 0 + + 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + + 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + + 00000000 SP_GS_PRIM_SIZE: 0 + + 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } +!+ 81100080 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | MERGEDREGS | 0x1000000 } + + 00000000 SP_UNKNOWN_A982: 0 + + 00000000 SP_SRGB_CNTL: { 0 } +!+ 0000000f SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } +!+ fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x } +!+ 000000fc SP_FS_OUTPUT[0].REG: { REGID = r63.x } +!+ 000000fc SP_FS_OUTPUT[0x1].REG: { REGID = r63.x } +!+ 000000fc SP_FS_OUTPUT[0x2].REG: { REGID = r63.x } +!+ 000000fc SP_FS_OUTPUT[0x3].REG: { REGID = r63.x } +!+ 000000fc SP_FS_OUTPUT[0x4].REG: { REGID = r63.x } +!+ 000000fc SP_FS_OUTPUT[0x5].REG: { REGID = r63.x } +!+ 000000fc SP_FS_OUTPUT[0x6].REG: { REGID = r63.x } +!+ 000000fc SP_FS_OUTPUT[0x7].REG: { REGID = r63.x } +!+ 00000031 SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM } +!+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } + + 00000000 SP_UNKNOWN_A9A8: 0 +!+ 00000005 SP_UNKNOWN_AB00: 0x5 +!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + + 00000000 SP_IBO_COUNT: 0 + + 00000000 SP_UNKNOWN_AE00: 0 +!+ 00001430 SP_UNKNOWN_AE03: 0x1430 +!+ 00000008 SP_UNKNOWN_AE04: 0x8 +!+ 0000003f SP_UNKNOWN_AE0F: 0x3f + + 00000000 SP_UNKNOWN_B182: 0 + + 00000000 SP_UNKNOWN_B183: 0 + + 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } +!+ 00000004 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } + + 00000000 SP_TP_SAMPLE_CONFIG: { 0 } + + 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } +!+ 000000a2 SP_TP_UNKNOWN_B309: 0xa2 +!+ 00100000 SP_UNKNOWN_B600: 0x100000 +!+ 00000044 SP_UNKNOWN_B605: 0x44 +!+ 00000100 HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED } + + 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 } + + 00000000 HLSQ_DS_CNTL: { CONSTLEN = 0 } + + 00000000 HLSQ_GS_CNTL: { CONSTLEN = 0 } +!+ 00000001 HLSQ_UNKNOWN_B980: 0x1 +!+ 00000007 HLSQ_CONTROL_1_REG: 0x7 +!+ fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } +!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } +!+ fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } +!+ 000000fc HLSQ_CONTROL_5_REG: 0xfc +!+ 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 } +!+ 00000108 HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED } + + 00000000 HLSQ_SHARED_CONSTS: { 0 } +!+ 00000080 HLSQ_UNKNOWN_BE00: 0x80 + + 00000000 HLSQ_UNKNOWN_BE01: 0 +!+ 00080000 HLSQ_UNKNOWN_BE04: 0x80000 +0000000001d8f130: 0000: 70388003 00000186 00000001 00000004 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d8f140: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 3 + :0,1,11,3 +0000000001d8f144: 0000: 48088a01 00000003 +0000000001d914cc: 0000: 70bf8003 01d8f000 00000000 00000053 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d914dc: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 12 + :0,1,12,3 +0000000001d914e0: 0000: 48088901 0000000c +t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords) + { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } + { ADDR_LO = 0 } + { ADDR_HI = 0 } +0000000001d914e8: 0000: 70438003 00040000 00000000 00000000 +t7 opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = UNK_2D } + event UNK_2D +0000000001d914f8: 0000: 70460001 0000002d +t7 opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = CACHE_INVALIDATE } + event CACHE_INVALIDATE +0000000001d91500: 0000: 70460001 00000031 +t7 opcode: CP_EVENT_WRITE (46) (5 dwords) + { EVENT = RB_DONE_TS } + { ADDR_0_LO = 0x1d90000 } + { ADDR_0_HI = 0 } + { 3 = 0x1 } + event RB_DONE_TS +0000000001d91508: 0000: 70460004 00000016 01d90000 00000000 00000001 +t7 opcode: CP_WAIT_REG_MEM (3c) (7 dwords) + { FUNCTION = WRITE_EQ | POLL_MEMORY } + { POLL_ADDR_LO = 0x1d90000 } + { POLL_ADDR_HI = 0 } + { REF = 0x1 } + { MASK = 0xffffffff } + { DELAY_LOOP_CYCLES = 0x10 } +0000000001d9151c: 0000: 70bc8006 00000013 01d90000 00000000 00000001 ffffffff 00000010 +t7 opcode: CP_EVENT_WRITE (46) (5 dwords) + { EVENT = CACHE_FLUSH_TS } + { ADDR_0_LO = 0x1d90000 } + { ADDR_0_HI = 0 } + { 3 = 0x2 } + event CACHE_FLUSH_TS +0000000001d91538: 0000: 70460004 00000004 01d90000 00000000 00000002 +t7 opcode: CP_WAIT_MEM_GTE (14) (5 dwords) + { RESERVED = 0 } + { POLL_ADDR_LO = 0x1d90000 } + { POLL_ADDR_HI = 0 } + { REF = 0x2 } +0000000001d9154c: 0000: 70940004 00000000 01d90000 00000000 00000002 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91560: 0000: 70268000 +t7 opcode: CP_WAIT_FOR_ME (13) (1 dwords) +0000000001d91564: 0000: 70138000 +t7 opcode: CP_MEM_WRITE (3d) (4 dwords) + { ADDR_LO = 0x1d90010 } + { ADDR_HI = 0 } + gpuaddr:0000000001d90010 +0000000001d91574: 0000: 00000000 +0000000001d91568: 0000: 703d8003 01d90010 00000000 00000000 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc78 } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d91578: 0000: 70450008 00000105 00000c78 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d91598: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc58 } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d9159c: 0000: 70450008 00000105 00000c58 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d915bc: 0020: 00001043 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc79 } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d915c0: 0000: 70450008 00000105 00000c79 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d915e0: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc59 } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d915e4: 0000: 70450008 00000105 00000c59 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d91604: 0020: 00001043 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc7a } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d91608: 0000: 70450008 00000105 00000c7a 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d91628: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc5a } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d9162c: 0000: 70450008 00000105 00000c5a 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d9164c: 0020: 00001043 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc7b } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d91650: 0000: 70450008 00000105 00000c7b 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d91670: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc5b } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d91674: 0000: 70450008 00000105 00000c5b 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d91694: 0020: 00001043 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc7c } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d91698: 0000: 70450008 00000105 00000c7c 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d916b8: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc5c } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d916bc: 0000: 70450008 00000105 00000c5c 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d916dc: 0020: 00001043 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc7d } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d916e0: 0000: 70450008 00000105 00000c7d 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d91700: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc5d } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d91704: 0000: 70450008 00000105 00000c5d 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d91724: 0020: 00001043 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc7e } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d91728: 0000: 70450008 00000105 00000c7e 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d91748: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc5e } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d9174c: 0000: 70450008 00000105 00000c5e 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d9176c: 0020: 00001043 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc7f } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d91770: 0000: 70450008 00000105 00000c7f 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d91790: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc5f } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d91794: 0000: 70450008 00000105 00000c5f 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d917b4: 0020: 00001043 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc80 } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d917b8: 0000: 70450008 00000105 00000c80 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d917d8: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc60 } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d917dc: 0000: 70450008 00000105 00000c60 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d917fc: 0020: 00001043 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc81 } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d91800: 0000: 70450008 00000105 00000c81 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d91820: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc61 } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d91824: 0000: 70450008 00000105 00000c61 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d91844: 0020: 00001043 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc82 } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d91848: 0000: 70450008 00000105 00000c82 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d91868: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc62 } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d9186c: 0000: 70450008 00000105 00000c62 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d9188c: 0020: 00001043 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc83 } + { POLL_ADDR_HI = 0 } + { REF = 0x440 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x441 } +0000000001d91890: 0000: 70450008 00000105 00000c83 00000000 00000440 ffffffff 01d90010 00000000 +0000000001d918b0: 0020: 00000441 +t7 opcode: CP_COND_WRITE5 (45) (9 dwords) + { FUNCTION = WRITE_GE | WRITE_MEMORY } + { POLL_ADDR_LO = 0xc63 } + { POLL_ADDR_HI = 0 } + { REF = 0x1040 } + { MASK = 0xffffffff } + { WRITE_ADDR_LO = 0x1d90010 } + { WRITE_ADDR_HI = 0 } + { WRITE_DATA = 0x1043 } +0000000001d918b4: 0000: 70450008 00000105 00000c63 00000000 00001040 ffffffff 01d90010 00000000 +0000000001d918d4: 0020: 00001043 +t7 opcode: CP_WAIT_MEM_WRITES (12) (1 dwords) +0000000001d918d8: 0000: 70928000 +t7 opcode: CP_WAIT_FOR_ME (13) (1 dwords) +0000000001d918dc: 0000: 70138000 +t7 opcode: CP_MEM_TO_REG (42) (4 dwords) + { REG = 0x883 | CNT = 0 } + { SRC = 0x1d90010 } + { SRC_HI = 0 } + base register: CP_SCRATCH[0].REG + gpuaddr:0000000001d90010 +0000000001d918e0: 0000: 70c28003 00000883 01d90010 00000000 +t7 opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0x883 | BIT = 0 | WAIT_FOR_ME } +0000000001d918f0: 0000: 70b90001 02000883 +t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) + { REG0 = 0 | MODE = PRED_TEST } + { DWORDS = 7 } +0000000001d918f8: 0000: 70c70002 10000000 00000007 +t7 opcode: CP_REG_TO_MEM (3e) (4 dwords) + { REG = 0x883 | CNT = 0 } + { DEST = 0x1d90008 } + { DEST_HI = 0 } + base register: CP_SCRATCH[0].REG + gpuaddr:0000000001d90008 +0000000001d91904: 0000: 703e8003 00000883 01d90008 00000000 +t4 write CP_SCRATCH[0].REG (0883) + CP_SCRATCH[0].REG: 0 +0000000001d91914: 0000: 48088301 00000000 +t7 opcode: CP_NOP (10) (3 dwords) +0000000001d9191c: 0000: 70100002 48088301 00000001 +t7 opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords) +0000000001d91928: 0000: 70640001 00000000 +t7 opcode: CP_SET_MODE (63) (2 dwords) +0000000001d91930: 0000: 70e30001 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91938: 0000: 70268000 +t4 write RB_CCU_CNTL (8e07) + RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM | UNK2 } +0000000001d9193c: 0000: 408e0701 7c400004 +t4 write VPC_SO_DISABLE (9306) + VPC_SO_DISABLE: { DISABLE } +0000000001d91944: 0000: 48930601 00000001 +t4 write GRAS_BIN_CONTROL (80a1) + GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | USE_VIZ | UNK22 = 0x18 } +0000000001d9194c: 0000: 4880a101 06201e11 +t4 write RB_BIN_CONTROL (8800) + RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | USE_VIZ | UNK22 = 0x18 } +0000000001d91954: 0000: 48880001 06201e11 +t4 write RB_BIN_CONTROL2 (88d3) + RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 } +0000000001d9195c: 0000: 4088d301 00001e11 +t4 write VFD_MODE_CNTL (a007) + VFD_MODE_CNTL: { 0 } +0000000001d91964: 0000: 40a00701 00000000 +t4 write PC_UNKNOWN_9805 (9805) + PC_UNKNOWN_9805: 0x1 +0000000001d9196c: 0000: 40980501 00000001 +t4 write SP_UNKNOWN_A0F8 (a0f8) + SP_UNKNOWN_A0F8: 0x1 +0000000001d91974: 0000: 40a0f801 00000001 +t7 opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords) +0000000001d9197c: 0000: 709d0001 00000001 +t7 opcode: CP_REG_WRITE (6d) (4 dwords) + { TRACKER = TRACK_RENDER_CNTL } + RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0 } +0000000001d91984: 0000: 706d8003 00000002 00008801 00000010 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91994: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 13 + :0,1,12,13 +0000000001d91998: 0000: 48088a01 0000000d +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = 0x14 | MARKER = RM6_GMEM } +0000000001d919a0: 0000: 70e50001 00000014 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d919a8: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 14 + :0,1,12,14 +0000000001d919ac: 0000: 48088a01 0000000e +t4 write GRAS_SC_WINDOW_SCISSOR_TL (80f0) + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } + GRAS_SC_WINDOW_SCISSOR_BR: { X = 543 | Y = 479 } +0000000001d919b4: 0000: 4080f002 00000000 01df021f +t4 write GRAS_2D_RESOLVE_CNTL_1 (840a) + GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 } + GRAS_2D_RESOLVE_CNTL_2: { X = 543 | Y = 479 } +0000000001d919c0: 0000: 48840a02 00000000 01df021f +t7 opcode: CP_WAIT_FOR_ME (13) (1 dwords) +0000000001d919cc: 0000: 70138000 +t7 opcode: CP_SET_MODE (63) (2 dwords) +0000000001d919d0: 0000: 70e30001 00000000 +t7 opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0x883 | BIT = 0 | WAIT_FOR_ME } +0000000001d919d8: 0000: 70b90001 02000883 +t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) + { REG0 = 0 | MODE = PRED_TEST } + { DWORDS = 11 } +0000000001d919e0: 0000: 70c70002 10000000 0000000b +t7 opcode: CP_SET_BIN_DATA5 (2f) (8 dwords) + { VSC_SIZE = 1 | VSC_N = 0 } + { BIN_DATA_ADDR_LO = 0x1d5d000 } + { BIN_DATA_ADDR_HI = 0 } + { BIN_SIZE_ADDRESS_LO = 0x1d65800 } + { BIN_SIZE_ADDRESS_HI = 0 } + { BIN_PRIM_STRM_LO = 0x1d67000 } + { BIN_PRIM_STRM_HI = 0 } +0000000001d919ec: 0000: 702f0007 00010000 01d5d000 00000000 01d65800 00000000 01d67000 00000000 +t7 opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords) +0000000001d91a0c: 0000: 70640001 00000000 +t7 opcode: CP_NOP (10) (3 dwords) +0000000001d91a14: 0000: 70100002 70640001 00000001 +t4 write RB_WINDOW_OFFSET (8890) + RB_WINDOW_OFFSET: { X = 0 | Y = 0 } +0000000001d91a20: 0000: 48889001 00000000 +t4 write RB_WINDOW_OFFSET2 (88d4) + RB_WINDOW_OFFSET2: { X = 0 | Y = 0 } +0000000001d91a28: 0000: 4888d401 00000000 +t4 write SP_WINDOW_OFFSET (b4d1) + SP_WINDOW_OFFSET: { X = 0 | Y = 0 } +0000000001d91a30: 0000: 48b4d101 00000000 +t4 write SP_TP_WINDOW_OFFSET (b307) + SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } +0000000001d91a38: 0000: 48b30701 00000000 +t4 write GRAS_BIN_CONTROL (80a1) + GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 } +0000000001d91a40: 0000: 4880a101 06001e11 +t4 write RB_BIN_CONTROL (8800) + RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 } +0000000001d91a48: 0000: 48880001 06001e11 +t4 write RB_BIN_CONTROL2 (88d3) + RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 } +0000000001d91a50: 0000: 4088d301 00001e11 +t7 opcode: CP_SET_MODE (63) (2 dwords) +0000000001d91a58: 0000: 70e30001 00000000 +t4 write RB_SAMPLE_CONFIG (8804) + RB_SAMPLE_CONFIG: { 0 } +0000000001d91a60: 0000: 40880401 00000000 +t4 write SP_TP_SAMPLE_CONFIG (b304) + SP_TP_SAMPLE_CONFIG: { 0 } +0000000001d91a68: 0000: 48b30401 00000000 +t4 write GRAS_SAMPLE_CONFIG (80a4) + GRAS_SAMPLE_CONFIG: { 0 } +0000000001d91a70: 0000: 4880a401 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91a78: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 15 + :0,1,15,14 +0000000001d91a7c: 0000: 48088901 0000000f +t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + ibaddr:00000000011160d0 + ibsize:00000018 +t4 write RB_BLIT_SCISSOR_TL (88d1) + RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } + RB_BLIT_SCISSOR_BR: { X = 2175 | Y = 1439 } +00000000011160d0: 0000: 4888d102 00000000 059f087f +t4 write RB_BLIT_DST_INFO (88d7) + RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM } +00000000011160dc: 0000: 4888d701 00001880 +t4 write RB_BLIT_INFO (88e3) + RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf } +00000000011160e4: 0000: 4088e301 000000f2 +t4 write RB_BLIT_BASE_GMEM (88d6) + RB_BLIT_BASE_GMEM: 0 +00000000011160ec: 0000: 4088d601 00000000 +t4 write RB_UNKNOWN_88D0 (88d0) + RB_UNKNOWN_88D0: { 0 } +00000000011160f4: 0000: 4088d001 00000000 +t4 write RB_BLIT_CLEAR_COLOR_DW0 (88df) + RB_BLIT_CLEAR_COLOR_DW0: 0 + RB_BLIT_CLEAR_COLOR_DW1: 0 + RB_BLIT_CLEAR_COLOR_DW2: 0 + RB_BLIT_CLEAR_COLOR_DW3: 0 +00000000011160fc: 0000: 4088df04 00000000 00000000 00000000 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001116110: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 5 + :0,1,15,5 +0000000001116114: 0000: 48088a01 00000005 +t7 opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = BLIT } + event BLIT + mode: RM6_GMEM + skip_ib2: g=1, l=0 + draw[1] register values + + 00000000 CP_SCRATCH[0].REG: 0 +!+ 0000000f CP_SCRATCH[0x6].REG: 15 + :0,1,15,5 +!+ 00000005 CP_SCRATCH[0x7].REG: 5 + :0,1,15,5 +!+ 06001e11 GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 } + + 00000000 GRAS_SAMPLE_CONFIG: { 0 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 01df021f GRAS_SC_WINDOW_SCISSOR_BR: { X = 543 | Y = 479 } + + 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 } +!+ 01df021f GRAS_2D_RESOLVE_CNTL_2: { X = 543 | Y = 479 } +!+ 06001e11 RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 } +!+ 00000010 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0 } + + 00000000 RB_SAMPLE_CONFIG: { 0 } + + 00000000 RB_WINDOW_OFFSET: { X = 0 | Y = 0 } + + 00000000 RB_UNKNOWN_88D0: { 0 } + + 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 059f087f RB_BLIT_SCISSOR_BR: { X = 2175 | Y = 1439 } + + 00001e11 RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 } + + 00000000 RB_WINDOW_OFFSET2: { X = 0 | Y = 0 } + + 00000000 RB_BLIT_BASE_GMEM: 0 +!+ 00001880 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM } + + 00000000 RB_BLIT_CLEAR_COLOR_DW0: 0 + + 00000000 RB_BLIT_CLEAR_COLOR_DW1: 0 + + 00000000 RB_BLIT_CLEAR_COLOR_DW2: 0 + + 00000000 RB_BLIT_CLEAR_COLOR_DW3: 0 +!+ 000000f2 RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf } + + 7c400004 RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM | UNK2 } +!+ 00000001 VPC_SO_DISABLE: { DISABLE } + + 00000001 PC_UNKNOWN_9805: 0x1 +!+ 00000000 VFD_MODE_CNTL: { 0 } + + 00000001 SP_UNKNOWN_A0F8: 0x1 + + 00000000 SP_TP_SAMPLE_CONFIG: { 0 } + + 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } + + 00000000 SP_WINDOW_OFFSET: { X = 0 | Y = 0 } +000000000111611c: 0000: 70460001 0000001e +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001116124: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 6 + :0,1,15,6 +0000000001116128: 0000: 48088a01 00000006 +0000000001d91a84: 0000: 70bf8003 011160d0 00000000 00000018 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91a94: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 16 + :0,1,16,6 +0000000001d91a98: 0000: 48088901 00000010 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91aa0: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 17 + :0,1,17,6 +0000000001d91aa4: 0000: 48088901 00000011 +t7 opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0xc38 | BIT = 0 | WAIT_FOR_ME } +0000000001d91aac: 0000: 70b90001 02000c38 +t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) + { REG0 = 0 | MODE = PRED_TEST } + { DWORDS = 4 } +0000000001d91ab4: 0000: 70c70002 10000000 00000004 +t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + ibaddr:0000000001d8f000 + ibsize:00000053 +t4 write VFD_INDEX_OFFSET (a00e) + VFD_INDEX_OFFSET: 0 +0000000001d8f000: 0000: 40a00e01 00000000 +t4 write VFD_INSTANCE_START_OFFSET (a00f) + VFD_INSTANCE_START_OFFSET: 0 +0000000001d8f008: 0000: 48a00f01 00000000 +t4 write PC_RESTART_INDEX (9803) + PC_RESTART_INDEX: 4294967295 +0000000001d8f010: 0000: 40980301 ffffffff +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d8f018: 0000: 70268000 +t4 write CP_SCRATCH[0x5].REG (0888) + CP_SCRATCH[0x5].REG: 1 + :0,1,17,6 +0000000001d8f01c: 0000: 40088801 00000001 +t4 write RB_STENCILREF (8887) + RB_STENCILREF: { REF = 0 | BFREF = 0 } +0000000001d8f024: 0000: 48888701 00000000 +t4 write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0) + GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 } + GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 2159 | Y = 1439 } +0000000001d8f02c: 0000: 4880b002 00000000 059f086f +t4 write GRAS_CL_VPORT[0].XOFFSET (8010) + GRAS_CL_VPORT[0].XOFFSET: 1080.000000 + GRAS_CL_VPORT[0].XSCALE: 1080.000000 + GRAS_CL_VPORT[0].YOFFSET: 720.000000 + GRAS_CL_VPORT[0].YSCALE: 720.000000 + GRAS_CL_VPORT[0].ZOFFSET: 0.500000 + GRAS_CL_VPORT[0].ZSCALE: 0.500000 +0000000001d8f038: 0000: 48801086 44870000 44870000 44340000 44340000 3f000000 3f000000 +t4 write GRAS_SC_VIEWPORT_SCISSOR[0].TL (80d0) + GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 } + GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 2159 | Y = 1439 } +0000000001d8f054: 0000: 4880d002 00000000 059f086f +t4 write GRAS_CL_GUARDBAND_CLIP_ADJ (8006) + GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 311 | VERT = 349 } +0000000001d8f060: 0000: 40800601 00057537 +t4 write RB_BLEND_CNTL (8865) + RB_BLEND_CNTL: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } +0000000001d8f068: 0000: 48886501 ffff0000 +t4 write RB_BLEND_RED_F32 (8860) + RB_BLEND_RED_F32: 0.000000 + RB_BLEND_GREEN_F32: 0.000000 + RB_BLEND_BLUE_F32: 0.000000 + RB_BLEND_ALPHA_F32: 0.000000 +0000000001d8f070: 0000: 48886004 00000000 00000000 00000000 00000000 +t7 opcode: CP_SET_DRAW_STATE (43) (40 dwords) + { COUNT = 12 | BINNING | GMEM | SYSMEM | GROUP_ID = 7 } + { ADDR_LO = 0x1116000 } + { ADDR_HI = 0 } + { COUNT = 9 | BINNING | GMEM | SYSMEM | GROUP_ID = 22 } + { ADDR_LO = 0x111e000 } + { ADDR_HI = 0 } + { COUNT = 21 | BINNING | GMEM | SYSMEM | GROUP_ID = 0 } + { ADDR_LO = 0x111f000 } + { ADDR_HI = 0 } + { COUNT = 192 | GMEM | SYSMEM | GROUP_ID = 1 } + { ADDR_LO = 0x1120000 } + { ADDR_HI = 0 } + { COUNT = 95 | BINNING | GROUP_ID = 2 } + { ADDR_LO = 0x1121000 } + { ADDR_HI = 0 } + { COUNT = 18 | GMEM | SYSMEM | GROUP_ID = 3 } + { ADDR_LO = 0x1122000 } + { ADDR_HI = 0 } + { COUNT = 14 | BINNING | GMEM | SYSMEM | GROUP_ID = 21 } + { ADDR_LO = 0x1123000 } + { ADDR_HI = 0 } + { COUNT = 5 | GMEM | SYSMEM | GROUP_ID = 4 } + { ADDR_LO = 0x1116030 } + { ADDR_HI = 0 } + { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 8 } + { ADDR_LO = 0 } + { ADDR_HI = 0 } + { COUNT = 20 | GMEM | SYSMEM | GROUP_ID = 12 } + { ADDR_LO = 0x1116050 } + { ADDR_HI = 0 } + { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 13 } + { ADDR_LO = 0 } + { ADDR_HI = 0 } + { COUNT = 36 | GMEM | SYSMEM | GROUP_ID = 23 } + { ADDR_LO = 0x1124000 } + { ADDR_HI = 0 } + { COUNT = 9 | GMEM | SYSMEM | GROUP_ID = 20 } + { ADDR_LO = 0x11160a0 } + { ADDR_HI = 0 } +0000000001d8f084: 0000: 70438027 0770000c 01116000 00000000 16700009 0111e000 00000000 00700015 +0000000001d8f0a4: 0020: 0111f000 00000000 016000c0 01120000 00000000 0210005f 01121000 00000000 +0000000001d8f0c4: 0040: 03600012 01122000 00000000 1570000e 01123000 00000000 04600005 01116030 +0000000001d8f0e4: 0060: 00000000 08720000 00000000 00000000 0c600014 01116050 00000000 0d720000 +0000000001d8f104: 0080: 00000000 00000000 17600024 01124000 00000000 14600009 011160a0 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d8f124: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 2 + :0,1,17,2 +0000000001d8f128: 0000: 48088a01 00000002 + group_id: 0 + count: 21 + addr: 000000000111f000 + flags: 0 + enable_mask: 0x7 +000000000111f000: 0000: 40bb0801 000000ff 48b80004 00000100 00000000 00000000 00000000 40bb1001 +000000000111f020: 0020: 00000108 48a82301 00000100 48a83b01 00000000 40a86301 00000000 48a89401 +000000000111f040: 0040: 00000000 48ab0401 00000100 48ab2001 00000000 +t4 write HLSQ_INVALIDATE_CMD (bb08) + HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 } +000000000111f000: 0000: 40bb0801 000000ff +t4 write HLSQ_VS_CNTL (b800) + HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED } + HLSQ_HS_CNTL: { CONSTLEN = 0 } + HLSQ_DS_CNTL: { CONSTLEN = 0 } + HLSQ_GS_CNTL: { CONSTLEN = 0 } +000000000111f008: 0000: 48b80004 00000100 00000000 00000000 00000000 +t4 write HLSQ_FS_CNTL (bb10) + HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED } +000000000111f01c: 0000: 40bb1001 00000108 +t4 write SP_VS_CONFIG (a823) + SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } +000000000111f024: 0000: 48a82301 00000100 +t4 write SP_HS_CONFIG (a83b) + SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } +000000000111f02c: 0000: 48a83b01 00000000 +t4 write SP_DS_CONFIG (a863) + SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } +000000000111f034: 0000: 40a86301 00000000 +t4 write SP_GS_CONFIG (a894) + SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } +000000000111f03c: 0000: 48a89401 00000000 +t4 write SP_FS_CONFIG (ab04) + SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } +000000000111f044: 0000: 48ab0401 00000100 +t4 write SP_IBO_COUNT (ab20) + SP_IBO_COUNT: 0 +000000000111f04c: 0000: 48ab2001 00000000 + group_id: 1 + count: 192 + addr: 0000000001120000 + flags: 0 + enable_mask: 0x6 +0000000001120000: 0000: 40a83301 00000000 40a99e01 00007fc0 40a9a801 00000000 40ab0001 00000005 +0000000001120020: 0020: 40a98c01 fcfcfc00 40a80001 80100080 40a82401 00000001 48a81c02 01012000 +0000000001120040: 0040: 00000000 70328003 00620000 01012000 00000000 40921204 ffffffff ffffffff +0000000001120060: 0060: ffffffff ffffffff 40a80301 00000f00 48a81301 00000000 48a83101 00000000 +0000000001120080: 0080: 48a80201 00000001 40930401 ff00ff00 489b0101 00000004 409b0301 00000000 +00000000011200a0: 00a0: 40b98285 00000007 fcfcfcfc fcfcfcfc 1513fcfc 000000fc 48b98001 00000001 +00000000011200c0: 00c0: 40a98001 81508980 48a98201 00000000 48910401 0000ffff 40800501 000003c8 +00000000011200e0: 00e0: 48880902 000003c8 00000000 40881001 00000000 40810101 00000000 48810901 +0000000001120100: 0100: 00000000 48a98e08 00000004 00000004 00000004 00000004 00000004 00000004 +0000000001120120: 0120: 00000004 00000004 40930101 00ff0004 409b0601 00000000 40a87101 00000000 +0000000001120140: 0140: 48910101 00ffff00 48910701 00000000 40ab0501 00000058 40a98302 01013000 +0000000001120160: 0160: 00000000 70348003 16320000 01013000 00000000 40a00186 fcfcfcfc 0000fcfc +0000000001120180: 0180: fcfcfcfc 000000fc 0000fcfc 00000000 40887001 00000000 48809401 00000000 +00000000011201a0: 01a0: 70340057 05704008 00000000 00000000 3fc00000 40000000 3f800000 40c90fdb +00000000011201c0: 01c0: 3e22f983 3f000000 c0490fdb 3ecccccd 3fa00000 40400000 3d4ccccd 3d75c28f +00000000011201e0: 01e0: c00ccccd 3e4ccccd 3fb8aa3b 3da3d70a bd4cccd0 3fd9999a 3f28f5c2 40600000 +0000000001120200: 0200: 3e6147ae 3f066666 3e333333 3dcccccd 3f1c28f6 3f400000 3f866666 3f215273 +0000000001120220: 0220: bfd91db5 be976a6f 3f8f5c29 3fabee11 3e95d327 3f978829 3f8a6d28 3f24b766 +0000000001120240: 0240: bfb16aad 3f11eb85 3fbc28f5 3fc8b439 3ea6594b 4003b646 400c7e28 3e3da33c +0000000001120260: 0260: 40386594 4044b09f 3dd82fd9 c0200000 3e99999a c0700000 be1d89d9 40133333 +0000000001120280: 0280: 3d3851eb 3f4ccccd 3e800000 3de38e39 3a83126f 3eb33333 3d99999a 400ccccd +00000000011202a0: 02a0: 3dd70a3e 3d3851ec 40d9999a 3d4ac083 3ba3d70a 3de147ae 358637bd 33d6bf95 +00000000011202c0: 02c0: 3f0ccccd 41800000 45070000 44b40000 3df5c28f 3f333333 3f266666 3f7851ec +00000000011202e0: 02e0: 3f19999a 3f666666 3f7d70a4 40100000 00000000 3db851ec 00000000 07ee25f4 +t4 write SP_HS_UNKNOWN_A833 (a833) + SP_HS_UNKNOWN_A833: 0 +0000000001120000: 0000: 40a83301 00000000 +t4 write SP_FS_PREFETCH_CNTL (a99e) + SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } +0000000001120008: 0000: 40a99e01 00007fc0 +t4 write SP_UNKNOWN_A9A8 (a9a8) + SP_UNKNOWN_A9A8: 0 +0000000001120010: 0000: 40a9a801 00000000 +t4 write SP_UNKNOWN_AB00 (ab00) + SP_UNKNOWN_AB00: 0x5 +0000000001120018: 0000: 40ab0001 00000005 +t4 write SP_FS_OUTPUT_CNTL0 (a98c) + SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x } +0000000001120020: 0000: 40a98c01 fcfcfc00 +t4 write SP_VS_CTRL_REG0 (a800) + SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | MERGEDREGS } +0000000001120028: 0000: 40a80001 80100080 +t4 write SP_VS_INSTRLEN (a824) + SP_VS_INSTRLEN: 1 +0000000001120030: 0000: 40a82401 00000001 +t4 write SP_VS_OBJ_START_LO (a81c) + SP_VS_OBJ_START_LO: 0x1012000 base=1012000, offset=0, size=128 + SP_VS_OBJ_START_HI: 0 base=1012000, offset=0, size=128 +0000000001012000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 +* + :0:0000:0000[03000000x_00000000x] end + :0:0001:0001[00000000x_00000000x] nop + :0:0002:0002[00000000x_00000000x] nop + :0:0003:0003[00000000x_00000000x] nop + :0:0004:0004[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): (cnt=0, max=0) + - used (merged): (cnt=0, max=0) + - input (half): (cnt=0, max=0) + - input (full): (cnt=0, max=0) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): (cnt=0, max=0) (estimated) + - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full + - shaderdb: 0 (ss), 0 (sy) +0000000001120038: 0000: 48a81c02 01012000 00000000 +t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords) + { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 } + { EXT_SRC_ADDR = 0x1012000 } + { EXT_SRC_ADDR_HI = 0 } + :0:0000:0000[03000000x_00000000x] end + :0:0001:0001[00000000x_00000000x] nop + :0:0002:0002[00000000x_00000000x] nop + :0:0003:0003[00000000x_00000000x] nop + :0:0004:0004[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): (cnt=0, max=0) + - used (merged): (cnt=0, max=0) + - input (half): (cnt=0, max=0) + - input (full): (cnt=0, max=0) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): (cnt=0, max=0) (estimated) + - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full + - shaderdb: 0 (ss), 0 (sy) +0000000001120044: 0000: 70328003 00620000 01012000 00000000 +t4 write VPC_VAR[0].DISABLE (9212) + VPC_VAR[0].DISABLE: 0xffffffff + VPC_VAR[0x1].DISABLE: 0xffffffff + VPC_VAR[0x2].DISABLE: 0xffffffff + VPC_VAR[0x3].DISABLE: 0xffffffff +0000000001120054: 0000: 40921204 ffffffff ffffffff ffffffff ffffffff +t4 write SP_VS_OUT[0].REG (a803) + SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +0000000001120068: 0000: 40a80301 00000f00 +t4 write SP_VS_VPC_DST[0].REG (a813) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } +0000000001120070: 0000: 48a81301 00000000 +t4 write SP_HS_UNKNOWN_A831 (a831) + SP_HS_UNKNOWN_A831: 0 +0000000001120078: 0000: 48a83101 00000000 +t4 write SP_VS_PRIMITIVE_CNTL (a802) + SP_VS_PRIMITIVE_CNTL: { OUT = 1 } +0000000001120080: 0000: 48a80201 00000001 +t4 write VPC_CNTL_0 (9304) + VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | UNKLOC = 255 } +0000000001120088: 0000: 40930401 ff00ff00 +t4 write PC_VS_OUT_CNTL (9b01) + PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 4 | CLIP_MASK = 0 } +0000000001120090: 0000: 489b0101 00000004 +t4 write PC_PRIMITIVE_CNTL_3 (9b03) + PC_PRIMITIVE_CNTL_3: 0 +0000000001120098: 0000: 409b0301 00000000 +t4 write HLSQ_CONTROL_1_REG (b982) + HLSQ_CONTROL_1_REG: 0x7 + HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r4.w | ZWCOORDREGID = r5.y } + HLSQ_CONTROL_5_REG: 0xfc +00000000011200a0: 0000: 40b98285 00000007 fcfcfcfc fcfcfcfc 1513fcfc 000000fc +t4 write HLSQ_UNKNOWN_B980 (b980) + HLSQ_UNKNOWN_B980: 0x1 +00000000011200b8: 0000: 48b98001 00000001 +t4 write SP_FS_CTRL_REG0 (a980) + SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 19 | BRANCHSTACK = 2 | THREADSIZE = FOUR_QUADS | VARYING | MERGEDREGS | 0x1000000 } +00000000011200c0: 0000: 40a98001 81508980 +t4 write SP_UNKNOWN_A982 (a982) + SP_UNKNOWN_A982: 0 +00000000011200c8: 0000: 48a98201 00000000 +t4 write VPC_VS_LAYER_CNTL (9104) + VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } +00000000011200d0: 0000: 48910401 0000ffff +t4 write GRAS_CNTL (8005) + GRAS_CNTL: { SIZE | COORD_MASK = 0xf } +00000000011200d8: 0000: 40800501 000003c8 +t4 write RB_RENDER_CONTROL0 (8809) + RB_RENDER_CONTROL0: { SIZE | COORD_MASK = 0xf } + RB_RENDER_CONTROL1: { 0 } +00000000011200e0: 0000: 48880902 000003c8 00000000 +t4 write RB_SAMPLE_CNTL (8810) + RB_SAMPLE_CNTL: { 0 } +00000000011200ec: 0000: 40881001 00000000 +t4 write GRAS_UNKNOWN_8101 (8101) + GRAS_UNKNOWN_8101: 0 +00000000011200f4: 0000: 40810101 00000000 +t4 write GRAS_SAMPLE_CNTL (8109) + GRAS_SAMPLE_CNTL: { 0 } +00000000011200fc: 0000: 48810901 00000000 +t4 write SP_FS_OUTPUT[0].REG (a98e) + SP_FS_OUTPUT[0].REG: { REGID = r1.x } + SP_FS_OUTPUT[0x1].REG: { REGID = r1.x } + SP_FS_OUTPUT[0x2].REG: { REGID = r1.x } + SP_FS_OUTPUT[0x3].REG: { REGID = r1.x } + SP_FS_OUTPUT[0x4].REG: { REGID = r1.x } + SP_FS_OUTPUT[0x5].REG: { REGID = r1.x } + SP_FS_OUTPUT[0x6].REG: { REGID = r1.x } + SP_FS_OUTPUT[0x7].REG: { REGID = r1.x } +0000000001120104: 0000: 48a98e08 00000004 00000004 00000004 00000004 00000004 00000004 00000004 +0000000001120124: 0020: 00000004 +t4 write VPC_VS_PACK (9301) + VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 } +0000000001120128: 0000: 40930101 00ff0004 +t4 write PC_PRIMITIVE_CNTL_6 (9b06) + PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } +0000000001120130: 0000: 409b0601 00000000 +t4 write SP_GS_PRIM_SIZE (a871) + SP_GS_PRIM_SIZE: 0 +0000000001120138: 0000: 40a87101 00000000 +t4 write VPC_VS_CLIP_CNTL (9101) + VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } +0000000001120140: 0000: 48910101 00ffff00 +t4 write VPC_UNKNOWN_9107 (9107) + VPC_UNKNOWN_9107: 0 +0000000001120148: 0000: 48910701 00000000 +t4 write SP_FS_INSTRLEN (ab05) + SP_FS_INSTRLEN: 88 +0000000001120150: 0000: 40ab0501 00000058 +t4 write SP_FS_OBJ_START_LO (a983) + SP_FS_OBJ_START_LO: 0x1013000 base=1013000, offset=0, size=11264 + SP_FS_OBJ_START_HI: 0 base=1013000, offset=0, size=11264 +0000000001013000: 0000: 40400000 204cc000 00000000 204cc006 3e99999a 204cc004 20080014 42700008 +0000000001013020: 0020: 10331003 6380000c 00000006 200cc00d 00041003 40700004 00000000 20244014 +0000000001013040: 0040: 1036000c 4070000e 0000000d 200cc005 1034000c 4070000f 10251024 63820004 +0000000001013060: 0060: 10251024 6387000d 800c1003 6380000c 10251024 6387800e 00000004 41300010 +0000000001013080: 0080: 0000000d 41300011 00000005 200cc00f 0000000e 41300012 40100004 40100004 +00000000010130a0: 00a0: 4011000d 4010000d 00001003 40700011 4012000e 4010000e 10261023 63820004 +00000000010130c0: 00c0: 10261023 6386800d 20080013 42700010 10261023 6387000e 40141066 4010001b +00000000010130e0: 00e0: 00141025 40700016 00000014 80100014 20040008 46f00008 00000004 80900000 + :1:0000:0000[204cc000x_40400000x] mov.u32u32 r0.x, 0x40400000 + :1:0001:0001[204cc006x_00000000x] mov.u32u32 r1.z, 0x00000000 + :1:0002:0002[204cc004x_3e99999ax] mov.u32u32 r1.x, 0x3e99999a + :2:0003:0003[42700008x_20080014x] sub.s r2.x, r5.x, 8 + :3:0004:0004[6380000cx_10331003x] mad.f32 r3.x, c0.w, r0.x, c12.w + :1:0005:0005[200cc00dx_00000006x] mov.u32u32 r3.y, r1.z + :2:0006:0006[40700004x_00041003x] mul.f r1.x, c0.w, r1.x + :1:0007:0007[20244014x_00000000x] mov.f32f32 r5.x, c0.x + :2:0008:0008[4070000ex_1036000cx] mul.f r3.z, r3.x, c13.z + :1:0009:0009[200cc005x_0000000dx] mov.u32u32 r1.y, r3.y + :2:0010:0010[4070000fx_1034000cx] mul.f r3.w, r3.x, c13.x + :3:0011:0011[63820004x_10251024x] mad.f32 r1.x, c9.x, r1.x, c9.y + :3:0012:0012[6387000dx_10251024x] mad.f32 r3.y, c9.x, r3.z, c9.y + :3:0013:0013[6380000cx_800c1003x] mad.f32 r3.x, c0.w, r0.x, (neg)r3.x + :3:0014:0014[6387800ex_10251024x] mad.f32 r3.z, c9.x, r3.w, c9.y + :2:0015:0015[41300010x_00000004x] floor.f r4.x, r1.x + :2:0016:0016[41300011x_0000000dx] floor.f r4.y, r3.y + :1:0017:0017[200cc00fx_00000005x] mov.u32u32 r3.w, r1.y + :2:0018:0018[41300012x_0000000ex] floor.f r4.z, r3.z + :2:0019:0019[40100004x_40100004x] add.f r1.x, r1.x, (neg)r4.x + :2:0020:0020[4010000dx_4011000dx] add.f r3.y, r3.y, (neg)r4.y + :2:0021:0021[40700011x_00001003x] mul.f r4.y, c0.w, r0.x + :2:0022:0022[4010000ex_4012000ex] add.f r3.z, r3.z, (neg)r4.z + :3:0023:0023[63820004x_10261023x] mad.f32 r1.x, c8.w, r1.x, c9.z + :3:0024:0024[6386800dx_10261023x] mad.f32 r3.y, c8.w, r3.y, c9.z + :2:0025:0025[42700010x_20080013x] sub.s r4.x, r4.w, 8 + :3:0026:0026[6387000ex_10261023x] mad.f32 r3.z, c8.w, r3.z, c9.z + :2:0027:0027[4010001bx_40141066x] add.f r6.w, c25.z, (neg)r5.x + :2:0028:0028[40700016x_00141025x] mul.f r5.z, c9.y, r5.x + :4:0029:0029[80100014x_00000014x] rcp r5.x, r5.x + :2:0030:0030[46f00008x_20040008x] shr.b r2.x, r2.x, 4 + :4:0031:0031[80900000x_00000004x] sin r0.x, r1.x + :2:0032:0032[40101000x_10270000x] (ss)add.f r0.x, r0.x, c9.w + :4:0033:0033[80b00004x_0000000dx] cos r1.x, r3.y + :2:0034:0034[4078001bx_1025001bx] (nop2) mul.f r6.w, r6.w, c9.y + :2:0035:0037[40700400x_10280000x] (sat)mul.f r0.x, r0.x, c10.x + :4:0036:0038[8090100dx_0000000ex] (ss)sin r3.y, r3.z + :2:0037:0039[46f0100ex_20040010x] (ss)shr.b r3.z, r4.x, 4 + :2:0038:0040[40700010x_00041031x] mul.f r4.x, c12.y, r1.x + :1:0039:0041[200c4008x_00000008x] cov.u32f32 r2.x, r2.x + :2:0040:0042[40700012x_1021000dx] mul.f r4.z, r3.y, c8.y + :1:0041:0043[200c4004x_0000000ex] cov.u32f32 r1.x, r3.z + :2:0042:0044[4070000ex_00001021x] mul.f r3.z, c8.y, r0.x + :2:0043:0045[4070000dx_000d1031x] mul.f r3.y, c12.y, r3.y + :2:0044:0046[40100008x_10250008x] add.f r2.x, r2.x, c9.y + :2:0045:0047[40100013x_10250004x] add.f r4.w, r1.x, c9.y + :2:0046:0048[40180804x_400e1029x] (nop3) add.f r1.x, c10.y, (neg)r3.z + :2:0047:0052[40700004x_00040000x] mul.f r1.x, r0.x, r1.x + :2:0048:0053[40100017x_40160013x] add.f r5.w, r4.w, (neg)r5.z + :2:0049:0054[40100013x_401b0013x] add.f r4.w, r4.w, (neg)r6.w + :3:0050:0055[63840008x_10091008x] mad.f32 r2.x, c2.x, r2.x, c2.y + :2:0051:0056[4070000ex_00040000x] mul.f r3.z, r0.x, r1.x + :1:0052:0057[204cc004x_3fc00000x] mov.u32u32 r1.x, 0x3fc00000 + :1:0053:0058[200cc003x_0000000fx] mov.u32u32 r0.w, r3.w + :1:0054:0059[2024400fx_00000003x] mov.f32f32 r3.w, c0.w + :2:0055:0060[40700013x_00140013x] mul.f r4.w, r4.w, r5.x + :2:0056:0061[40100016x_40161004x] add.f r5.z, c1.x, (neg)r5.z + :1:0057:0062[200cc000x_00000003x] mov.u32u32 r0.x, r0.w + :3:0058:0063[6387801ax_10251024x] mad.f32 r6.z, c9.x, r3.w, c9.y + :2:0059:0064[40700019x_000f1032x] mul.f r6.y, c12.z, r3.w + :2:0060:0065[40700015x_000f1035x] mul.f r5.y, c13.y, r3.w + :1:0061:0066[200cc002x_00000000x] mov.u32u32 r0.z, r0.x + :2:0062:0067[4130001cx_0000001ax] floor.f r7.x, r6.z + :3:0063:0068[638c8019x_10251024x] mad.f32 r6.y, c9.x, r6.y, c9.y + :3:0064:0069[638a8015x_10251024x] mad.f32 r5.y, c9.x, r5.y, c9.y + :1:0065:0070[200cc000x_00000002x] mov.u32u32 r0.x, r0.z + :2:0066:0071[4018081ax_401c001ax] (nop3) add.f r6.z, r6.z, (neg)r7.x + :3:0067:0075[638d001ax_10261023x] mad.f32 r6.z, c8.w, r6.z, c9.z + :2:0068:0076[41300018x_00000015x] floor.f r6.x, r5.y + :1:0069:0077[200cc001x_00000000x] mov.u32u32 r0.y, r0.x + :0:0070:0078[00000300x_00000000x] (rpt3)nop + :4:0071:0082[80900014x_0000001ax] sin r5.x, r6.z + :2:0072:0083[4130101ax_00000019x] (ss)floor.f r6.z, r6.y + :2:0073:0084[40100015x_40180015x] add.f r5.y, r5.y, (neg)r6.x + :1:0074:0085[200cc000x_00000001x] mov.u32u32 r0.x, r0.y + :2:0075:0086[40700014x_10250014x] mul.f r5.x, r5.x, c9.y + :2:0076:0087[40100019x_401a0019x] add.f r6.y, r6.y, (neg)r6.z + :3:0077:0088[638a8015x_10269023x] (nop2) mad.f32 r5.y, c8.w, r5.y, c9.z + :3:0078:0091[638c8819x_10269023x] (nop3) mad.f32 r6.y, c8.w, r6.y, c9.z + :0:0079:0095[00000200x_00000000x] (rpt2)nop + :4:0080:0098[80900019x_00000019x] sin r6.y, r6.y + :4:0081:0099[80b00015x_00000015x] cos r5.y, r5.y + :3:0082:0100[638c9014x_00141031x] (ss)mad.f32 r5.x, c12.y, r6.y, r5.x + :3:0083:0101[638a8010x_80101031x] mad.f32 r4.x, c12.y, r5.y, (neg)r4.x + :2:0084:0102[40700815x_00151031x] (nop1) mul.f r5.y, c12.y, r5.y + :2:0085:0104[4010000dx_400d0014x] add.f r3.y, r5.x, (neg)r3.y + :2:0086:0105[40780018x_00100010x] (nop2) mul.f r6.x, r4.x, r4.x + :3:0087:0108[63868818x_0018000dx] (nop1) mad.f32 r6.x, r3.y, r3.y, r6.x + :3:0088:0110[63860818x_0018800cx] (nop3) mad.f32 r6.x, r3.x, r3.x, r6.x + :0:0089:0114[00000200x_00000000x] (rpt2)nop + :4:0090:0117[80300018x_00000018x] rsq r6.x, r6.x + :2:0091:0118[4070100cx_0018000cx] (ss)mul.f r3.x, r3.x, r6.x + :2:0092:0119[40700010x_00180010x] mul.f r4.x, r4.x, r6.x + :2:0093:0120[4070080dx_0018000dx] (nop1) mul.f r3.y, r3.y, r6.x + :2:0094:0122[40700818x_000c000cx] (nop1) mul.f r6.x, r3.x, r3.x + :3:0095:0124[63868818x_0018800dx] (nop3) mad.f32 r6.x, r3.y, r3.y, r6.x + :0:0096:0128[00000200x_00000000x] (rpt2)nop + :4:0097:0131[80300018x_00000018x] rsq r6.x, r6.x + :2:0098:0132[40701019x_0018000cx] (ss)mul.f r6.y, r3.x, r6.x + :2:0099:0133[40780018x_0018000dx] (nop2) mul.f r6.x, r3.y, r6.x + :2:0100:0136[4070001ax_000c0019x] mul.f r6.z, r6.y, r3.x + :2:0101:0137[40700019x_00100019x] mul.f r6.y, r6.y, r4.x + :3:0102:0138[6386801ax_001a0018x] mad.f32 r6.z, r6.x, r3.y, r6.z + :2:0103:0139[40780018x_00100018x] (nop2) mul.f r6.x, r6.x, r4.x + :2:0104:0142[4070081bx_001a001ax] (nop1) mul.f r6.w, r6.z, r6.z + :3:0105:0144[638c081bx_401b4018x] (nop1) mad.f32 r6.w, (neg)r6.x, (neg)r6.x, r6.w + :3:0106:0146[638c881bx_401bc019x] (nop3) mad.f32 r6.w, (neg)r6.y, (neg)r6.y, r6.w + :0:0107:0150[00000200x_00000000x] (rpt2)nop + :4:0108:0153[8030001bx_0000001bx] rsq r6.w, r6.w + :2:0109:0154[40701018x_001b0018x] (ss)mul.f r6.x, r6.x, r6.w + :2:0110:0155[4070001ax_001b001ax] mul.f r6.z, r6.z, r6.w + :2:0111:0156[40700819x_001b0019x] (nop1) mul.f r6.y, r6.y, r6.w + :2:0112:0158[4070001bx_000c0018x] mul.f r6.w, r6.x, r3.x + :2:0113:0159[4070001ex_000d001ax] mul.f r7.z, r6.z, r3.y + :2:0114:0160[4070001dx_00100019x] mul.f r7.y, r6.y, r4.x + :3:0115:0161[6386801bx_001b4019x] mad.f32 r6.w, (neg)r6.y, r3.y, r6.w + :3:0116:0162[6386001dx_001d001ax] mad.f32 r7.y, r6.z, r3.x, r7.y + :3:0117:0163[6388081ex_801e4018x] (nop1) mad.f32 r7.z, (neg)r6.x, r4.x, (neg)r7.z + :2:0118:0165[4070081cx_001b001bx] (nop1) mul.f r7.x, r6.w, r6.w + :3:0119:0167[638e881cx_001c001dx] (nop1) mad.f32 r7.x, r7.y, r7.y, r7.x + :3:0120:0169[638f081cx_001c801ex] (nop3) mad.f32 r7.x, r7.z, r7.z, r7.x + :0:0121:0173[00000200x_00000000x] (rpt2)nop + :4:0122:0176[8030001cx_0000001cx] rsq r7.x, r7.x + :2:0123:0177[4070101bx_001c001bx] (ss)mul.f r6.w, r6.w, r7.x + :2:0124:0178[4070001ex_001c001ex] mul.f r7.z, r7.z, r7.x + :2:0125:0179[4070001cx_001c001dx] mul.f r7.x, r7.y, r7.x + :1:0126:0180[2024401dx_00000001x] mov.f32f32 r7.y, c0.y + :0:0127:0181[00000200x_00000000x] (rpt2)nop + :2:0128:0184[4078001fx_001d1025x] (nop2) mul.f r7.w, c9.y, r7.y + :4:0129:0187[80100021x_0000001dx] rcp r8.y, r7.y + :2:0130:0188[4010101dx_401d1067x] (ss)add.f r7.y, c25.w, (neg)r7.y + :2:0131:0189[40100020x_401f0008x] add.f r8.x, r2.x, (neg)r7.w + :2:0132:0190[4010001fx_401f1005x] add.f r7.w, c1.y, (neg)r7.w + :2:0133:0191[40700017x_00210017x] mul.f r5.w, r5.w, r8.y + :2:0134:0192[4070001dx_1025001dx] mul.f r7.y, r7.y, c9.y + :2:0135:0193[40700020x_00210020x] mul.f r8.x, r8.x, r8.y + :2:0136:0194[40780016x_00210016x] (nop2) mul.f r5.z, r5.z, r8.y + :2:0137:0197[4070001ax_001a0020x] mul.f r6.z, r8.x, r6.z + :2:0138:0198[40700019x_00200019x] mul.f r6.y, r6.y, r8.x + :2:0139:0199[40700018x_00200018x] mul.f r6.x, r6.x, r8.x + :3:0140:0200[638d801ax_001a0017x] mad.f32 r6.z, r5.w, r6.w, r6.z + :3:0141:0201[638f0019x_80190017x] mad.f32 r6.y, r5.w, r7.z, (neg)r6.y + :3:0142:0202[638e0017x_80180017x] mad.f32 r5.w, r5.w, r7.x, (neg)r6.x + :2:0143:0203[40100008x_401d0008x] add.f r2.x, r2.x, (neg)r7.y + :2:0144:0204[40100010x_4010001ax] add.f r4.x, r6.z, (neg)r4.x + :3:0145:0205[63890012x_4016102dx] mad.f32 r4.z, c11.y, (neg)r4.z, r5.z + :2:0146:0206[4010000dx_400d0017x] add.f r3.y, r5.w, (neg)r3.y + :2:0147:0207[40700017x_00210008x] mul.f r5.w, r2.x, r8.y + :2:0148:0208[40700008x_10210016x] mul.f r2.x, r5.z, c8.y + :2:0149:0209[40700016x_00100010x] mul.f r5.z, r4.x, r4.x + :2:0150:0210[4010000cx_400c0019x] add.f r3.x, r6.y, (neg)r3.x + :3:0151:0211[63868016x_0016000dx] mad.f32 r5.z, r3.y, r3.y, r5.z + :2:0152:0212[40100014x_40080014x] add.f r5.x, r5.x, (neg)r2.x + :3:0153:0213[63890012x_10251024x] mad.f32 r4.z, c9.x, r4.z, c9.y + :3:0154:0214[63860808x_0016800cx] (nop3) mad.f32 r2.x, r3.x, r3.x, r5.z + :0:0155:0218[00000200x_00000000x] (rpt2)nop + :4:0156:0221[80300008x_00000008x] rsq r2.x, r2.x + :2:0157:0222[40701010x_00080010x] (ss)mul.f r4.x, r4.x, r2.x + :2:0158:0223[4070000cx_0008000cx] mul.f r3.x, r3.x, r2.x + :2:0159:0224[40700008x_0008000dx] mul.f r2.x, r3.y, r2.x + :2:0160:0225[4138080dx_00000012x] (nop3) floor.f r3.y, r4.z + :2:0161:0229[4018080dx_400d0012x] (nop3) add.f r3.y, r4.z, (neg)r3.y + :3:0162:0233[6386880dx_10269023x] (nop3) mad.f32 r3.y, c8.w, r3.y, c9.z + :0:0163:0237[00000200x_00000000x] (rpt2)nop + :4:0164:0240[80b00012x_0000000dx] cos r4.z, r3.y + :4:0165:0241[8090100dx_0000000dx] (ss)sin r3.y, r3.y + :2:0166:0242[40700816x_00120010x] (nop1) mul.f r5.z, r4.x, r4.z + :3:0167:0244[63869016x_40160008x] (ss)mad.f32 r5.z, r2.x, (neg)r3.y, r5.z + :2:0168:0245[4070080dx_000d0010x] (nop1) mul.f r3.y, r4.x, r3.y + :3:0169:0247[6389000dx_000d0008x] mad.f32 r3.y, r2.x, r4.z, r3.y + :1:0170:0248[280cc008x_00000006x] (jp)mov.u32u32 r2.x, r1.z + :0:0171:0249[00000200x_00000000x] (rpt2)nop + :2:0172:0252[42bb08f8x_20820008x] (nop3) cmps.s.ge p0.x, r2.x, 130 + :0:0173:0256[00000200x_00000000x] (rpt2)nop + :0:0174:0259[00800000x_00000464x] br p0.x, #1124 + :1:0175:0260[280cc008x_00000003x] (jp)mov.u32u32 r2.x, r0.w + :0:0176:0261[00000200x_00000000x] (rpt2)nop + :2:0177:0264[40b808f8x_0008106ex] (nop3) cmps.f.lt p0.x, c27.z, r2.x + :0:0178:0268[00000200x_00000000x] (rpt2)nop + :0:0179:0271[00800000x_0000045fx] br p0.x, #1119 + :1:0180:0272[280cc012x_00000004x] (jp)mov.u32u32 r4.z, r1.x + :1:0181:0273[200cc018x_00000004x] mov.u32u32 r6.x, r1.x + :1:0182:0274[200cc019x_00000004x] mov.u32u32 r6.y, r1.x + :3:0183:0275[63870010x_1037102ax] mad.f32 r4.x, c10.z, r3.z, c13.w + :3:0184:0276[63868012x_00140012x] mad.f32 r4.z, r4.z, r3.y, r5.x + :3:0185:0277[638b0018x_00150018x] mad.f32 r6.x, r6.x, r5.z, r5.y + :3:0186:0278[63860019x_00110019x] mad.f32 r6.y, r6.y, r3.x, r4.y + :3:0187:0279[63870008x_1037902dx] (nop2) mad.f32 r2.x, c11.y, r3.z, c13.w + :2:0188:0282[4070001cx_10360019x] mul.f r7.x, r6.y, c13.z + :2:0189:0283[4010001ax_10030019x] add.f r6.z, r6.y, c0.w + :2:0190:0284[4070001dx_10340019x] mul.f r7.y, r6.y, c13.x + :2:0191:0285[4070001bx_10380019x] mul.f r6.w, r6.y, c14.x + :3:0192:0286[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :3:0193:0287[638d001ax_10251024x] mad.f32 r6.z, c9.x, r6.z, c9.y + :3:0194:0288[638e881dx_10251024x] (nop1) mad.f32 r7.y, c9.x, r7.y, c9.y + :2:0195:0290[41300020x_0000001cx] floor.f r8.x, r7.x + :2:0196:0291[4130001ex_0000001ax] floor.f r7.z, r6.z + :2:0197:0292[41300822x_0000001dx] (nop1) floor.f r8.z, r7.y + :2:0198:0294[4010001cx_4020001cx] add.f r7.x, r7.x, (neg)r8.x + :2:0199:0295[4010001ax_401e001ax] add.f r6.z, r6.z, (neg)r7.z + :2:0200:0296[4010001dx_4022001dx] add.f r7.y, r7.y, (neg)r8.z + :1:0201:0297[204cc01ex_3f4ccccdx] mov.u32u32 r7.z, 0x3f4ccccd + :3:0202:0298[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :3:0203:0299[638d001ax_10261023x] mad.f32 r6.z, c8.w, r6.z, c9.z + :3:0204:0300[638e801dx_10261023x] mad.f32 r7.y, c8.w, r7.y, c9.z + :2:0205:0301[4070001ex_001e1003x] mul.f r7.z, c0.w, r7.z + :2:0206:0302[40700022x_000f104ax] mul.f r8.z, c18.z, r3.w + :3:0207:0303[638d801bx_001e1039x] mad.f32 r6.w, c14.y, r6.w, r7.z + :2:0208:0304[40700020x_000f104dx] mul.f r8.x, c19.y, r3.w + :4:0209:0305[80b0001cx_0000001cx] cos r7.x, r7.x + :2:0210:0306[4070101cx_1021001cx] (ss)mul.f r7.x, r7.x, c8.y + :4:0211:0307[8090001ax_0000001ax] sin r6.z, r6.z + :0:0212:0308[00000000x_00000000x] nop + :4:0213:0309[8090001dx_0000001dx] sin r7.y, r7.y + :3:0214:0310[638d881bx_10251024x] (nop1) mad.f32 r6.w, c9.x, r6.w, c9.y + :2:0215:0312[4010001cx_401c0018x] add.f r7.x, r6.x, (neg)r7.x + :2:0216:0313[4078101dx_1021001dx] (ss)(nop2) mul.f r7.y, r7.y, c8.y + :2:0217:0316[4070001cx_001c001cx] mul.f r7.x, r7.x, r7.x + :2:0218:0317[4018081dx_401d0012x] (nop3) add.f r7.y, r4.z, (neg)r7.y + :3:0219:0321[638e801cx_001c001dx] mad.f32 r7.x, r7.y, r7.y, r7.x + :1:0220:0322[204cc01dx_3db851ecx] mov.u32u32 r7.y, 0x3db851ec + :0:0221:0323[00000200x_00000000x] (rpt2)nop + :2:0222:0326[4070081dx_001d1003x] (nop1) mul.f r7.y, c0.w, r7.y + :3:0223:0328[6388081ax_001d801ax] (nop3) mad.f32 r6.z, r6.z, r4.x, r7.y + :3:0224:0332[638d081ax_10259024x] (nop3) mad.f32 r6.z, c9.x, r6.z, c9.y + :2:0225:0336[41380823x_0000001ax] (nop3) floor.f r8.w, r6.z + :2:0226:0340[4018081ax_4023001ax] (nop3) add.f r6.z, r6.z, (neg)r8.w + :3:0227:0344[638d081ax_10269023x] (nop3) mad.f32 r6.z, c8.w, r6.z, c9.z + :0:0228:0348[00000200x_00000000x] (rpt2)nop + :4:0229:0351[80900023x_0000001ax] sin r8.w, r6.z + :4:0230:0352[80b0101ax_0000001ax] (ss)cos r6.z, r6.z + :2:0231:0353[40700824x_00230018x] (nop1) mul.f r9.x, r6.x, r8.w + :3:0232:0355[638d1024x_00240012x] (ss)mad.f32 r9.x, r4.z, r6.z, r9.x + :2:0233:0356[4070081ax_001a0018x] (nop1) mul.f r6.z, r6.x, r6.z + :3:0234:0358[6391801ax_401a0012x] mad.f32 r6.z, r4.z, (neg)r8.w, r6.z + :2:0235:0359[40780023x_10380024x] (nop2) mul.f r8.w, r9.x, c14.x + :2:0236:0362[40700025x_1038001ax] mul.f r9.y, r6.z, c14.x + :3:0237:0363[63918023x_001e9039x] (nop2) mad.f32 r8.w, c14.y, r8.w, r7.z + :3:0238:0366[63928025x_001e1039x] mad.f32 r9.y, c14.y, r9.y, r7.z + :3:0239:0367[63918023x_10259024x] (nop2) mad.f32 r8.w, c9.x, r8.w, c9.y + :3:0240:0370[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :2:0241:0371[41380026x_00000023x] (nop2) floor.f r9.z, r8.w + :2:0242:0374[41300027x_00000025x] floor.f r9.w, r9.y + :2:0243:0375[40180023x_40260023x] (nop2) add.f r8.w, r8.w, (neg)r9.z + :2:0244:0378[40100025x_40270025x] add.f r9.y, r9.y, (neg)r9.w + :3:0245:0379[63918023x_10269023x] (nop2) mad.f32 r8.w, c8.w, r8.w, c9.z + :3:0246:0382[63928825x_10269023x] (nop3) mad.f32 r9.y, c8.w, r9.y, c9.z + :0:0247:0386[00000200x_00000000x] (rpt2)nop + :4:0248:0389[80900025x_00000025x] sin r9.y, r9.y + :4:0249:0390[80900023x_00000023x] sin r8.w, r8.w + :2:0250:0391[40701823x_00080023x] (ss)(nop1) mul.f r8.w, r8.w, r2.x + :3:0251:0393[638d001ax_00231038x] mad.f32 r6.z, c14.x, r6.z, r8.w + :2:0252:0394[40780023x_00080025x] (nop2) mul.f r8.w, r9.y, r2.x + :2:0253:0397[40700026x_103b001ax] mul.f r9.z, r6.z, c14.w + :2:0254:0398[40700027x_103f001ax] mul.f r9.w, r6.z, c15.w + :3:0255:0399[638c8023x_00231038x] mad.f32 r8.w, c14.x, r6.y, r8.w + :2:0256:0400[40700025x_1042001ax] mul.f r9.y, r6.z, c16.z + :3:0257:0401[638d081ax_10251024x] (nop1) mad.f32 r6.z, c9.x, r6.z, c9.y + :3:0258:0403[63918828x_10251024x] (nop1) mad.f32 r10.x, c9.x, r8.w, c9.y + :2:0259:0405[41300829x_0000001ax] (nop1) floor.f r10.y, r6.z + :2:0260:0407[4130082ax_00000028x] (nop1) floor.f r10.z, r10.x + :2:0261:0409[4010081ax_4029001ax] (nop1) add.f r6.z, r6.z, (neg)r10.y + :2:0262:0411[40100828x_402a0028x] (nop1) add.f r10.x, r10.x, (neg)r10.z + :3:0263:0413[638d081ax_10261023x] (nop1) mad.f32 r6.z, c8.w, r6.z, c9.z + :3:0264:0415[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0265:0419[00000000x_00000000x] nop + :4:0266:0420[80b00029x_0000001ax] cos r10.y, r6.z + :4:0267:0421[8090101ax_0000001ax] (ss)sin r6.z, r6.z + :0:0268:0422[00000100x_00000000x] (rpt1)nop + :4:0269:0424[8090002ax_00000028x] sin r10.z, r10.x + :4:0270:0425[80b01028x_00000028x] (ss)cos r10.x, r10.x + :2:0271:0426[40700029x_002a0029x] mul.f r10.y, r10.y, r10.z + :2:0272:0427[4138082ax_0000001bx] (nop3) floor.f r10.z, r6.w + :2:0273:0431[4018081bx_402a001bx] (nop3) add.f r6.w, r6.w, (neg)r10.z + :3:0274:0435[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:0275:0439[00000200x_00000000x] (rpt2)nop + :4:0276:0442[8090001bx_0000001bx] sin r6.w, r6.w + :2:0277:0443[4070181bx_0008001bx] (ss)(nop1) mul.f r6.w, r6.w, r2.x + :3:0278:0445[6392081bx_001b9038x] (nop3) mad.f32 r6.w, c14.x, r9.x, r6.w + :3:0279:0449[638d8024x_00251043x] mad.f32 r9.x, c16.w, r6.w, r9.y + :3:0280:0450[638d8025x_0026103cx] mad.f32 r9.y, c15.x, r6.w, r9.z + :3:0281:0451[63918024x_00241044x] mad.f32 r9.x, c17.x, r8.w, r9.x + :3:0282:0452[63918025x_0025103dx] mad.f32 r9.y, c15.y, r8.w, r9.y + :3:0283:0453[638d8026x_00271040x] mad.f32 r9.z, c16.x, r6.w, r9.w + :3:0284:0454[638d801bx_10251024x] mad.f32 r6.w, c9.x, r6.w, c9.y + :3:0285:0455[63918023x_00269041x] (nop2) mad.f32 r8.w, c16.y, r8.w, r9.z + :2:0286:0458[41380826x_0000001bx] (nop3) floor.f r9.z, r6.w + :2:0287:0462[4018081bx_4026001bx] (nop3) add.f r6.w, r6.w, (neg)r9.z + :3:0288:0466[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:0289:0470[00000200x_00000000x] (rpt2)nop + :4:0290:0473[80b00026x_0000001bx] cos r9.z, r6.w + :4:0291:0474[8090101bx_0000001bx] (ss)sin r6.w, r6.w + :3:0292:0475[638d081ax_00290026x] (nop1) mad.f32 r6.z, r9.z, r6.z, r10.y + :3:0293:0477[638d901ax_001a0028x] (ss)mad.f32 r6.z, r10.x, r6.w, r6.z + :2:0294:0478[4070081bx_000f103ex] (nop1) mul.f r6.w, c15.z, r3.w + :3:0295:0480[63920026x_001b103ax] mad.f32 r9.z, c14.z, r9.x, r6.w + :3:0296:0481[63928027x_001b103ax] mad.f32 r9.w, c14.z, r9.y, r6.w + :3:0297:0482[63918828x_001b103ax] (nop1) mad.f32 r10.x, c14.z, r8.w, r6.w + :3:0298:0484[63930026x_10251024x] mad.f32 r9.z, c9.x, r9.z, c9.y + :3:0299:0485[63938027x_10251024x] mad.f32 r9.w, c9.x, r9.w, c9.y + :3:0300:0486[63940828x_10251024x] (nop1) mad.f32 r10.x, c9.x, r10.x, c9.y + :2:0301:0488[41300029x_00000026x] floor.f r10.y, r9.z + :2:0302:0489[4138002ax_00000027x] (nop2) floor.f r10.z, r9.w + :2:0303:0492[40100026x_40290026x] add.f r9.z, r9.z, (neg)r10.y + :2:0304:0493[40180027x_402a0027x] (nop2) add.f r9.w, r9.w, (neg)r10.z + :3:0305:0496[63930026x_10261023x] mad.f32 r9.z, c8.w, r9.z, c9.z + :3:0306:0497[63938827x_10269023x] (nop3) mad.f32 r9.w, c8.w, r9.w, c9.z + :0:0307:0501[00000100x_00000000x] (rpt1)nop + :4:0308:0503[80900026x_00000026x] sin r9.z, r9.z + :3:0309:0504[63841025x_00250026x] (ss)mad.f32 r9.y, r9.z, r2.x, r9.y + :4:0310:0505[80900027x_00000027x] sin r9.w, r9.w + :3:0311:0506[63841023x_00238027x] (ss)(nop2) mad.f32 r8.w, r9.w, r2.x, r8.w + :2:0312:0509[40700026x_10420025x] mul.f r9.z, r9.y, c16.z + :2:0313:0510[40700029x_103f0025x] mul.f r10.y, r9.y, c15.w + :2:0314:0511[40700027x_103b0025x] mul.f r9.w, r9.y, c14.w + :3:0315:0512[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :3:0316:0513[6391802ax_10259024x] (nop2) mad.f32 r10.z, c9.x, r8.w, c9.y + :2:0317:0516[4130002bx_00000025x] floor.f r10.w, r9.y + :2:0318:0517[4138002cx_0000002ax] (nop2) floor.f r11.x, r10.z + :2:0319:0520[40100025x_402b0025x] add.f r9.y, r9.y, (neg)r10.w + :2:0320:0521[4018002ax_402c002ax] (nop2) add.f r10.z, r10.z, (neg)r11.x + :3:0321:0524[63928025x_10261023x] mad.f32 r9.y, c8.w, r9.y, c9.z + :3:0322:0525[6395082ax_10269023x] (nop3) mad.f32 r10.z, c8.w, r10.z, c9.z + :0:0323:0529[00000100x_00000000x] (rpt1)nop + :4:0324:0531[80b0002bx_00000025x] cos r10.w, r9.y + :4:0325:0532[80901025x_00000025x] (ss)sin r9.y, r9.y + :0:0326:0533[00000000x_00000000x] nop + :4:0327:0534[8090002cx_0000002ax] sin r11.x, r10.z + :4:0328:0535[80b0102ax_0000002ax] (ss)cos r10.z, r10.z + :2:0329:0536[4070002bx_002c002bx] mul.f r10.w, r10.w, r11.x + :2:0330:0537[4138082cx_00000028x] (nop3) floor.f r11.x, r10.x + :2:0331:0541[40180828x_402c0028x] (nop3) add.f r10.x, r10.x, (neg)r11.x + :3:0332:0545[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0333:0549[00000200x_00000000x] (rpt2)nop + :4:0334:0552[80900028x_00000028x] sin r10.x, r10.x + :3:0335:0553[63841824x_00248028x] (ss)(nop3) mad.f32 r9.x, r10.x, r2.x, r9.x + :3:0336:0557[63920026x_00261043x] mad.f32 r9.z, c16.w, r9.x, r9.z + :3:0337:0558[63920027x_0027103cx] mad.f32 r9.w, c15.x, r9.x, r9.w + :3:0338:0559[63920028x_00291040x] mad.f32 r10.x, c16.x, r9.x, r10.y + :3:0339:0560[63920024x_10251024x] mad.f32 r9.x, c9.x, r9.x, c9.y + :3:0340:0561[63918026x_00261044x] mad.f32 r9.z, c17.x, r8.w, r9.z + :3:0341:0562[63918027x_0027103dx] mad.f32 r9.w, c15.y, r8.w, r9.w + :3:0342:0563[63918023x_00281041x] mad.f32 r8.w, c16.y, r8.w, r10.x + :2:0343:0564[41380828x_00000024x] (nop3) floor.f r10.x, r9.x + :2:0344:0568[40180824x_40280024x] (nop3) add.f r9.x, r9.x, (neg)r10.x + :3:0345:0572[63920824x_10269023x] (nop3) mad.f32 r9.x, c8.w, r9.x, c9.z + :0:0346:0576[00000200x_00000000x] (rpt2)nop + :4:0347:0579[80b00028x_00000024x] cos r10.x, r9.x + :4:0348:0580[80901024x_00000024x] (ss)sin r9.x, r9.x + :3:0349:0581[63928825x_002b0028x] (nop1) mad.f32 r9.y, r10.x, r9.y, r10.w + :3:0350:0583[63921824x_0025802ax] (ss)(nop3) mad.f32 r9.x, r10.z, r9.x, r9.y + :2:0351:0587[40780824x_10450024x] (nop3) mul.f r9.x, r9.x, c17.y + :2:0352:0591[4010001ax_c024c01ax] add.f r6.z, (absneg)r6.z, (absneg)r9.x + :2:0353:0592[40700824x_000f1047x] (nop1) mul.f r9.x, c17.w, r3.w + :3:0354:0594[63930025x_00241046x] mad.f32 r9.y, c17.z, r9.z, r9.x + :3:0355:0595[63938028x_00241046x] mad.f32 r10.x, c17.z, r9.w, r9.x + :3:0356:0596[63918829x_00241046x] (nop1) mad.f32 r10.y, c17.z, r8.w, r9.x + :3:0357:0598[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :3:0358:0599[63940028x_10251024x] mad.f32 r10.x, c9.x, r10.x, c9.y + :3:0359:0600[63948829x_10251024x] (nop1) mad.f32 r10.y, c9.x, r10.y, c9.y + :2:0360:0602[4130002ax_00000025x] floor.f r10.z, r9.y + :2:0361:0603[4138002bx_00000028x] (nop2) floor.f r10.w, r10.x + :2:0362:0606[40100025x_402a0025x] add.f r9.y, r9.y, (neg)r10.z + :2:0363:0607[40180028x_402b0028x] (nop2) add.f r10.x, r10.x, (neg)r10.w + :3:0364:0610[63928025x_10261023x] mad.f32 r9.y, c8.w, r9.y, c9.z + :3:0365:0611[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0366:0615[00000100x_00000000x] (rpt1)nop + :4:0367:0617[80900025x_00000025x] sin r9.y, r9.y + :3:0368:0618[63841025x_00270025x] (ss)mad.f32 r9.y, r9.y, r2.x, r9.w + :4:0369:0619[80900028x_00000028x] sin r10.x, r10.x + :3:0370:0620[63841023x_00238028x] (ss)(nop2) mad.f32 r8.w, r10.x, r2.x, r8.w + :2:0371:0623[40700027x_10420025x] mul.f r9.w, r9.y, c16.z + :2:0372:0624[4070002ax_103f0025x] mul.f r10.z, r9.y, c15.w + :2:0373:0625[40700028x_103b0025x] mul.f r10.x, r9.y, c14.w + :3:0374:0626[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :3:0375:0627[6391802bx_10259024x] (nop2) mad.f32 r10.w, c9.x, r8.w, c9.y + :2:0376:0630[4130002cx_00000025x] floor.f r11.x, r9.y + :2:0377:0631[4138002dx_0000002bx] (nop2) floor.f r11.y, r10.w + :2:0378:0634[40100025x_402c0025x] add.f r9.y, r9.y, (neg)r11.x + :2:0379:0635[4018002bx_402d002bx] (nop2) add.f r10.w, r10.w, (neg)r11.y + :3:0380:0638[63928025x_10261023x] mad.f32 r9.y, c8.w, r9.y, c9.z + :3:0381:0639[6395882bx_10269023x] (nop3) mad.f32 r10.w, c8.w, r10.w, c9.z + :0:0382:0643[00000100x_00000000x] (rpt1)nop + :4:0383:0645[80b0002cx_00000025x] cos r11.x, r9.y + :4:0384:0646[80901025x_00000025x] (ss)sin r9.y, r9.y + :0:0385:0647[00000000x_00000000x] nop + :4:0386:0648[8090002dx_0000002bx] sin r11.y, r10.w + :4:0387:0649[80b0102bx_0000002bx] (ss)cos r10.w, r10.w + :2:0388:0650[4070002cx_002d002cx] mul.f r11.x, r11.x, r11.y + :2:0389:0651[4138082dx_00000029x] (nop3) floor.f r11.y, r10.y + :2:0390:0655[40180829x_402d0029x] (nop3) add.f r10.y, r10.y, (neg)r11.y + :3:0391:0659[63948829x_10269023x] (nop3) mad.f32 r10.y, c8.w, r10.y, c9.z + :0:0392:0663[00000200x_00000000x] (rpt2)nop + :4:0393:0666[80900029x_00000029x] sin r10.y, r10.y + :3:0394:0667[63841826x_00268029x] (ss)(nop3) mad.f32 r9.z, r10.y, r2.x, r9.z + :3:0395:0671[63930027x_00271043x] mad.f32 r9.w, c16.w, r9.z, r9.w + :3:0396:0672[63930028x_0028103cx] mad.f32 r10.x, c15.x, r9.z, r10.x + :3:0397:0673[63930029x_002a1040x] mad.f32 r10.y, c16.x, r9.z, r10.z + :3:0398:0674[63918027x_00271044x] mad.f32 r9.w, c17.x, r8.w, r9.w + :3:0399:0675[63918028x_0028103dx] mad.f32 r10.x, c15.y, r8.w, r10.x + :3:0400:0676[63918023x_00291041x] mad.f32 r8.w, c16.y, r8.w, r10.y + :3:0401:0677[63930026x_10251024x] mad.f32 r9.z, c9.x, r9.z, c9.y + :3:0402:0678[63938029x_00221049x] mad.f32 r10.y, c18.y, r9.w, r8.z + :3:0403:0679[6394002ax_00221049x] mad.f32 r10.z, c18.y, r10.x, r8.z + :3:0404:0680[6391882dx_00221049x] (nop1) mad.f32 r11.y, c18.y, r8.w, r8.z + :3:0405:0682[63948029x_10251024x] mad.f32 r10.y, c9.x, r10.y, c9.y + :3:0406:0683[6395002ax_10251024x] mad.f32 r10.z, c9.x, r10.z, c9.y + :3:0407:0684[6396882dx_10251024x] (nop1) mad.f32 r11.y, c9.x, r11.y, c9.y + :2:0408:0686[4130002ex_00000029x] floor.f r11.z, r10.y + :2:0409:0687[4138002fx_0000002ax] (nop2) floor.f r11.w, r10.z + :2:0410:0690[40100029x_402e0029x] add.f r10.y, r10.y, (neg)r11.z + :2:0411:0691[4018002ax_402f002ax] (nop2) add.f r10.z, r10.z, (neg)r11.w + :3:0412:0694[63948029x_10261023x] mad.f32 r10.y, c8.w, r10.y, c9.z + :3:0413:0695[6395082ax_10269023x] (nop3) mad.f32 r10.z, c8.w, r10.z, c9.z + :0:0414:0699[00000100x_00000000x] (rpt1)nop + :4:0415:0701[80900029x_00000029x] sin r10.y, r10.y + :3:0416:0702[63841028x_00280029x] (ss)mad.f32 r10.x, r10.y, r2.x, r10.x + :4:0417:0703[8090002ax_0000002ax] sin r10.z, r10.z + :3:0418:0704[63841023x_0023802ax] (ss)(nop2) mad.f32 r8.w, r10.z, r2.x, r8.w + :2:0419:0707[40700029x_10420028x] mul.f r10.y, r10.x, c16.z + :2:0420:0708[4070002ex_103f0028x] mul.f r11.z, r10.x, c15.w + :3:0421:0709[6391802fx_10251024x] mad.f32 r11.w, c9.x, r8.w, c9.y + :2:0422:0710[4070002ax_103b0028x] mul.f r10.z, r10.x, c14.w + :3:0423:0711[63940828x_10251024x] (nop1) mad.f32 r10.x, c9.x, r10.x, c9.y + :2:0424:0713[41300831x_0000002fx] (nop1) floor.f r12.y, r11.w + :2:0425:0715[41300830x_00000028x] (nop1) floor.f r12.x, r10.x + :2:0426:0717[4010082fx_4031002fx] (nop1) add.f r11.w, r11.w, (neg)r12.y + :2:0427:0719[40100828x_40300028x] (nop1) add.f r10.x, r10.x, (neg)r12.x + :3:0428:0721[6397882fx_10261023x] (nop1) mad.f32 r11.w, c8.w, r11.w, c9.z + :3:0429:0723[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0430:0727[00000000x_00000000x] nop + :4:0431:0728[80900031x_0000002fx] sin r12.y, r11.w + :4:0432:0729[80b0102fx_0000002fx] (ss)cos r11.w, r11.w + :0:0433:0730[00000100x_00000000x] (rpt1)nop + :4:0434:0732[80b00030x_00000028x] cos r12.x, r10.x + :4:0435:0733[80901028x_00000028x] (ss)sin r10.x, r10.x + :2:0436:0734[40700030x_00310030x] mul.f r12.x, r12.x, r12.y + :2:0437:0735[41380831x_0000002dx] (nop3) floor.f r12.y, r11.y + :2:0438:0739[4018082dx_4031002dx] (nop3) add.f r11.y, r11.y, (neg)r12.y + :3:0439:0743[6396882dx_10269023x] (nop3) mad.f32 r11.y, c8.w, r11.y, c9.z + :0:0440:0747[00000200x_00000000x] (rpt2)nop + :4:0441:0750[8090002dx_0000002dx] sin r11.y, r11.y + :3:0442:0751[63841827x_0027802dx] (ss)(nop3) mad.f32 r9.w, r11.y, r2.x, r9.w + :3:0443:0755[63938029x_00291043x] mad.f32 r10.y, c16.w, r9.w, r10.y + :3:0444:0756[6393802ax_002a103cx] mad.f32 r10.z, c15.x, r9.w, r10.z + :3:0445:0757[6393802dx_002e1040x] mad.f32 r11.y, c16.x, r9.w, r11.z + :3:0446:0758[63918029x_00291044x] mad.f32 r10.y, c17.x, r8.w, r10.y + :3:0447:0759[6391802ax_002a103dx] mad.f32 r10.z, c15.y, r8.w, r10.z + :3:0448:0760[63918023x_002d1041x] mad.f32 r8.w, c16.y, r8.w, r11.y + :3:0449:0761[63938027x_10251024x] mad.f32 r9.w, c9.x, r9.w, c9.y + :3:0450:0762[6394802dx_0020104cx] mad.f32 r11.y, c19.x, r10.y, r8.x + :3:0451:0763[6395002ex_0020104cx] mad.f32 r11.z, c19.x, r10.z, r8.x + :3:0452:0764[63918831x_0020104cx] (nop1) mad.f32 r12.y, c19.x, r8.w, r8.x + :3:0453:0766[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :3:0454:0767[6397002ex_10251024x] mad.f32 r11.z, c9.x, r11.z, c9.y + :3:0455:0768[63988831x_10251024x] (nop1) mad.f32 r12.y, c9.x, r12.y, c9.y + :2:0456:0770[41300032x_0000002dx] floor.f r12.z, r11.y + :2:0457:0771[41380033x_0000002ex] (nop2) floor.f r12.w, r11.z + :2:0458:0774[4010002dx_4032002dx] add.f r11.y, r11.y, (neg)r12.z + :2:0459:0775[4018002ex_4033002ex] (nop2) add.f r11.z, r11.z, (neg)r12.w + :3:0460:0778[6396802dx_10261023x] mad.f32 r11.y, c8.w, r11.y, c9.z + :3:0461:0779[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:0462:0783[00000100x_00000000x] (rpt1)nop + :4:0463:0785[8090002dx_0000002dx] sin r11.y, r11.y + :3:0464:0786[6384102ax_002a002dx] (ss)mad.f32 r10.z, r11.y, r2.x, r10.z + :4:0465:0787[8090002ex_0000002ex] sin r11.z, r11.z + :3:0466:0788[63841023x_0023802ex] (ss)(nop2) mad.f32 r8.w, r11.z, r2.x, r8.w + :3:0467:0791[6395002ax_10251024x] mad.f32 r10.z, c9.x, r10.z, c9.y + :3:0468:0792[63918023x_10259024x] (nop2) mad.f32 r8.w, c9.x, r8.w, c9.y + :2:0469:0795[4130002dx_0000002ax] floor.f r11.y, r10.z + :2:0470:0796[4138002ex_00000023x] (nop2) floor.f r11.z, r8.w + :2:0471:0799[4010002ax_402d002ax] add.f r10.z, r10.z, (neg)r11.y + :2:0472:0800[40180023x_402e0023x] (nop2) add.f r8.w, r8.w, (neg)r11.z + :3:0473:0803[6395002ax_10261023x] mad.f32 r10.z, c8.w, r10.z, c9.z + :3:0474:0804[63918823x_10269023x] (nop3) mad.f32 r8.w, c8.w, r8.w, c9.z + :0:0475:0808[00000100x_00000000x] (rpt1)nop + :4:0476:0810[80b0002dx_0000002ax] cos r11.y, r10.z + :4:0477:0811[8090102ax_0000002ax] (ss)sin r10.z, r10.z + :0:0478:0812[00000000x_00000000x] nop + :4:0479:0813[8090002ex_00000023x] sin r11.z, r8.w + :4:0480:0814[80b01023x_00000023x] (ss)cos r8.w, r8.w + :2:0481:0815[4070002dx_002e002dx] mul.f r11.y, r11.y, r11.z + :2:0482:0816[4138082ex_00000031x] (nop3) floor.f r11.z, r12.y + :2:0483:0820[4018082ex_402e0031x] (nop3) add.f r11.z, r12.y, (neg)r11.z + :3:0484:0824[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:0485:0828[00000200x_00000000x] (rpt2)nop + :4:0486:0831[8090002ex_0000002ex] sin r11.z, r11.z + :3:0487:0832[63841829x_0029802ex] (ss)(nop3) mad.f32 r10.y, r11.z, r2.x, r10.y + :3:0488:0836[63948829x_10259024x] (nop3) mad.f32 r10.y, c9.x, r10.y, c9.y + :2:0489:0840[4138082ex_00000029x] (nop3) floor.f r11.z, r10.y + :2:0490:0844[40180829x_402e0029x] (nop3) add.f r10.y, r10.y, (neg)r11.z + :3:0491:0848[63948829x_10269023x] (nop3) mad.f32 r10.y, c8.w, r10.y, c9.z + :0:0492:0852[00000200x_00000000x] (rpt2)nop + :4:0493:0855[80b0002ex_00000029x] cos r11.z, r10.y + :4:0494:0856[80901029x_00000029x] (ss)sin r10.y, r10.y + :3:0495:0857[6395082ax_002d002ex] (nop1) mad.f32 r10.z, r11.z, r10.z, r11.y + :3:0496:0859[63949023x_002a0023x] (ss)mad.f32 r8.w, r8.w, r10.y, r10.z + :2:0497:0860[41380829x_00000027x] (nop3) floor.f r10.y, r9.w + :2:0498:0864[40100027x_40290027x] add.f r9.w, r9.w, (neg)r10.y + :2:0499:0865[40780023x_104e0023x] (nop2) mul.f r8.w, r8.w, c19.z + :3:0500:0868[63938827x_10269023x] (nop3) mad.f32 r9.w, c8.w, r9.w, c9.z + :0:0501:0872[00000200x_00000000x] (rpt2)nop + :4:0502:0875[80b00029x_00000027x] cos r10.y, r9.w + :4:0503:0876[80901027x_00000027x] (ss)sin r9.w, r9.w + :3:0504:0877[63940828x_00300029x] (nop1) mad.f32 r10.x, r10.y, r10.x, r12.x + :3:0505:0879[63939027x_0028002fx] (ss)mad.f32 r9.w, r11.w, r9.w, r10.x + :2:0506:0880[41380828x_00000026x] (nop3) floor.f r10.x, r9.z + :2:0507:0884[40100026x_40280026x] add.f r9.z, r9.z, (neg)r10.x + :2:0508:0885[40780027x_104b0027x] (nop2) mul.f r9.w, r9.w, c18.w + :3:0509:0888[63930826x_10269023x] (nop3) mad.f32 r9.z, c8.w, r9.z, c9.z + :0:0510:0892[00000200x_00000000x] (rpt2)nop + :4:0511:0895[80b00028x_00000026x] cos r10.x, r9.z + :4:0512:0896[80901026x_00000026x] (ss)sin r9.z, r9.z + :3:0513:0897[63928825x_002c0028x] (nop1) mad.f32 r9.y, r10.x, r9.y, r11.x + :3:0514:0899[63931825x_0025802bx] (ss)(nop3) mad.f32 r9.y, r10.w, r9.z, r9.y + :2:0515:0903[40780825x_10480025x] (nop3) mul.f r9.y, r9.y, c18.x + :2:0516:0907[4018081ax_c025001ax] (nop3) add.f r6.z, r6.z, (absneg)r9.y + :2:0517:0911[4018081ax_c027001ax] (nop3) add.f r6.z, r6.z, (absneg)r9.w + :2:0518:0915[4010081ax_c023001ax] (nop1) add.f r6.z, r6.z, (absneg)r8.w + :3:0519:0917[6387081ax_001a9029x] (nop3) mad.f32 r6.z, c10.y, r3.z, r6.z + :2:0520:0921[4010081ax_104f801ax] (nop1) add.f r6.z, (abs)r6.z, c19.w + :3:0521:0923[6387081ax_001a1050x] (nop1) mad.f32 r6.z, c20.x, r3.z, r6.z + :3:0522:0925[6390881ax_001a001fx] (nop1) mad.f32 r6.z, r7.w, r8.y, r6.z + :3:0523:0927[638e081ax_001a902dx] (nop3) mad.f32 r6.z, c11.y, r7.x, r6.z + :2:0524:0931[40100025x_1056001ax] add.f r9.y, r6.z, c21.z + :2:0525:0932[40180023x_001a106fx] (nop2) add.f r8.w, c27.w, r6.z + :2:0526:0935[40b000f8x_0025106cx] cmps.f.lt p0.x, c27.x, r9.y + :2:0527:0936[40100425x_001a1030x] (sat)add.f r9.y, c12.x, r6.z + :2:0528:0937[40580023x_10700023x] (nop2) max.f r8.w, r8.w, c28.x + :2:0529:0940[40700026x_103e0025x] mul.f r9.z, r9.y, c15.z + :2:0530:0941[40300023x_10290023x] min.f r8.w, r8.w, c10.y + :0:0531:0942[00900000x_000002cdx] br !p0.x, #717 + :2:0532:0943[48100028x_10550019x] (jp)add.f r10.x, r6.y, c21.y + :2:0533:0944[40700029x_10270019x] mul.f r10.y, r6.y, c9.w + :2:0534:0945[40100019x_10590019x] add.f r6.y, r6.y, c22.y + :2:0535:0946[40700027x_00260026x] mul.f r9.w, r9.z, r9.z + :2:0536:0947[4010002ax_10590018x] add.f r10.z, r6.x, c22.y + :3:0537:0948[63948029x_10251024x] mad.f32 r10.y, c9.x, r10.y, c9.y + :2:0538:0949[4010002cx_10030019x] add.f r11.x, r6.y, c0.w + :2:0539:0950[4010002bx_10030028x] add.f r10.w, r10.x, c0.w + :2:0540:0951[40700027x_00260027x] mul.f r9.w, r9.w, r9.z + :2:0541:0952[4130002ex_00000029x] floor.f r11.z, r10.y + :3:0542:0953[6396002cx_10251024x] mad.f32 r11.x, c9.x, r11.x, c9.y + :2:0543:0954[40100018x_10550018x] add.f r6.x, r6.x, c21.y + :3:0544:0955[6395802bx_10251024x] mad.f32 r10.w, c9.x, r10.w, c9.y + :2:0545:0956[40100029x_402e0029x] add.f r10.y, r10.y, (neg)r11.z + :2:0546:0957[4130002ex_0000002cx] floor.f r11.z, r11.x + :2:0547:0958[40700007x_0027102fx] mul.f r1.w, c11.w, r9.w + :2:0548:0959[4130002fx_0000002bx] floor.f r11.w, r10.w + :3:0549:0960[63948029x_10261023x] mad.f32 r10.y, c8.w, r10.y, c9.z + :2:0550:0961[4010002cx_402e002cx] add.f r11.x, r11.x, (neg)r11.z + :2:0551:0962[4010001ax_001a1051x] add.f r6.z, c20.y, r6.z + :2:0552:0963[4010002bx_402f002bx] add.f r10.w, r10.w, (neg)r11.w + :2:0553:0964[4070002dx_10380019x] mul.f r11.y, r6.y, c14.x + :3:0554:0965[6396002cx_10261023x] mad.f32 r11.x, c8.w, r11.x, c9.z + :2:0555:0966[4070041ax_1052001ax] (sat)mul.f r6.z, r6.z, c20.z + :4:0556:0967[80900029x_00000029x] sin r10.y, r10.y + :3:0557:0968[6395802bx_10261023x] mad.f32 r10.w, c8.w, r10.w, c9.z + :3:0558:0969[6396802dx_001e1039x] mad.f32 r11.y, c14.y, r11.y, r7.z + :3:0559:0970[6394902ex_10211025x] (ss)mad.f32 r11.z, c9.y, r10.y, c8.y + :2:0560:0971[4070001ax_1053001ax] mul.f r6.z, r6.z, c20.w + :3:0561:0972[63948031x_105b1025x] mad.f32 r12.y, c9.y, r10.y, c22.w + :4:0562:0973[8090002cx_0000002cx] sin r11.x, r11.x + :3:0563:0974[638e002ex_002e1037x] mad.f32 r11.z, c13.w, r7.x, r11.z + :3:0564:0975[638e0031x_00311037x] mad.f32 r12.y, c13.w, r7.x, r12.y + :4:0565:0976[8090002bx_0000002bx] sin r10.w, r10.w + :3:0566:0977[63948029x_105e1025x] mad.f32 r10.y, c9.y, r10.y, c23.z + :3:0567:0978[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :3:0568:0979[638e001cx_00291037x] mad.f32 r7.x, c13.w, r7.x, r10.y + :3:0569:0980[63988029x_10251024x] mad.f32 r10.y, c9.x, r12.y, c9.y + :3:0570:0981[6388102bx_001d002bx] (ss)mad.f32 r10.w, r10.w, r4.x, r7.y + :3:0571:0982[63880010x_001d002cx] mad.f32 r4.x, r11.x, r4.x, r7.y + :3:0572:0983[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :2:0573:0984[41300031x_00000029x] floor.f r12.y, r10.y + :3:0574:0985[6395802bx_10251024x] mad.f32 r10.w, c9.x, r10.w, c9.y + :3:0575:0986[6397001dx_10251024x] mad.f32 r7.y, c9.x, r11.z, c9.y + :2:0576:0987[41300032x_0000001cx] floor.f r12.z, r7.x + :2:0577:0988[40100029x_40310029x] add.f r10.y, r10.y, (neg)r12.y + :2:0578:0989[40100031x_10550012x] add.f r12.y, r4.z, c21.y + :2:0579:0990[4130002cx_0000001dx] floor.f r11.x, r7.y + :2:0580:0991[4010001cx_4032001cx] add.f r7.x, r7.x, (neg)r12.z + :3:0581:0992[63948029x_10261023x] mad.f32 r10.y, c8.w, r10.y, c9.z + :3:0582:0993[63880010x_10251024x] mad.f32 r4.x, c9.x, r4.x, c9.y + :2:0583:0994[4010001dx_402c001dx] add.f r7.y, r7.y, (neg)r11.x + :3:0584:0995[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :2:0585:0996[4130002cx_0000002bx] floor.f r11.x, r10.w + :2:0586:0997[40100012x_10590012x] add.f r4.z, r4.z, c22.y + :3:0587:0998[638e801dx_10261023x] mad.f32 r7.y, c8.w, r7.y, c9.z + :4:0588:0999[80900029x_00000029x] sin r10.y, r10.y + :2:0589:1000[4130002ex_00000010x] floor.f r11.z, r4.x + :2:0590:1001[4010002bx_402c002bx] add.f r10.w, r10.w, (neg)r11.x + :3:0591:1002[63949029x_10251025x] (ss)mad.f32 r10.y, c9.y, r10.y, c9.y + :4:0592:1003[8090001cx_0000001cx] sin r7.x, r7.x + :3:0593:1004[638e101cx_10251025x] (ss)mad.f32 r7.x, c9.y, r7.x, c9.y + :2:0594:1005[40100010x_402e0010x] add.f r4.x, r4.x, (neg)r11.z + :3:0595:1006[6395802bx_10261023x] mad.f32 r10.w, c8.w, r10.w, c9.z + :4:0596:1007[8090001dx_0000001dx] sin r7.y, r7.y + :2:0597:1008[40700029x_00270029x] mul.f r10.y, r10.y, r9.w + :2:0598:1009[4070001cx_0027001cx] mul.f r7.x, r7.x, r9.w + :3:0599:1010[63880010x_10261023x] mad.f32 r4.x, c8.w, r4.x, c9.z + :3:0600:1011[638e901dx_10251025x] (ss)mad.f32 r7.y, c9.y, r7.y, c9.y + :2:0601:1012[40700829x_001a0029x] (nop1) mul.f r10.y, r10.y, r6.z + :4:0602:1014[8090002cx_0000002bx] sin r11.x, r10.w + :4:0603:1015[80b0102bx_0000002bx] (ss)cos r10.w, r10.w + :0:0604:1016[00000000x_00000000x] nop + :2:0605:1017[4070001dx_0027001dx] mul.f r7.y, r7.y, r9.w + :2:0606:1018[40700027x_002c0018x] mul.f r9.w, r6.x, r11.x + :4:0607:1019[8090002ex_00000010x] sin r11.z, r4.x + :4:0608:1020[80b01010x_00000010x] (ss)cos r4.x, r4.x + :0:0609:1021[00000000x_00000000x] nop + :3:0610:1022[63958027x_00270031x] mad.f32 r9.w, r12.y, r10.w, r9.w + :2:0611:1023[4070001dx_001a001dx] mul.f r7.y, r7.y, r6.z + :2:0612:1024[4070001ax_001a001cx] mul.f r6.z, r7.x, r6.z + :2:0613:1025[4130001cx_0000002dx] floor.f r7.x, r11.y + :2:0614:1026[4070002fx_002e002ax] mul.f r11.w, r10.z, r11.z + :2:0615:1027[40701030x_0010002ax] (ss)mul.f r12.x, r10.z, r4.x + :3:0616:1028[63880010x_002f0012x] mad.f32 r4.x, r4.z, r4.x, r11.w + :2:0617:1029[4010001cx_401c002dx] add.f r7.x, r11.y, (neg)r7.x + :2:0618:1030[4070002dx_002b0018x] mul.f r11.y, r6.x, r10.w + :3:0619:1031[6397002ex_40300012x] mad.f32 r11.z, r4.z, (neg)r11.z, r12.x + :3:0620:1032[6396002bx_402d0031x] mad.f32 r10.w, r12.y, (neg)r11.x, r11.y + :2:0621:1033[4070002cx_10380027x] mul.f r11.x, r9.w, c14.x + :3:0622:1034[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :2:0623:1035[40700030x_1038002ex] mul.f r12.x, r11.z, c14.x + :2:0624:1036[4070002dx_1038002bx] mul.f r11.y, r10.w, c14.x + :3:0625:1037[6396002cx_001e9039x] (nop2) mad.f32 r11.x, c14.y, r11.x, r7.z + :3:0626:1040[6396802dx_001e1039x] mad.f32 r11.y, c14.y, r11.y, r7.z + :4:0627:1041[8090001cx_0000001cx] sin r7.x, r7.x + :3:0628:1042[6396002cx_10251024x] mad.f32 r11.x, c9.x, r11.x, c9.y + :2:0629:1043[4070181cx_0008001cx] (ss)(nop1) mul.f r7.x, r7.x, r2.x + :3:0630:1045[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :2:0631:1046[41300032x_0000002cx] floor.f r12.z, r11.x + :3:0632:1047[6388001cx_001c1038x] mad.f32 r7.x, c14.x, r4.x, r7.x + :2:0633:1048[40700010x_10380010x] mul.f r4.x, r4.x, c14.x + :2:0634:1049[41300033x_0000002dx] floor.f r12.w, r11.y + :2:0635:1050[4018002cx_4032002cx] (nop2) add.f r11.x, r11.x, (neg)r12.z + :2:0636:1053[4010002dx_4033002dx] add.f r11.y, r11.y, (neg)r12.w + :3:0637:1054[6396002cx_10261023x] mad.f32 r11.x, c8.w, r11.x, c9.z + :3:0638:1055[63880810x_001e1039x] (nop1) mad.f32 r4.x, c14.y, r4.x, r7.z + :3:0639:1057[6396882dx_10269023x] (nop3) mad.f32 r11.y, c8.w, r11.y, c9.z + :4:0640:1061[8090002cx_0000002cx] sin r11.x, r11.x + :3:0641:1062[63880010x_10251024x] mad.f32 r4.x, c9.x, r4.x, c9.y + :2:0642:1063[4070182cx_0008002cx] (ss)(nop1) mul.f r11.x, r11.x, r2.x + :4:0643:1065[8090002dx_0000002dx] sin r11.y, r11.y + :3:0644:1066[6395802bx_002c1038x] mad.f32 r10.w, c14.x, r10.w, r11.x + :2:0645:1067[41300037x_00000010x] floor.f r13.w, r4.x + :2:0646:1068[4070182cx_0008002dx] (ss)(nop1) mul.f r11.x, r11.y, r2.x + :3:0647:1070[6394002cx_002c1038x] mad.f32 r11.x, c14.x, r10.x, r11.x + :2:0648:1071[40700032x_103b002bx] mul.f r12.z, r10.w, c14.w + :2:0649:1072[40700033x_103f002bx] mul.f r12.w, r10.w, c15.w + :2:0650:1073[4070002dx_1042002bx] mul.f r11.y, r10.w, c16.z + :3:0651:1074[63960034x_10251024x] mad.f32 r13.x, c9.x, r11.x, c9.y + :3:0652:1075[6395802bx_10251024x] mad.f32 r10.w, c9.x, r10.w, c9.y + :2:0653:1076[40100810x_40370010x] (nop1) add.f r4.x, r4.x, (neg)r13.w + :2:0654:1078[41300036x_00000034x] floor.f r13.z, r13.x + :2:0655:1079[41300035x_0000002bx] floor.f r13.y, r10.w + :3:0656:1080[63880810x_10261023x] (nop1) mad.f32 r4.x, c8.w, r4.x, c9.z + :2:0657:1082[40100034x_40360034x] add.f r13.x, r13.x, (neg)r13.z + :2:0658:1083[4018002bx_4035002bx] (nop2) add.f r10.w, r10.w, (neg)r13.y + :3:0659:1086[639a0034x_10261023x] mad.f32 r13.x, c8.w, r13.x, c9.z + :4:0660:1087[80900010x_00000010x] sin r4.x, r4.x + :3:0661:1088[6395802bx_10261023x] mad.f32 r10.w, c8.w, r10.w, c9.z + :2:0662:1089[40781810x_00080010x] (ss)(nop3) mul.f r4.x, r4.x, r2.x + :0:0663:1093[00000000x_00000000x] nop + :4:0664:1094[80900036x_00000034x] sin r13.z, r13.x + :4:0665:1095[80b01034x_00000034x] (ss)cos r13.x, r13.x + :0:0666:1096[00000000x_00000000x] nop + :4:0667:1097[80b00035x_0000002bx] cos r13.y, r10.w + :4:0668:1098[8090102bx_0000002bx] (ss)sin r10.w, r10.w + :3:0669:1099[63970010x_00101038x] mad.f32 r4.x, c14.x, r11.z, r4.x + :2:0670:1100[40700035x_00360035x] mul.f r13.y, r13.y, r13.z + :2:0671:1101[40780836x_10380028x] (nop3) mul.f r13.z, r10.x, c14.x + :3:0672:1105[639b0036x_001e1039x] mad.f32 r13.z, c14.y, r13.z, r7.z + :3:0673:1106[6398001ex_001e1039x] mad.f32 r7.z, c14.y, r12.x, r7.z + :2:0674:1107[40700037x_103b0010x] mul.f r13.w, r4.x, c14.w + :2:0675:1108[4070002ex_10420010x] mul.f r11.z, r4.x, c16.z + :3:0676:1109[638e0037x_0037103cx] mad.f32 r13.w, c15.x, r7.x, r13.w + :3:0677:1110[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :2:0678:1111[40700038x_103f0010x] mul.f r14.x, r4.x, c15.w + :3:0679:1112[638e0030x_10251024x] mad.f32 r12.x, c9.x, r7.x, c9.y + :3:0680:1113[638e002ex_002e1043x] mad.f32 r11.z, c16.w, r7.x, r11.z + :2:0681:1114[41300039x_0000001ex] floor.f r14.y, r7.z + :3:0682:1115[638e001cx_00381040x] mad.f32 r7.x, c16.x, r7.x, r14.x + :3:0683:1116[639b002fx_10251024x] mad.f32 r11.w, c9.x, r13.z, c9.y + :2:0684:1117[41300036x_00000030x] floor.f r13.z, r12.x + :2:0685:1118[4010001ex_4039001ex] add.f r7.z, r7.z, (neg)r14.y + :3:0686:1119[63880010x_10259024x] (nop2) mad.f32 r4.x, c9.x, r4.x, c9.y + :3:0687:1122[638f001ex_10261023x] mad.f32 r7.z, c8.w, r7.z, c9.z + :2:0688:1123[40100030x_40360030x] add.f r12.x, r12.x, (neg)r13.z + :2:0689:1124[41380838x_00000010x] (nop3) floor.f r14.x, r4.x + :0:0690:1128[00000000x_00000000x] nop + :4:0691:1129[8090001ex_0000001ex] sin r7.z, r7.z + :3:0692:1130[63980030x_10261023x] mad.f32 r12.x, c8.w, r12.x, c9.z + :2:0693:1131[40100010x_40380010x] add.f r4.x, r4.x, (neg)r14.x + :2:0694:1132[4070181ex_0008001ex] (ss)(nop1) mul.f r7.z, r7.z, r2.x + :3:0695:1134[638c801ex_001e1038x] mad.f32 r7.z, c14.x, r6.y, r7.z + :3:0696:1135[63880010x_10269023x] (nop2) mad.f32 r4.x, c8.w, r4.x, c9.z + :3:0697:1138[638f0037x_0037103dx] mad.f32 r13.w, c15.y, r7.z, r13.w + :4:0698:1139[80b00036x_00000030x] cos r13.z, r12.x + :4:0699:1140[80901030x_00000030x] (ss)sin r12.x, r12.x + :3:0700:1141[638f002ex_002e1044x] mad.f32 r11.z, c17.x, r7.z, r11.z + :3:0701:1142[638f081cx_001c1041x] (nop1) mad.f32 r7.x, c16.y, r7.z, r7.x + :4:0702:1144[80b00038x_00000010x] cos r14.x, r4.x + :4:0703:1145[80901010x_00000010x] (ss)sin r4.x, r4.x + :3:0704:1146[639b803ax_001b103ax] mad.f32 r14.z, c14.z, r13.w, r6.w + :3:0705:1147[63970039x_001b103ax] mad.f32 r14.y, c14.z, r11.z, r6.w + :3:0706:1148[638e003bx_001b103ax] mad.f32 r14.w, c14.z, r7.x, r6.w + :3:0707:1149[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :3:0708:1150[639d003ax_10251024x] mad.f32 r14.z, c9.x, r14.z, c9.y + :3:0709:1151[639c8039x_10251024x] mad.f32 r14.y, c9.x, r14.y, c9.y + :3:0710:1152[639d883bx_10251024x] (nop1) mad.f32 r14.w, c9.x, r14.w, c9.y + :2:0711:1154[4130003dx_0000003ax] floor.f r15.y, r14.z + :2:0712:1155[4138003cx_00000039x] (nop2) floor.f r15.x, r14.y + :2:0713:1158[4010003ax_403d003ax] add.f r14.z, r14.z, (neg)r15.y + :2:0714:1159[40180039x_403c0039x] (nop2) add.f r14.y, r14.y, (neg)r15.x + :3:0715:1162[639d003ax_10261023x] mad.f32 r14.z, c8.w, r14.z, c9.z + :3:0716:1163[639c8839x_10269023x] (nop3) mad.f32 r14.y, c8.w, r14.y, c9.z + :0:0717:1167[00000100x_00000000x] (rpt1)nop + :4:0718:1169[8090003ax_0000003ax] sin r14.z, r14.z + :3:0719:1170[6384101cx_001c003ax] (ss)mad.f32 r7.x, r14.z, r2.x, r7.x + :4:0720:1171[80900039x_00000039x] sin r14.y, r14.y + :3:0721:1172[63841037x_00378039x] (ss)(nop2) mad.f32 r13.w, r14.y, r2.x, r13.w + :3:0722:1175[638e003dx_10251024x] mad.f32 r15.y, c9.x, r7.x, c9.y + :2:0723:1176[40700039x_10420037x] mul.f r14.y, r13.w, c16.z + :2:0724:1177[4070003ax_103b0037x] mul.f r14.z, r13.w, c14.w + :2:0725:1178[4070003cx_103f0037x] mul.f r15.x, r13.w, c15.w + :2:0726:1179[4130003fx_0000003dx] floor.f r15.w, r15.y + :3:0727:1180[639b8037x_10259024x] (nop2) mad.f32 r13.w, c9.x, r13.w, c9.y + :2:0728:1183[4010003dx_403f003dx] add.f r15.y, r15.y, (neg)r15.w + :2:0729:1184[4138003ex_00000037x] (nop2) floor.f r15.z, r13.w + :3:0730:1187[639e803dx_10261023x] mad.f32 r15.y, c8.w, r15.y, c9.z + :2:0731:1188[40180837x_403e0037x] (nop3) add.f r13.w, r13.w, (neg)r15.z + :0:0732:1192[00000100x_00000000x] (rpt1)nop + :4:0733:1194[8090003fx_0000003dx] sin r15.w, r15.y + :4:0734:1195[80b0103dx_0000003dx] (ss)cos r15.y, r15.y + :3:0735:1196[639b8837x_10269023x] (nop3) mad.f32 r13.w, c8.w, r13.w, c9.z + :0:0736:1200[00000200x_00000000x] (rpt2)nop + :4:0737:1203[80b0003ex_00000037x] cos r15.z, r13.w + :4:0738:1204[80901037x_00000037x] (ss)sin r13.w, r13.w + :2:0739:1205[4070003ex_003f003ex] mul.f r15.z, r15.z, r15.w + :2:0740:1206[4138083fx_0000003bx] (nop3) floor.f r15.w, r14.w + :2:0741:1210[4018083bx_403f003bx] (nop3) add.f r14.w, r14.w, (neg)r15.w + :3:0742:1214[639d883bx_10269023x] (nop3) mad.f32 r14.w, c8.w, r14.w, c9.z + :0:0743:1218[00000200x_00000000x] (rpt2)nop + :4:0744:1221[8090003bx_0000003bx] sin r14.w, r14.w + :3:0745:1222[6384182ex_002e803bx] (ss)(nop3) mad.f32 r11.z, r14.w, r2.x, r11.z + :3:0746:1226[63970039x_00391043x] mad.f32 r14.y, c16.w, r11.z, r14.y + :3:0747:1227[6397003ax_003a103cx] mad.f32 r14.z, c15.x, r11.z, r14.z + :3:0748:1228[6397003bx_003c1040x] mad.f32 r14.w, c16.x, r11.z, r15.x + :3:0749:1229[638e0039x_00391044x] mad.f32 r14.y, c17.x, r7.x, r14.y + :3:0750:1230[638e003ax_003a103dx] mad.f32 r14.z, c15.y, r7.x, r14.z + :3:0751:1231[638e001cx_003b1041x] mad.f32 r7.x, c16.y, r7.x, r14.w + :3:0752:1232[6397002ex_10251024x] mad.f32 r11.z, c9.x, r11.z, c9.y + :3:0753:1233[639c803bx_00241046x] mad.f32 r14.w, c17.z, r14.y, r9.x + :3:0754:1234[639d003cx_00241046x] mad.f32 r15.x, c17.z, r14.z, r9.x + :3:0755:1235[638e083fx_00241046x] (nop1) mad.f32 r15.w, c17.z, r7.x, r9.x + :3:0756:1237[639d803bx_10251024x] mad.f32 r14.w, c9.x, r14.w, c9.y + :3:0757:1238[639e003cx_10251024x] mad.f32 r15.x, c9.x, r15.x, c9.y + :3:0758:1239[639f883fx_10251024x] (nop1) mad.f32 r15.w, c9.x, r15.w, c9.y + :2:0759:1241[41300040x_0000003bx] floor.f r16.x, r14.w + :2:0760:1242[41380041x_0000003cx] (nop2) floor.f r16.y, r15.x + :2:0761:1245[4010003bx_4040003bx] add.f r14.w, r14.w, (neg)r16.x + :2:0762:1246[4018003cx_4041003cx] (nop2) add.f r15.x, r15.x, (neg)r16.y + :3:0763:1249[639d803bx_10261023x] mad.f32 r14.w, c8.w, r14.w, c9.z + :3:0764:1250[639e083cx_10269023x] (nop3) mad.f32 r15.x, c8.w, r15.x, c9.z + :0:0765:1254[00000100x_00000000x] (rpt1)nop + :4:0766:1256[8090003bx_0000003bx] sin r14.w, r14.w + :3:0767:1257[6384103ax_003a003bx] (ss)mad.f32 r14.z, r14.w, r2.x, r14.z + :4:0768:1258[8090003cx_0000003cx] sin r15.x, r15.x + :3:0769:1259[6384101cx_001c803cx] (ss)(nop2) mad.f32 r7.x, r15.x, r2.x, r7.x + :2:0770:1262[4070003bx_1042003ax] mul.f r14.w, r14.z, c16.z + :2:0771:1263[40700040x_103f003ax] mul.f r16.x, r14.z, c15.w + :2:0772:1264[4070003cx_103b003ax] mul.f r15.x, r14.z, c14.w + :3:0773:1265[639d003ax_10251024x] mad.f32 r14.z, c9.x, r14.z, c9.y + :3:0774:1266[638e0041x_10259024x] (nop2) mad.f32 r16.y, c9.x, r7.x, c9.y + :2:0775:1269[41300042x_0000003ax] floor.f r16.z, r14.z + :2:0776:1270[41380043x_00000041x] (nop2) floor.f r16.w, r16.y + :2:0777:1273[4010003ax_4042003ax] add.f r14.z, r14.z, (neg)r16.z + :2:0778:1274[40180041x_40430041x] (nop2) add.f r16.y, r16.y, (neg)r16.w + :3:0779:1277[639d003ax_10261023x] mad.f32 r14.z, c8.w, r14.z, c9.z + :3:0780:1278[63a08841x_10269023x] (nop3) mad.f32 r16.y, c8.w, r16.y, c9.z + :0:0781:1282[00000100x_00000000x] (rpt1)nop + :4:0782:1284[80b00042x_0000003ax] cos r16.z, r14.z + :4:0783:1285[8090103ax_0000003ax] (ss)sin r14.z, r14.z + :0:0784:1286[00000000x_00000000x] nop + :4:0785:1287[80900043x_00000041x] sin r16.w, r16.y + :4:0786:1288[80b01041x_00000041x] (ss)cos r16.y, r16.y + :2:0787:1289[40700042x_00430042x] mul.f r16.z, r16.z, r16.w + :2:0788:1290[41380843x_0000003fx] (nop3) floor.f r16.w, r15.w + :2:0789:1294[4018083fx_4043003fx] (nop3) add.f r15.w, r15.w, (neg)r16.w + :3:0790:1298[639f883fx_10269023x] (nop3) mad.f32 r15.w, c8.w, r15.w, c9.z + :0:0791:1302[00000200x_00000000x] (rpt2)nop + :4:0792:1305[8090003fx_0000003fx] sin r15.w, r15.w + :3:0793:1306[63841839x_0039803fx] (ss)(nop3) mad.f32 r14.y, r15.w, r2.x, r14.y + :3:0794:1310[639c803bx_003b1043x] mad.f32 r14.w, c16.w, r14.y, r14.w + :3:0795:1311[639c803cx_003c103cx] mad.f32 r15.x, c15.x, r14.y, r15.x + :3:0796:1312[639c803fx_00401040x] mad.f32 r15.w, c16.x, r14.y, r16.x + :3:0797:1313[638e003bx_003b1044x] mad.f32 r14.w, c17.x, r7.x, r14.w + :3:0798:1314[638e003cx_003c103dx] mad.f32 r15.x, c15.y, r7.x, r15.x + :3:0799:1315[638e001cx_003f1041x] mad.f32 r7.x, c16.y, r7.x, r15.w + :3:0800:1316[639c8039x_10251024x] mad.f32 r14.y, c9.x, r14.y, c9.y + :3:0801:1317[639d803fx_00221049x] mad.f32 r15.w, c18.y, r14.w, r8.z + :3:0802:1318[639e0040x_00221049x] mad.f32 r16.x, c18.y, r15.x, r8.z + :3:0803:1319[638e0843x_00221049x] (nop1) mad.f32 r16.w, c18.y, r7.x, r8.z + :3:0804:1321[639f803fx_10251024x] mad.f32 r15.w, c9.x, r15.w, c9.y + :3:0805:1322[63a00040x_10251024x] mad.f32 r16.x, c9.x, r16.x, c9.y + :3:0806:1323[63a18843x_10251024x] (nop1) mad.f32 r16.w, c9.x, r16.w, c9.y + :2:0807:1325[41300044x_0000003fx] floor.f r17.x, r15.w + :2:0808:1326[41380045x_00000040x] (nop2) floor.f r17.y, r16.x + :2:0809:1329[4010003fx_4044003fx] add.f r15.w, r15.w, (neg)r17.x + :2:0810:1330[40180040x_40450040x] (nop2) add.f r16.x, r16.x, (neg)r17.y + :3:0811:1333[639f803fx_10261023x] mad.f32 r15.w, c8.w, r15.w, c9.z + :3:0812:1334[63a00840x_10269023x] (nop3) mad.f32 r16.x, c8.w, r16.x, c9.z + :0:0813:1338[00000100x_00000000x] (rpt1)nop + :4:0814:1340[8090003fx_0000003fx] sin r15.w, r15.w + :3:0815:1341[6384103cx_003c003fx] (ss)mad.f32 r15.x, r15.w, r2.x, r15.x + :4:0816:1342[80900040x_00000040x] sin r16.x, r16.x + :3:0817:1343[6384101cx_001c8040x] (ss)(nop2) mad.f32 r7.x, r16.x, r2.x, r7.x + :2:0818:1346[4070003fx_1042003cx] mul.f r15.w, r15.x, c16.z + :2:0819:1347[40700044x_103f003cx] mul.f r17.x, r15.x, c15.w + :2:0820:1348[40700040x_103b003cx] mul.f r16.x, r15.x, c14.w + :3:0821:1349[639e003cx_10251024x] mad.f32 r15.x, c9.x, r15.x, c9.y + :3:0822:1350[638e0045x_10259024x] (nop2) mad.f32 r17.y, c9.x, r7.x, c9.y + :2:0823:1353[41300046x_0000003cx] floor.f r17.z, r15.x + :2:0824:1354[41380047x_00000045x] (nop2) floor.f r17.w, r17.y + :2:0825:1357[4010003cx_4046003cx] add.f r15.x, r15.x, (neg)r17.z + :2:0826:1358[40180045x_40470045x] (nop2) add.f r17.y, r17.y, (neg)r17.w + :3:0827:1361[639e003cx_10261023x] mad.f32 r15.x, c8.w, r15.x, c9.z + :3:0828:1362[63a28845x_10269023x] (nop3) mad.f32 r17.y, c8.w, r17.y, c9.z + :0:0829:1366[00000100x_00000000x] (rpt1)nop + :4:0830:1368[80b00046x_0000003cx] cos r17.z, r15.x + :4:0831:1369[8090103cx_0000003cx] (ss)sin r15.x, r15.x + :0:0832:1370[00000000x_00000000x] nop + :4:0833:1371[80900047x_00000045x] sin r17.w, r17.y + :4:0834:1372[80b01045x_00000045x] (ss)cos r17.y, r17.y + :2:0835:1373[40700046x_00470046x] mul.f r17.z, r17.z, r17.w + :2:0836:1374[41380847x_00000043x] (nop3) floor.f r17.w, r16.w + :2:0837:1378[40180843x_40470043x] (nop3) add.f r16.w, r16.w, (neg)r17.w + :3:0838:1382[63a18843x_10269023x] (nop3) mad.f32 r16.w, c8.w, r16.w, c9.z + :0:0839:1386[00000200x_00000000x] (rpt2)nop + :4:0840:1389[80900043x_00000043x] sin r16.w, r16.w + :3:0841:1390[6384183bx_003b8043x] (ss)(nop3) mad.f32 r14.w, r16.w, r2.x, r14.w + :3:0842:1394[639d803fx_003f1043x] mad.f32 r15.w, c16.w, r14.w, r15.w + :3:0843:1395[639d8040x_0040103cx] mad.f32 r16.x, c15.x, r14.w, r16.x + :3:0844:1396[639d8043x_00441040x] mad.f32 r16.w, c16.x, r14.w, r17.x + :3:0845:1397[639d803bx_10251024x] mad.f32 r14.w, c9.x, r14.w, c9.y + :3:0846:1398[638e003fx_003f1044x] mad.f32 r15.w, c17.x, r7.x, r15.w + :3:0847:1399[638e0040x_0040103dx] mad.f32 r16.x, c15.y, r7.x, r16.x + :3:0848:1400[638e001cx_00439041x] (nop2) mad.f32 r7.x, c16.y, r7.x, r16.w + :3:0849:1403[63a00044x_0020104cx] mad.f32 r17.x, c19.x, r16.x, r8.x + :3:0850:1404[638e0047x_0020104cx] mad.f32 r17.w, c19.x, r7.x, r8.x + :3:0851:1405[639f8843x_0020104cx] (nop1) mad.f32 r16.w, c19.x, r15.w, r8.x + :3:0852:1407[63a20044x_10251024x] mad.f32 r17.x, c9.x, r17.x, c9.y + :3:0853:1408[63a38047x_10251024x] mad.f32 r17.w, c9.x, r17.w, c9.y + :3:0854:1409[63a18843x_10251024x] (nop1) mad.f32 r16.w, c9.x, r16.w, c9.y + :2:0855:1411[41300849x_00000044x] (nop1) floor.f r18.y, r17.x + :2:0856:1413[41300848x_00000043x] (nop1) floor.f r18.x, r16.w + :2:0857:1415[40100844x_40490044x] (nop1) add.f r17.x, r17.x, (neg)r18.y + :2:0858:1417[40100843x_40480043x] (nop1) add.f r16.w, r16.w, (neg)r18.x + :3:0859:1419[63a20844x_10261023x] (nop1) mad.f32 r17.x, c8.w, r17.x, c9.z + :3:0860:1421[63a18843x_10269023x] (nop3) mad.f32 r16.w, c8.w, r16.w, c9.z + :0:0861:1425[00000000x_00000000x] nop + :4:0862:1426[80900044x_00000044x] sin r17.x, r17.x + :3:0863:1427[6384181cx_001c0044x] (ss)(nop1) mad.f32 r7.x, r17.x, r2.x, r7.x + :4:0864:1429[80900043x_00000043x] sin r16.w, r16.w + :3:0865:1430[63841840x_00400043x] (ss)(nop1) mad.f32 r16.x, r16.w, r2.x, r16.x + :3:0866:1432[638e081cx_10251024x] (nop1) mad.f32 r7.x, c9.x, r7.x, c9.y + :3:0867:1434[63a00840x_10251024x] (nop1) mad.f32 r16.x, c9.x, r16.x, c9.y + :2:0868:1436[41300844x_0000001cx] (nop1) floor.f r17.x, r7.x + :2:0869:1438[41300843x_00000040x] (nop1) floor.f r16.w, r16.x + :2:0870:1440[4010081cx_4044001cx] (nop1) add.f r7.x, r7.x, (neg)r17.x + :2:0871:1442[40100840x_40430040x] (nop1) add.f r16.x, r16.x, (neg)r16.w + :3:0872:1444[638e081cx_10261023x] (nop1) mad.f32 r7.x, c8.w, r7.x, c9.z + :3:0873:1446[63a00840x_10269023x] (nop3) mad.f32 r16.x, c8.w, r16.x, c9.z + :0:0874:1450[00000000x_00000000x] nop + :4:0875:1451[80900044x_0000001cx] sin r17.x, r7.x + :4:0876:1452[80b0101cx_0000001cx] (ss)cos r7.x, r7.x + :0:0877:1453[00000100x_00000000x] (rpt1)nop + :4:0878:1455[80b00043x_00000040x] cos r16.w, r16.x + :4:0879:1456[80901040x_00000040x] (ss)sin r16.x, r16.x + :2:0880:1457[40700043x_00440043x] mul.f r16.w, r16.w, r17.x + :2:0881:1458[41380844x_00000047x] (nop3) floor.f r17.x, r17.w + :2:0882:1462[40180844x_40440047x] (nop3) add.f r17.x, r17.w, (neg)r17.x + :3:0883:1466[63a20844x_10269023x] (nop3) mad.f32 r17.x, c8.w, r17.x, c9.z + :0:0884:1470[00000200x_00000000x] (rpt2)nop + :4:0885:1473[80900044x_00000044x] sin r17.x, r17.x + :3:0886:1474[6384183fx_003f8044x] (ss)(nop3) mad.f32 r15.w, r17.x, r2.x, r15.w + :3:0887:1478[639f883fx_10259024x] (nop3) mad.f32 r15.w, c9.x, r15.w, c9.y + :2:0888:1482[41380844x_0000003fx] (nop3) floor.f r17.x, r15.w + :2:0889:1486[4018083fx_4044003fx] (nop3) add.f r15.w, r15.w, (neg)r17.x + :3:0890:1490[639f883fx_10269023x] (nop3) mad.f32 r15.w, c8.w, r15.w, c9.z + :0:0891:1494[00000200x_00000000x] (rpt2)nop + :4:0892:1497[80b00044x_0000003fx] cos r17.x, r15.w + :4:0893:1498[8090103fx_0000003fx] (ss)sin r15.w, r15.w + :3:0894:1499[63a00840x_00430044x] (nop1) mad.f32 r16.x, r17.x, r16.x, r16.w + :3:0895:1501[639f901cx_0040001cx] (ss)mad.f32 r7.x, r7.x, r15.w, r16.x + :2:0896:1502[4138083fx_0000003bx] (nop3) floor.f r15.w, r14.w + :2:0897:1506[4010003bx_403f003bx] add.f r14.w, r14.w, (neg)r15.w + :2:0898:1507[4078001cx_104e001cx] (nop2) mul.f r7.x, r7.x, c19.z + :3:0899:1510[639d883bx_10269023x] (nop3) mad.f32 r14.w, c8.w, r14.w, c9.z + :0:0900:1514[00000200x_00000000x] (rpt2)nop + :4:0901:1517[80b0003fx_0000003bx] cos r15.w, r14.w + :4:0902:1518[8090103bx_0000003bx] (ss)sin r14.w, r14.w + :3:0903:1519[639e083cx_0046003fx] (nop1) mad.f32 r15.x, r15.w, r15.x, r17.z + :3:0904:1521[639d903bx_003c0045x] (ss)mad.f32 r14.w, r17.y, r14.w, r15.x + :2:0905:1522[4138083cx_00000039x] (nop3) floor.f r15.x, r14.y + :2:0906:1526[40100039x_403c0039x] add.f r14.y, r14.y, (neg)r15.x + :2:0907:1527[4078003bx_104b003bx] (nop2) mul.f r14.w, r14.w, c18.w + :3:0908:1530[639c8839x_10269023x] (nop3) mad.f32 r14.y, c8.w, r14.y, c9.z + :0:0909:1534[00000200x_00000000x] (rpt2)nop + :4:0910:1537[80b0003cx_00000039x] cos r15.x, r14.y + :4:0911:1538[80901039x_00000039x] (ss)sin r14.y, r14.y + :3:0912:1539[639d083ax_0042003cx] (nop1) mad.f32 r14.z, r15.x, r14.z, r16.z + :3:0913:1541[639c9039x_003a0041x] (ss)mad.f32 r14.y, r16.y, r14.y, r14.z + :2:0914:1542[4138083ax_0000002ex] (nop3) floor.f r14.z, r11.z + :2:0915:1546[4010002ex_403a002ex] add.f r11.z, r11.z, (neg)r14.z + :2:0916:1547[40780039x_10480039x] (nop2) mul.f r14.y, r14.y, c18.x + :3:0917:1550[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:0918:1554[00000200x_00000000x] (rpt2)nop + :4:0919:1557[80b0003ax_0000002ex] cos r14.z, r11.z + :4:0920:1558[8090102ex_0000002ex] (ss)sin r11.z, r11.z + :3:0921:1559[639b8837x_003e003ax] (nop1) mad.f32 r13.w, r14.z, r13.w, r15.z + :3:0922:1561[6397102ex_0037003dx] (ss)mad.f32 r11.z, r15.y, r11.z, r13.w + :2:0923:1562[41380837x_0000001ex] (nop3) floor.f r13.w, r7.z + :2:0924:1566[4010001ex_4037001ex] add.f r7.z, r7.z, (neg)r13.w + :2:0925:1567[4078002ex_1045002ex] (nop2) mul.f r11.z, r11.z, c17.y + :3:0926:1570[638f081ex_10269023x] (nop3) mad.f32 r7.z, c8.w, r7.z, c9.z + :0:0927:1574[00000200x_00000000x] (rpt2)nop + :4:0928:1577[80900037x_0000001ex] sin r13.w, r7.z + :4:0929:1578[80b0101ex_0000001ex] (ss)cos r7.z, r7.z + :2:0930:1579[40700837x_00370038x] (nop1) mul.f r13.w, r14.x, r13.w + :3:0931:1581[63880810x_00370036x] (nop1) mad.f32 r4.x, r13.z, r4.x, r13.w + :3:0932:1583[63981810x_0010801ex] (ss)(nop3) mad.f32 r4.x, r7.z, r12.x, r4.x + :2:0933:1587[40180810x_c02ec010x] (nop3) add.f r4.x, (absneg)r4.x, (absneg)r11.z + :2:0934:1591[40180810x_c0390010x] (nop3) add.f r4.x, r4.x, (absneg)r14.y + :2:0935:1595[40180810x_c03b0010x] (nop3) add.f r4.x, r4.x, (absneg)r14.w + :2:0936:1599[40100010x_c01c0010x] add.f r4.x, r4.x, (absneg)r7.x + :2:0937:1600[4130001cx_0000002fx] floor.f r7.x, r11.w + :3:0938:1601[63870010x_00109029x] (nop2) mad.f32 r4.x, c10.y, r3.z, r4.x + :2:0939:1604[4010001cx_401c002fx] add.f r7.x, r11.w, (neg)r7.x + :2:0940:1605[40180010x_104f8010x] (nop2) add.f r4.x, (abs)r4.x, c19.w + :3:0941:1608[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :3:0942:1609[63870810x_00109050x] (nop3) mad.f32 r4.x, c20.x, r3.z, r4.x + :0:0943:1613[00000100x_00000000x] (rpt1)nop + :4:0944:1615[8090001cx_0000001cx] sin r7.x, r7.x + :3:0945:1616[63908010x_0010001fx] mad.f32 r4.x, r7.w, r8.y, r4.x + :2:0946:1617[4070181cx_0008001cx] (ss)(nop1) mul.f r7.x, r7.x, r2.x + :3:0947:1619[6393801cx_001c1038x] mad.f32 r7.x, c14.x, r9.w, r7.x + :2:0948:1620[40180010x_10560010x] (nop2) add.f r4.x, r4.x, c21.z + :3:0949:1623[638e0027x_0032103cx] mad.f32 r9.w, c15.x, r7.x, r12.z + :3:0950:1624[638e001ex_002d1043x] mad.f32 r7.z, c16.w, r7.x, r11.y + :3:0951:1625[63960027x_0027103dx] mad.f32 r9.w, c15.y, r11.x, r9.w + :3:0952:1626[638e002dx_00331040x] mad.f32 r11.y, c16.x, r7.x, r12.w + :3:0953:1627[6396001ex_001e1044x] mad.f32 r7.z, c17.x, r11.x, r7.z + :3:0954:1628[6396002cx_002d1041x] mad.f32 r11.x, c16.y, r11.x, r11.y + :3:0955:1629[6393802ex_001b103ax] mad.f32 r11.z, c14.z, r9.w, r6.w + :3:0956:1630[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :3:0957:1631[638f002dx_001b103ax] mad.f32 r11.y, c14.z, r7.z, r6.w + :3:0958:1632[6396001bx_001b103ax] mad.f32 r6.w, c14.z, r11.x, r6.w + :3:0959:1633[6397082ex_10259024x] (nop3) mad.f32 r11.z, c9.x, r11.z, c9.y + :2:0960:1637[41300030x_0000002ex] floor.f r12.x, r11.z + :3:0961:1638[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :3:0962:1639[638d881bx_10251024x] (nop1) mad.f32 r6.w, c9.x, r6.w, c9.y + :2:0963:1641[4010002ex_4030002ex] add.f r11.z, r11.z, (neg)r12.x + :2:0964:1642[4138002fx_0000002dx] (nop2) floor.f r11.w, r11.y + :3:0965:1645[6397002ex_10261023x] mad.f32 r11.z, c8.w, r11.z, c9.z + :2:0966:1646[4018082dx_402f002dx] (nop3) add.f r11.y, r11.y, (neg)r11.w + :0:0967:1650[00000100x_00000000x] (rpt1)nop + :4:0968:1652[8090002ex_0000002ex] sin r11.z, r11.z + :3:0969:1653[6396802dx_10261023x] mad.f32 r11.y, c8.w, r11.y, c9.z + :3:0970:1654[6384182cx_002c802ex] (ss)(nop3) mad.f32 r11.x, r11.z, r2.x, r11.x + :3:0971:1658[63960830x_10259024x] (nop3) mad.f32 r12.x, c9.x, r11.x, c9.y + :2:0972:1662[41300033x_00000030x] floor.f r12.w, r12.x + :4:0973:1663[8090002dx_0000002dx] sin r11.y, r11.y + :3:0974:1664[63841027x_0027802dx] (ss)(nop2) mad.f32 r9.w, r11.y, r2.x, r9.w + :2:0975:1667[40100030x_40330030x] add.f r12.x, r12.x, (neg)r12.w + :2:0976:1668[4070002dx_10420027x] mul.f r11.y, r9.w, c16.z + :2:0977:1669[4070002ex_103b0027x] mul.f r11.z, r9.w, c14.w + :2:0978:1670[4070002fx_103f0027x] mul.f r11.w, r9.w, c15.w + :3:0979:1671[63980030x_10261023x] mad.f32 r12.x, c8.w, r12.x, c9.z + :3:0980:1672[63938827x_10259024x] (nop3) mad.f32 r9.w, c9.x, r9.w, c9.y + :0:0981:1676[00000100x_00000000x] (rpt1)nop + :4:0982:1678[80900033x_00000030x] sin r12.w, r12.x + :4:0983:1679[80b01030x_00000030x] (ss)cos r12.x, r12.x + :2:0984:1680[41380832x_00000027x] (nop3) floor.f r12.z, r9.w + :2:0985:1684[40180827x_40320027x] (nop3) add.f r9.w, r9.w, (neg)r12.z + :3:0986:1688[63938827x_10269023x] (nop3) mad.f32 r9.w, c8.w, r9.w, c9.z + :0:0987:1692[00000200x_00000000x] (rpt2)nop + :4:0988:1695[80b00032x_00000027x] cos r12.z, r9.w + :4:0989:1696[80901027x_00000027x] (ss)sin r9.w, r9.w + :2:0990:1697[40700032x_00330032x] mul.f r12.z, r12.z, r12.w + :2:0991:1698[41380833x_0000001bx] (nop3) floor.f r12.w, r6.w + :2:0992:1702[4018081bx_4033001bx] (nop3) add.f r6.w, r6.w, (neg)r12.w + :3:0993:1706[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:0994:1710[00000200x_00000000x] (rpt2)nop + :4:0995:1713[8090001bx_0000001bx] sin r6.w, r6.w + :3:0996:1714[6384181bx_001e801bx] (ss)(nop3) mad.f32 r6.w, r6.w, r2.x, r7.z + :3:0997:1718[638d801ex_002d1043x] mad.f32 r7.z, c16.w, r6.w, r11.y + :3:0998:1719[638d802dx_002e103cx] mad.f32 r11.y, c15.x, r6.w, r11.z + :3:0999:1720[6396001ex_001e1044x] mad.f32 r7.z, c17.x, r11.x, r7.z + :3:1000:1721[6396002dx_002d103dx] mad.f32 r11.y, c15.y, r11.x, r11.y + :3:1001:1722[638d802ex_002f1040x] mad.f32 r11.z, c16.x, r6.w, r11.w + :3:1002:1723[638d801bx_10251024x] mad.f32 r6.w, c9.x, r6.w, c9.y + :3:1003:1724[6396002cx_002e1041x] mad.f32 r11.x, c16.y, r11.x, r11.z + :3:1004:1725[6396802fx_00241046x] mad.f32 r11.w, c17.z, r11.y, r9.x + :3:1005:1726[638f002ex_00249046x] (nop2) mad.f32 r11.z, c17.z, r7.z, r9.x + :3:1006:1729[6397802fx_10251024x] mad.f32 r11.w, c9.x, r11.w, c9.y + :3:1007:1730[63960024x_00241046x] mad.f32 r9.x, c17.z, r11.x, r9.x + :3:1008:1731[6397082ex_10251024x] (nop1) mad.f32 r11.z, c9.x, r11.z, c9.y + :2:1009:1733[41300036x_0000002fx] floor.f r13.z, r11.w + :3:1010:1734[63920024x_10251024x] mad.f32 r9.x, c9.x, r9.x, c9.y + :2:1011:1735[41300833x_0000002ex] (nop1) floor.f r12.w, r11.z + :2:1012:1737[4018082fx_4036002fx] (nop3) add.f r11.w, r11.w, (neg)r13.z + :3:1013:1741[6397802fx_10261023x] mad.f32 r11.w, c8.w, r11.w, c9.z + :2:1014:1742[4018082ex_4033002ex] (nop3) add.f r11.z, r11.z, (neg)r12.w + :0:1015:1746[00000100x_00000000x] (rpt1)nop + :4:1016:1748[8090002fx_0000002fx] sin r11.w, r11.w + :3:1017:1749[6397002ex_10261023x] mad.f32 r11.z, c8.w, r11.z, c9.z + :3:1018:1750[6384182cx_002c802fx] (ss)(nop3) mad.f32 r11.x, r11.w, r2.x, r11.x + :3:1019:1754[63960836x_10259024x] (nop3) mad.f32 r13.z, c9.x, r11.x, c9.y + :2:1020:1758[41300038x_00000036x] floor.f r14.x, r13.z + :4:1021:1759[8090002ex_0000002ex] sin r11.z, r11.z + :3:1022:1760[6384102dx_002d802ex] (ss)(nop2) mad.f32 r11.y, r11.z, r2.x, r11.y + :2:1023:1763[40100036x_40380036x] add.f r13.z, r13.z, (neg)r14.x + :2:1024:1764[4070002ex_1042002dx] mul.f r11.z, r11.y, c16.z + :2:1025:1765[4070002fx_103b002dx] mul.f r11.w, r11.y, c14.w + :2:1026:1766[40700033x_103f002dx] mul.f r12.w, r11.y, c15.w + :3:1027:1767[639b0036x_10261023x] mad.f32 r13.z, c8.w, r13.z, c9.z + :3:1028:1768[6396882dx_10259024x] (nop3) mad.f32 r11.y, c9.x, r11.y, c9.y + :0:1029:1772[00000100x_00000000x] (rpt1)nop + :4:1030:1774[80900038x_00000036x] sin r14.x, r13.z + :4:1031:1775[80b01036x_00000036x] (ss)cos r13.z, r13.z + :2:1032:1776[41380837x_0000002dx] (nop3) floor.f r13.w, r11.y + :2:1033:1780[4018082dx_4037002dx] (nop3) add.f r11.y, r11.y, (neg)r13.w + :3:1034:1784[6396882dx_10269023x] (nop3) mad.f32 r11.y, c8.w, r11.y, c9.z + :0:1035:1788[00000200x_00000000x] (rpt2)nop + :4:1036:1791[80b00037x_0000002dx] cos r13.w, r11.y + :4:1037:1792[8090102dx_0000002dx] (ss)sin r11.y, r11.y + :2:1038:1793[40700037x_00380037x] mul.f r13.w, r13.w, r14.x + :2:1039:1794[41380838x_00000024x] (nop3) floor.f r14.x, r9.x + :2:1040:1798[40180824x_40380024x] (nop3) add.f r9.x, r9.x, (neg)r14.x + :3:1041:1802[63920824x_10269023x] (nop3) mad.f32 r9.x, c8.w, r9.x, c9.z + :0:1042:1806[00000200x_00000000x] (rpt2)nop + :4:1043:1809[80900024x_00000024x] sin r9.x, r9.x + :3:1044:1810[6384181ex_001e8024x] (ss)(nop3) mad.f32 r7.z, r9.x, r2.x, r7.z + :3:1045:1814[638f0024x_002e1043x] mad.f32 r9.x, c16.w, r7.z, r11.z + :3:1046:1815[638f002ex_002f103cx] mad.f32 r11.z, c15.x, r7.z, r11.w + :3:1047:1816[638f002fx_00331040x] mad.f32 r11.w, c16.x, r7.z, r12.w + :3:1048:1817[6396002ex_002e103dx] mad.f32 r11.z, c15.y, r11.x, r11.z + :3:1049:1818[63960024x_00241044x] mad.f32 r9.x, c17.x, r11.x, r9.x + :3:1050:1819[6396002cx_002f1041x] mad.f32 r11.x, c16.y, r11.x, r11.w + :3:1051:1820[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :3:1052:1821[63970033x_00221049x] mad.f32 r12.w, c18.y, r11.z, r8.z + :3:1053:1822[6392002fx_00221049x] mad.f32 r11.w, c18.y, r9.x, r8.z + :3:1054:1823[63960822x_00221049x] (nop1) mad.f32 r8.z, c18.y, r11.x, r8.z + :3:1055:1825[63998033x_10251024x] mad.f32 r12.w, c9.x, r12.w, c9.y + :3:1056:1826[6397802fx_10251024x] mad.f32 r11.w, c9.x, r11.w, c9.y + :3:1057:1827[63910822x_10251024x] (nop1) mad.f32 r8.z, c9.x, r8.z, c9.y + :2:1058:1829[41300039x_00000033x] floor.f r14.y, r12.w + :2:1059:1830[41380038x_0000002fx] (nop2) floor.f r14.x, r11.w + :2:1060:1833[40100033x_40390033x] add.f r12.w, r12.w, (neg)r14.y + :2:1061:1834[4018002fx_4038002fx] (nop2) add.f r11.w, r11.w, (neg)r14.x + :3:1062:1837[63998033x_10261023x] mad.f32 r12.w, c8.w, r12.w, c9.z + :3:1063:1838[6397882fx_10269023x] (nop3) mad.f32 r11.w, c8.w, r11.w, c9.z + :0:1064:1842[00000100x_00000000x] (rpt1)nop + :4:1065:1844[80900033x_00000033x] sin r12.w, r12.w + :3:1066:1845[6384102cx_002c0033x] (ss)mad.f32 r11.x, r12.w, r2.x, r11.x + :4:1067:1846[8090002fx_0000002fx] sin r11.w, r11.w + :3:1068:1847[6384102ex_002e802fx] (ss)(nop2) mad.f32 r11.z, r11.w, r2.x, r11.z + :3:1069:1850[63960039x_10251024x] mad.f32 r14.y, c9.x, r11.x, c9.y + :2:1070:1851[4070002fx_1042002ex] mul.f r11.w, r11.z, c16.z + :2:1071:1852[40700033x_103b002ex] mul.f r12.w, r11.z, c14.w + :2:1072:1853[40700038x_103f002ex] mul.f r14.x, r11.z, c15.w + :2:1073:1854[4130003bx_00000039x] floor.f r14.w, r14.y + :3:1074:1855[6397002ex_10259024x] (nop2) mad.f32 r11.z, c9.x, r11.z, c9.y + :2:1075:1858[40100039x_403b0039x] add.f r14.y, r14.y, (neg)r14.w + :2:1076:1859[4138003ax_0000002ex] (nop2) floor.f r14.z, r11.z + :3:1077:1862[639c8039x_10261023x] mad.f32 r14.y, c8.w, r14.y, c9.z + :2:1078:1863[4018082ex_403a002ex] (nop3) add.f r11.z, r11.z, (neg)r14.z + :0:1079:1867[00000100x_00000000x] (rpt1)nop + :4:1080:1869[8090003bx_00000039x] sin r14.w, r14.y + :4:1081:1870[80b01039x_00000039x] (ss)cos r14.y, r14.y + :3:1082:1871[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:1083:1875[00000200x_00000000x] (rpt2)nop + :4:1084:1878[80b0003ax_0000002ex] cos r14.z, r11.z + :4:1085:1879[8090102ex_0000002ex] (ss)sin r11.z, r11.z + :2:1086:1880[4070003ax_003b003ax] mul.f r14.z, r14.z, r14.w + :2:1087:1881[4138083bx_00000022x] (nop3) floor.f r14.w, r8.z + :2:1088:1885[40180822x_403b0022x] (nop3) add.f r8.z, r8.z, (neg)r14.w + :3:1089:1889[63910822x_10269023x] (nop3) mad.f32 r8.z, c8.w, r8.z, c9.z + :0:1090:1893[00000200x_00000000x] (rpt2)nop + :4:1091:1896[80900022x_00000022x] sin r8.z, r8.z + :3:1092:1897[63841822x_00248022x] (ss)(nop3) mad.f32 r8.z, r8.z, r2.x, r9.x + :3:1093:1901[63910024x_002f1043x] mad.f32 r9.x, c16.w, r8.z, r11.w + :3:1094:1902[6391002fx_0033103cx] mad.f32 r11.w, c15.x, r8.z, r12.w + :3:1095:1903[63960024x_00241044x] mad.f32 r9.x, c17.x, r11.x, r9.x + :3:1096:1904[63910033x_00381040x] mad.f32 r12.w, c16.x, r8.z, r14.x + :3:1097:1905[6396002fx_002f103dx] mad.f32 r11.w, c15.y, r11.x, r11.w + :3:1098:1906[6396002cx_00331041x] mad.f32 r11.x, c16.y, r11.x, r12.w + :3:1099:1907[63920033x_0020104cx] mad.f32 r12.w, c19.x, r9.x, r8.x + :3:1100:1908[63910022x_10251024x] mad.f32 r8.z, c9.x, r8.z, c9.y + :3:1101:1909[63978038x_0020104cx] mad.f32 r14.x, c19.x, r11.w, r8.x + :3:1102:1910[63960020x_0020104cx] mad.f32 r8.x, c19.x, r11.x, r8.x + :3:1103:1911[63998833x_10251024x] (nop1) mad.f32 r12.w, c9.x, r12.w, c9.y + :3:1104:1913[639c0038x_10251024x] mad.f32 r14.x, c9.x, r14.x, c9.y + :3:1105:1914[63900020x_10251024x] mad.f32 r8.x, c9.x, r8.x, c9.y + :2:1106:1915[4130083bx_00000033x] (nop1) floor.f r14.w, r12.w + :2:1107:1917[4130083cx_00000038x] (nop1) floor.f r15.x, r14.x + :2:1108:1919[40100833x_403b0033x] (nop1) add.f r12.w, r12.w, (neg)r14.w + :2:1109:1921[40100838x_403c0038x] (nop1) add.f r14.x, r14.x, (neg)r15.x + :3:1110:1923[63998833x_10261023x] (nop1) mad.f32 r12.w, c8.w, r12.w, c9.z + :3:1111:1925[639c0838x_10269023x] (nop3) mad.f32 r14.x, c8.w, r14.x, c9.z + :0:1112:1929[00000000x_00000000x] nop + :4:1113:1930[80900033x_00000033x] sin r12.w, r12.w + :3:1114:1931[6384182fx_002f0033x] (ss)(nop1) mad.f32 r11.w, r12.w, r2.x, r11.w + :4:1115:1933[80900038x_00000038x] sin r14.x, r14.x + :3:1116:1934[6384182cx_002c0038x] (ss)(nop1) mad.f32 r11.x, r14.x, r2.x, r11.x + :3:1117:1936[6397882fx_10251024x] (nop1) mad.f32 r11.w, c9.x, r11.w, c9.y + :3:1118:1938[6396082cx_10251024x] (nop1) mad.f32 r11.x, c9.x, r11.x, c9.y + :2:1119:1940[41300833x_0000002fx] (nop1) floor.f r12.w, r11.w + :2:1120:1942[41300838x_0000002cx] (nop1) floor.f r14.x, r11.x + :2:1121:1944[4010082fx_4033002fx] (nop1) add.f r11.w, r11.w, (neg)r12.w + :2:1122:1946[4010082cx_4038002cx] (nop1) add.f r11.x, r11.x, (neg)r14.x + :3:1123:1948[6397882fx_10261023x] (nop1) mad.f32 r11.w, c8.w, r11.w, c9.z + :3:1124:1950[6396082cx_10269023x] (nop3) mad.f32 r11.x, c8.w, r11.x, c9.z + :0:1125:1954[00000000x_00000000x] nop + :4:1126:1955[80b00033x_0000002fx] cos r12.w, r11.w + :4:1127:1956[8090102fx_0000002fx] (ss)sin r11.w, r11.w + :0:1128:1957[00000100x_00000000x] (rpt1)nop + :4:1129:1959[80900038x_0000002cx] sin r14.x, r11.x + :4:1130:1960[80b0102cx_0000002cx] (ss)cos r11.x, r11.x + :2:1131:1961[40700033x_00380033x] mul.f r12.w, r12.w, r14.x + :2:1132:1962[41380838x_00000020x] (nop3) floor.f r14.x, r8.x + :2:1133:1966[40180820x_40380020x] (nop3) add.f r8.x, r8.x, (neg)r14.x + :3:1134:1970[63900820x_10269023x] (nop3) mad.f32 r8.x, c8.w, r8.x, c9.z + :0:1135:1974[00000200x_00000000x] (rpt2)nop + :4:1136:1977[80900020x_00000020x] sin r8.x, r8.x + :3:1137:1978[63841808x_00248020x] (ss)(nop3) mad.f32 r2.x, r8.x, r2.x, r9.x + :3:1138:1982[63840808x_10259024x] (nop3) mad.f32 r2.x, c9.x, r2.x, c9.y + :2:1139:1986[41380820x_00000008x] (nop3) floor.f r8.x, r2.x + :2:1140:1990[40180808x_40200008x] (nop3) add.f r2.x, r2.x, (neg)r8.x + :3:1141:1994[63840808x_10269023x] (nop3) mad.f32 r2.x, c8.w, r2.x, c9.z + :0:1142:1998[00000200x_00000000x] (rpt2)nop + :4:1143:2001[80b00020x_00000008x] cos r8.x, r2.x + :4:1144:2002[80901008x_00000008x] (ss)sin r2.x, r2.x + :3:1145:2003[63978820x_00330020x] (nop1) mad.f32 r8.x, r8.x, r11.w, r12.w + :3:1146:2005[63841008x_0020002cx] (ss)mad.f32 r2.x, r11.x, r2.x, r8.x + :2:1147:2006[41380820x_00000022x] (nop3) floor.f r8.x, r8.z + :2:1148:2010[40100020x_40200022x] add.f r8.x, r8.z, (neg)r8.x + :2:1149:2011[40780008x_104e0008x] (nop2) mul.f r2.x, r2.x, c19.z + :3:1150:2014[63900820x_10269023x] (nop3) mad.f32 r8.x, c8.w, r8.x, c9.z + :0:1151:2018[00000200x_00000000x] (rpt2)nop + :4:1152:2021[80b00022x_00000020x] cos r8.z, r8.x + :4:1153:2022[80901020x_00000020x] (ss)sin r8.x, r8.x + :3:1154:2023[63970822x_003a0022x] (nop1) mad.f32 r8.z, r8.z, r11.z, r14.z + :3:1155:2025[63901020x_00220039x] (ss)mad.f32 r8.x, r14.y, r8.x, r8.z + :2:1156:2026[41380822x_0000001ex] (nop3) floor.f r8.z, r7.z + :2:1157:2030[4010001ex_4022001ex] add.f r7.z, r7.z, (neg)r8.z + :2:1158:2031[40780020x_104b0020x] (nop2) mul.f r8.x, r8.x, c18.w + :3:1159:2034[638f081ex_10269023x] (nop3) mad.f32 r7.z, c8.w, r7.z, c9.z + :0:1160:2038[00000200x_00000000x] (rpt2)nop + :4:1161:2041[80b00022x_0000001ex] cos r8.z, r7.z + :4:1162:2042[8090101ex_0000001ex] (ss)sin r7.z, r7.z + :3:1163:2043[63968822x_00370022x] (nop1) mad.f32 r8.z, r8.z, r11.y, r13.w + :3:1164:2045[638f101ex_00220036x] (ss)mad.f32 r7.z, r13.z, r7.z, r8.z + :2:1165:2046[41380822x_0000001bx] (nop3) floor.f r8.z, r6.w + :2:1166:2050[4010001bx_4022001bx] add.f r6.w, r6.w, (neg)r8.z + :2:1167:2051[4078001ex_1048001ex] (nop2) mul.f r7.z, r7.z, c18.x + :3:1168:2054[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:1169:2058[00000200x_00000000x] (rpt2)nop + :4:1170:2061[80b00022x_0000001bx] cos r8.z, r6.w + :4:1171:2062[8090101bx_0000001bx] (ss)sin r6.w, r6.w + :3:1172:2063[63938822x_00320022x] (nop1) mad.f32 r8.z, r8.z, r9.w, r12.z + :3:1173:2065[638d901bx_00220030x] (ss)mad.f32 r6.w, r12.x, r6.w, r8.z + :2:1174:2066[41380822x_0000001cx] (nop3) floor.f r8.z, r7.x + :2:1175:2070[4010001cx_4022001cx] add.f r7.x, r7.x, (neg)r8.z + :2:1176:2071[4078001bx_1045001bx] (nop2) mul.f r6.w, r6.w, c17.y + :3:1177:2074[638e081cx_10269023x] (nop3) mad.f32 r7.x, c8.w, r7.x, c9.z + :0:1178:2078[00000200x_00000000x] (rpt2)nop + :4:1179:2081[80b00022x_0000001cx] cos r8.z, r7.x + :4:1180:2082[8090101cx_0000001cx] (ss)sin r7.x, r7.x + :3:1181:2083[63958822x_00350022x] (nop1) mad.f32 r8.z, r8.z, r10.w, r13.y + :3:1182:2085[638e181cx_00228034x] (ss)(nop3) mad.f32 r7.x, r13.x, r7.x, r8.z + :2:1183:2089[4010001bx_c01bc01cx] add.f r6.w, (absneg)r7.x, (absneg)r6.w + :2:1184:2090[4070001cx_10360019x] mul.f r7.x, r6.y, c13.z + :2:1185:2091[40700819x_10340019x] (nop1) mul.f r6.y, r6.y, c13.x + :2:1186:2093[4010001bx_c01e001bx] add.f r6.w, r6.w, (absneg)r7.z + :3:1187:2094[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :3:1188:2095[638c8019x_10251024x] mad.f32 r6.y, c9.x, r6.y, c9.y + :2:1189:2096[4070001ex_10340028x] mul.f r7.z, r10.x, c13.x + :2:1190:2097[4010001bx_c020001bx] add.f r6.w, r6.w, (absneg)r8.x + :2:1191:2098[41300022x_0000001cx] floor.f r8.z, r7.x + :2:1192:2099[41300024x_00000019x] floor.f r9.x, r6.y + :3:1193:2100[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :2:1194:2101[40100008x_c008001bx] add.f r2.x, r6.w, (absneg)r2.x + :2:1195:2102[4070001bx_10360028x] mul.f r6.w, r10.x, c13.z + :2:1196:2103[40100019x_40240019x] add.f r6.y, r6.y, (neg)r9.x + :2:1197:2104[4010001cx_4022001cx] add.f r7.x, r7.x, (neg)r8.z + :3:1198:2105[63870008x_00081029x] mad.f32 r2.x, c10.y, r3.z, r2.x + :3:1199:2106[638d801bx_10251024x] mad.f32 r6.w, c9.x, r6.w, c9.y + :3:1200:2107[638c8019x_10261023x] mad.f32 r6.y, c8.w, r6.y, c9.z + :3:1201:2108[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :2:1202:2109[40100008x_104f8008x] add.f r2.x, (abs)r2.x, c19.w + :2:1203:2110[41300020x_0000001bx] floor.f r8.x, r6.w + :3:1204:2111[63870008x_00089050x] (nop2) mad.f32 r2.x, c20.x, r3.z, r2.x + :2:1205:2114[4010001bx_4020001bx] add.f r6.w, r6.w, (neg)r8.x + :4:1206:2115[80900019x_00000019x] sin r6.y, r6.y + :4:1207:2116[80b0001cx_0000001cx] cos r7.x, r7.x + :3:1208:2117[63908008x_0008001fx] mad.f32 r2.x, r7.w, r8.y, r2.x + :2:1209:2118[40701819x_10210019x] (ss)(nop1) mul.f r6.y, r6.y, c8.y + :3:1210:2120[638d801bx_10261023x] mad.f32 r6.w, c8.w, r6.w, c9.z + :2:1211:2121[4070001cx_1021001cx] mul.f r7.x, r7.x, c8.y + :2:1212:2122[40100008x_10560008x] add.f r2.x, r2.x, c21.z + :2:1213:2123[40180812x_40190012x] (nop3) add.f r4.z, r4.z, (neg)r6.y + :4:1214:2127[80b0001bx_0000001bx] cos r6.w, r6.w + :2:1215:2128[4078181bx_1021001bx] (ss)(nop3) mul.f r6.w, r6.w, c8.y + :2:1216:2132[40100018x_401b0018x] add.f r6.x, r6.x, (neg)r6.w + :2:1217:2133[4018081bx_401c002ax] (nop3) add.f r6.w, r10.z, (neg)r7.x + :2:1218:2137[4070001bx_001b001bx] mul.f r6.w, r6.w, r6.w + :2:1219:2138[40700018x_00180018x] mul.f r6.x, r6.x, r6.x + :3:1220:2139[63890812x_001b8012x] (nop3) mad.f32 r4.z, r4.z, r4.z, r6.w + :3:1221:2143[63890010x_0010102dx] mad.f32 r4.x, c11.y, r4.z, r4.x + :2:1222:2144[41300012x_0000001ex] floor.f r4.z, r7.z + :3:1223:2145[63928010x_8010903ex] (nop2) mad.f32 r4.x, c15.z, r9.y, (neg)r4.x + :2:1224:2148[40100012x_4012001ex] add.f r4.z, r7.z, (neg)r4.z + :2:1225:2149[40780010x_10270010x] (nop2) mul.f r4.x, r4.x, c9.w + :3:1226:2152[63890012x_10261023x] mad.f32 r4.z, c8.w, r4.z, c9.z + :2:1227:2153[40580c10x_10580010x] (sat)(nop3) max.f r4.x, r4.x, c22.x + :0:1228:2157[00000100x_00000000x] (rpt1)nop + :4:1229:2159[80900012x_00000012x] sin r4.z, r4.z + :2:1230:2160[40781812x_10210012x] (ss)(nop3) mul.f r4.z, r4.z, c8.y + :2:1231:2164[40180812x_40120031x] (nop3) add.f r4.z, r12.y, (neg)r4.z + :3:1232:2168[63890812x_00188012x] (nop3) mad.f32 r4.z, r4.z, r4.z, r6.x + :3:1233:2172[63890808x_0008102dx] (nop1) mad.f32 r2.x, c11.y, r4.z, r2.x + :3:1234:2174[63928808x_8008903ex] (nop3) mad.f32 r2.x, c15.z, r9.y, (neg)r2.x + :2:1235:2178[40780808x_10570008x] (nop3) mul.f r2.x, r2.x, c21.w + :2:1236:2182[40580c08x_10580008x] (sat)(nop3) max.f r2.x, r2.x, c22.x + :2:1237:2186[40180808x_00100008x] (nop3) add.f r2.x, r2.x, r4.x + :3:1238:2190[63840010x_1060105fx] mad.f32 r4.x, c23.w, r2.x, c24.x + :3:1239:2191[63840012x_105a1054x] mad.f32 r4.z, c21.x, r2.x, c22.z + :3:1240:2192[63840808x_105d105cx] (nop1) mad.f32 r2.x, c23.x, r2.x, c23.y + :2:1241:2194[40700010x_00100026x] mul.f r4.x, r9.z, r4.x + :2:1242:2195[40700012x_00120026x] mul.f r4.z, r9.z, r4.z + :2:1243:2196[40700818x_00080026x] (nop1) mul.f r6.x, r9.z, r2.x + :2:1244:2198[40700808x_0010001ax] (nop1) mul.f r2.x, r6.z, r4.x + :2:1245:2200[40700009x_00180029x] mul.f r2.y, r10.y, r6.x + :2:1246:2201[4070000ax_0012001dx] mul.f r2.z, r7.y, r4.z + :0:1247:2202[01000000x_0000000ex] jump #14 + :1:1248:2203[284cc007x_00000000x] (jp)mov.u32u32 r1.w, 0x00000000 + :0:1249:2204[00000200x_00000000x] (rpt2)nop + :1:1250:2207[200cc010x_00000007x] mov.u32u32 r4.x, r1.w + :0:1251:2208[00000200x_00000000x] (rpt2)nop + :1:1252:2211[200cc00ax_00000010x] mov.u32u32 r2.z, r4.x + :0:1253:2212[00000200x_00000000x] (rpt2)nop + :1:1254:2215[200cc010x_0000000ax] mov.u32u32 r4.x, r2.z + :0:1255:2216[00000200x_00000000x] (rpt2)nop + :1:1256:2219[200cc009x_00000010x] mov.u32u32 r2.y, r4.x + :0:1257:2220[00000200x_00000000x] (rpt2)nop + :1:1258:2223[200cc010x_00000009x] mov.u32u32 r4.x, r2.y + :0:1259:2224[00000200x_00000000x] (rpt2)nop + :1:1260:2227[200cc008x_00000010x] mov.u32u32 r2.x, r4.x + :1:1261:2228[280cc012x_00000004x] (jp)mov.u32u32 r4.z, r1.x + :1:1262:2229[200cc019x_00000009x] mov.u32u32 r6.y, r2.y + :1:1263:2230[200cc01ax_0000000ax] mov.u32u32 r6.z, r2.z + :1:1264:2231[200cc01bx_00000007x] mov.u32u32 r6.w, r1.w + :3:1265:2232[63890012x_102c102dx] mad.f32 r4.z, c11.y, r4.z, c11.x + :1:1266:2233[200cc01cx_00000003x] mov.u32u32 r7.x, r0.w + :1:1267:2234[200cc01dx_00000000x] mov.u32u32 r7.y, r0.x + :1:1268:2235[200cc01ex_00000001x] mov.u32u32 r7.z, r0.y + :2:1269:2236[40700012x_102e0012x] mul.f r4.z, r4.z, c11.z + :2:1270:2237[4010001cx_401c1022x] add.f r7.x, c8.z, (neg)r7.x + :1:1271:2238[200cc020x_00000002x] mov.u32u32 r8.x, r0.z + :2:1272:2239[40780810x_102a0023x] (nop3) mul.f r4.x, r8.w, c10.z + :4:1273:2243[8070000bx_00000012x] exp2 r2.w, r4.z + :2:1274:2244[40700010x_00230010x] mul.f r4.x, r4.x, r8.w + :1:1275:2245[200cd012x_0000000bx] (ss)mov.u32u32 r4.z, r2.w + :1:1276:2246[200cc018x_00000005x] mov.u32u32 r6.x, r1.y + :0:1277:2247[00000200x_00000000x] (rpt2)nop + :2:1278:2250[40100412x_40180012x] (sat)add.f r4.z, r4.z, (neg)r6.x + :2:1279:2251[40100010x_40101025x] add.f r4.x, c9.y, (neg)r4.x + :1:1280:2252[200cc018x_00000003x] mov.u32u32 r6.x, r0.w + :1:1281:2253[200cc022x_00000004x] mov.u32u32 r8.z, r1.x + :3:1282:2254[63890008x_0008102bx] mad.f32 r2.x, c10.w, r4.z, r2.x + :3:1283:2255[63890019x_00191061x] mad.f32 r6.y, c24.y, r4.z, r6.y + :3:1284:2256[6389001bx_001b1037x] mad.f32 r6.w, c13.w, r4.z, r6.w + :2:1285:2257[40500010x_10710010x] max.f r4.x, r4.x, c28.y + :3:1286:2258[638e0000x_001d0008x] mad.f32 r0.x, r2.x, r7.x, r7.y + :3:1287:2259[63890008x_001a1061x] mad.f32 r2.x, c24.y, r4.z, r6.z + :3:1288:2260[638e0001x_001e0019x] mad.f32 r0.y, r6.y, r7.x, r7.z + :2:1289:2261[40300010x_10500010x] min.f r4.x, r4.x, c20.x + :1:1290:2262[200cc023x_00000006x] mov.u32u32 r8.w, r1.z + :3:1291:2263[638e0002x_00200008x] mad.f32 r0.z, r2.x, r7.x, r8.x + :3:1292:2264[638e0003x_0018001bx] mad.f32 r0.w, r6.w, r7.x, r6.x + :2:1293:2265[40100004x_00100022x] add.f r1.x, r8.z, r4.x + :1:1294:2266[200cc024x_0000000bx] mov.u32u32 r9.x, r2.w + :2:1295:2267[42180006x_20010023x] (nop2) add.u r1.z, r8.w, 1 + :1:1296:2270[200cc005x_00000024x] mov.u32u32 r1.y, r9.x + :0:1297:2271[01000000x_fffffb99x] jump #-1127 + :2:1298:2272[48500401x_00010001x] (jp)(sat)max.f r0.y, r0.y, r0.y + :2:1299:2273[40500402x_00020002x] (sat)max.f r0.z, r0.z, r0.z + :2:1300:2274[40100003x_400e1022x] add.f r0.w, c8.z, (neg)r3.z + :2:1301:2275[40500400x_00000000x] (sat)max.f r0.x, r0.x, r0.x + :2:1302:2276[4070000fx_00010001x] mul.f r3.w, r0.y, r0.y + :2:1303:2277[40500006x_00010002x] max.f r1.z, r0.z, r0.y + :2:1304:2278[40500403x_102a0003x] (sat)max.f r0.w, r0.w, c10.z + :2:1305:2279[40500004x_00010000x] max.f r1.x, r0.x, r0.y + :2:1306:2280[40100005x_40020000x] add.f r1.y, r0.x, (neg)r0.z + :2:1307:2281[40300007x_00010000x] min.f r1.w, r0.x, r0.y + :2:1308:2282[4010000ex_40000002x] add.f r3.z, r0.z, (neg)r0.x + :2:1309:2283[40500004x_00020004x] max.f r1.x, r1.x, r0.z + :3:1310:2284[63828005x_00020003x] mad.f32 r1.y, r0.w, r1.y, r0.z + :2:1311:2285[40300007x_00020007x] min.f r1.w, r1.w, r0.z + :2:1312:2286[40500006x_00000006x] max.f r1.z, r1.z, r0.x + :3:1313:2287[6387000ex_00000003x] mad.f32 r3.z, r0.w, r3.z, r0.x + :2:1314:2288[40100008x_10630004x] add.f r2.x, r1.x, c24.w + :2:1315:2289[40100005x_10620005x] add.f r1.y, r1.y, c24.z + :2:1316:2290[40300002x_00010002x] min.f r0.z, r0.z, r0.y + :2:1317:2291[40100004x_40070004x] add.f r1.x, r1.x, (neg)r1.w + :3:1318:2292[6380800ax_80051021x] mad.f32 r2.z, c8.y, r0.y, (neg)r1.y + :3:1319:2293[6382800fx_000f0005x] mad.f32 r3.w, r1.y, r1.y, r3.w + :2:1320:2294[40300000x_00000002x] min.f r0.x, r0.z, r0.x + :4:1321:2295[80100008x_00000008x] rcp r2.x, r2.x + :2:1322:2296[40500007x_00010005x] max.f r1.w, r1.y, r0.y + :2:1323:2297[40100002x_400e000ax] add.f r0.z, r2.z, (neg)r3.z + :2:1324:2298[4030000cx_00010005x] min.f r3.x, r1.y, r0.y + :3:1325:2299[6387000ax_000f000ex] mad.f32 r2.z, r3.z, r3.z, r3.w + :2:1326:2300[40500007x_000e0007x] max.f r1.w, r1.w, r3.z + :2:1327:2301[40100009x_10630006x] add.f r2.y, r1.z, c24.w + :2:1328:2302[4030000cx_000e000cx] min.f r3.x, r3.x, r3.z + :2:1329:2303[40100000x_40000006x] add.f r0.x, r1.z, (neg)r0.x + :2:1330:2304[4010000fx_10630007x] add.f r3.w, r1.w, c24.w + :3:1331:2305[6382800dx_80011021x] mad.f32 r3.y, c8.y, r1.y, (neg)r0.y + :4:1332:2306[8030000ax_0000000ax] rsq r2.z, r2.z + :2:1333:2307[40100007x_400c0007x] add.f r1.w, r1.w, (neg)r3.x + :2:1334:2308[40700006x_00020002x] mul.f r1.z, r0.z, r0.z + :4:1335:2309[80100009x_00000009x] rcp r2.y, r2.y + :2:1336:2310[4010000bx_00010005x] add.f r2.w, r1.y, r0.y + :2:1337:2311[4010000dx_400e000dx] add.f r3.y, r3.y, (neg)r3.z + :2:1338:2312[40701010x_000a0001x] (ss)mul.f r4.x, r0.y, r2.z + :4:1339:2313[8010000cx_0000000fx] rcp r3.x, r3.w + :2:1340:2314[4070100fx_00090000x] (ss)mul.f r3.w, r0.x, r2.y + :2:1341:2315[4010000bx_000b000ex] add.f r2.w, r3.z, r2.w + :3:1342:2316[63840004x_800f0004x] mad.f32 r1.x, r1.x, r2.x, (neg)r3.w + :3:1343:2317[63868006x_0006000dx] mad.f32 r1.z, r3.y, r3.y, r1.z + :2:1344:2318[40700008x_000a0005x] mul.f r2.x, r1.y, r2.z + :2:1345:2319[4070000ax_000a000ex] mul.f r2.z, r3.z, r2.z + :2:1346:2320[40700803x_00040003x] (nop1) mul.f r0.w, r0.w, r1.x + :3:1347:2322[63848000x_00030000x] mad.f32 r0.x, r0.x, r2.y, r0.w + :3:1348:2323[63870003x_80011021x] mad.f32 r0.w, c8.y, r3.z, (neg)r0.y + :3:1349:2324[63860000x_80008007x] (nop2) mad.f32 r0.x, r1.w, r3.x, (neg)r0.x + :2:1350:2327[40180803x_40050003x] (nop3) add.f r0.w, r0.w, (neg)r1.y + :3:1351:2331[63818804x_00068003x] (nop3) mad.f32 r1.x, r0.w, r0.w, r1.z + :0:1352:2335[00000200x_00000000x] (rpt2)nop + :4:1353:2338[80300004x_00000004x] rsq r1.x, r1.x + :2:1354:2339[40701003x_00040003x] (ss)mul.f r0.w, r0.w, r1.x + :2:1355:2340[40700002x_00040002x] mul.f r0.z, r0.z, r1.x + :2:1356:2341[40780004x_0004000dx] (nop2) mul.f r1.x, r3.y, r1.x + :2:1357:2344[40700007x_00100002x] mul.f r1.w, r0.z, r4.x + :2:1358:2345[40700006x_00031020x] mul.f r1.z, c8.x, r0.w + :3:1359:2346[63840007x_00070004x] mad.f32 r1.w, r1.x, r2.x, r1.w + :2:1360:2347[40700002x_00021020x] mul.f r0.z, c8.x, r0.z + :2:1361:2348[40700004x_00041020x] mul.f r1.x, c8.x, r1.x + :2:1362:2349[40700006x_80000006x] mul.f r1.z, r1.z, (abs)r0.x + :3:1363:2350[63850003x_00070003x] mad.f32 r0.w, r0.w, r2.z, r1.w + :2:1364:2351[40700002x_80000002x] mul.f r0.z, r0.z, (abs)r0.x + :2:1365:2352[40700000x_80000004x] mul.f r0.x, r1.x, (abs)r0.x + :1:1366:2353[204cc007x_3f800000x] mov.u32u32 r1.w, 0x3f800000 + :2:1367:2354[40700004x_00030006x] mul.f r1.x, r1.z, r0.w + :2:1368:2355[40700002x_00030002x] mul.f r0.z, r0.z, r0.w + :2:1369:2356[40780000x_00030000x] (nop2) mul.f r0.x, r0.x, r0.w + :3:1370:2359[63858401x_00010002x] (sat)mad.f32 r0.y, r0.z, r2.w, r0.y + :3:1371:2360[63858403x_000e0004x] (sat)mad.f32 r0.w, r1.x, r2.w, r3.z + :3:1372:2361[63858400x_00050000x] (sat)mad.f32 r0.x, r0.x, r2.w, r1.y + :2:1373:2362[40100004x_40171022x] add.f r1.x, c8.z, (neg)r5.w + :2:1374:2363[40180805x_40131022x] (nop3) add.f r1.y, c8.z, (neg)r4.w + :4:1375:2367[80500002x_00000003x] log2 r0.z, r0.w + :4:1376:2368[80500001x_00000001x] log2 r0.y, r0.y + :0:1377:2369[00000000x_00000000x] nop + :4:1378:2370[80500000x_00000000x] log2 r0.x, r0.x + :2:1379:2371[40701003x_00131065x] (ss)mul.f r0.w, c25.y, r4.w + :2:1380:2372[40700002x_106c0002x] mul.f r0.z, r0.z, c27.x + :2:1381:2373[40700001x_106a0001x] mul.f r0.y, r0.y, c26.z + :2:1382:2374[40700000x_10640000x] mul.f r0.x, r0.x, c25.x + :2:1383:2375[40780803x_00170003x] (nop3) mul.f r0.w, r0.w, r5.w + :2:1384:2379[40700003x_00050003x] mul.f r0.w, r0.w, r1.y + :4:1385:2380[80700002x_00000002x] exp2 r0.z, r0.z + :4:1386:2381[80700001x_00000001x] exp2 r0.y, r0.y + :0:1387:2382[00000000x_00000000x] nop + :4:1388:2383[80700000x_00000000x] exp2 r0.x, r0.x + :2:1389:2384[40701802x_106d0002x] (ss)(nop1) mul.f r0.z, r0.z, c27.y + :2:1390:2386[40700003x_00040003x] mul.f r0.w, r0.w, r1.x + :2:1391:2387[40780801x_106b0001x] (nop3) mul.f r0.y, r0.y, c26.w + :0:1392:2391[00000100x_00000000x] (rpt1)nop + :4:1393:2393[80500003x_00000003x] log2 r0.w, r0.w + :2:1394:2394[40781803x_10680003x] (ss)(nop3) mul.f r0.w, r0.w, c26.x + :0:1395:2398[00000200x_00000000x] (rpt2)nop + :4:1396:2401[80700003x_00000003x] exp2 r0.w, r0.w + :3:1397:2402[63819803x_10509069x] (ss)(nop3) mad.f32 r0.w, c26.y, r0.w, c20.x + :2:1398:2406[40700006x_00030002x] mul.f r1.z, r0.z, r0.w + :2:1399:2407[40700005x_00030001x] mul.f r1.y, r0.y, r0.w + :2:1400:2408[40700004x_00030000x] mul.f r1.x, r0.x, r0.w + :0:1401:2409[03000000x_00000000x] end + :0:1402:2410[00000000x_00000000x] nop + :0:1403:2411[00000000x_00000000x] nop + :0:1404:2412[00000000x_00000000x] nop + :0:1405:2413[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-73 (cnt=74, max=73) + - used (merged): 0-147 (cnt=148, max=147) + - input (half): (cnt=0, max=0) + - input (full): 19-20 (cnt=2, max=20) + - const (half): (cnt=0, max=0) + - const (full): 0-1 3-5 8-9 32-113 (cnt=89, max=113) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 4-7 (cnt=4, max=7) (estimated) + - shaderdb: 2414 instructions, 1355 nops, 1059 non-nops, (1406 instlen), 0 half, 19 full + - shaderdb: 140 (ss), 0 (sy) +0000000001120158: 0000: 40a98302 01013000 00000000 +t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords) + { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 88 } + { EXT_SRC_ADDR = 0x1013000 } + { EXT_SRC_ADDR_HI = 0 } + :1:0000:0000[204cc000x_40400000x] mov.u32u32 r0.x, 0x40400000 + :1:0001:0001[204cc006x_00000000x] mov.u32u32 r1.z, 0x00000000 + :1:0002:0002[204cc004x_3e99999ax] mov.u32u32 r1.x, 0x3e99999a + :2:0003:0003[42700008x_20080014x] sub.s r2.x, r5.x, 8 + :3:0004:0004[6380000cx_10331003x] mad.f32 r3.x, c0.w, r0.x, c12.w + :1:0005:0005[200cc00dx_00000006x] mov.u32u32 r3.y, r1.z + :2:0006:0006[40700004x_00041003x] mul.f r1.x, c0.w, r1.x + :1:0007:0007[20244014x_00000000x] mov.f32f32 r5.x, c0.x + :2:0008:0008[4070000ex_1036000cx] mul.f r3.z, r3.x, c13.z + :1:0009:0009[200cc005x_0000000dx] mov.u32u32 r1.y, r3.y + :2:0010:0010[4070000fx_1034000cx] mul.f r3.w, r3.x, c13.x + :3:0011:0011[63820004x_10251024x] mad.f32 r1.x, c9.x, r1.x, c9.y + :3:0012:0012[6387000dx_10251024x] mad.f32 r3.y, c9.x, r3.z, c9.y + :3:0013:0013[6380000cx_800c1003x] mad.f32 r3.x, c0.w, r0.x, (neg)r3.x + :3:0014:0014[6387800ex_10251024x] mad.f32 r3.z, c9.x, r3.w, c9.y + :2:0015:0015[41300010x_00000004x] floor.f r4.x, r1.x + :2:0016:0016[41300011x_0000000dx] floor.f r4.y, r3.y + :1:0017:0017[200cc00fx_00000005x] mov.u32u32 r3.w, r1.y + :2:0018:0018[41300012x_0000000ex] floor.f r4.z, r3.z + :2:0019:0019[40100004x_40100004x] add.f r1.x, r1.x, (neg)r4.x + :2:0020:0020[4010000dx_4011000dx] add.f r3.y, r3.y, (neg)r4.y + :2:0021:0021[40700011x_00001003x] mul.f r4.y, c0.w, r0.x + :2:0022:0022[4010000ex_4012000ex] add.f r3.z, r3.z, (neg)r4.z + :3:0023:0023[63820004x_10261023x] mad.f32 r1.x, c8.w, r1.x, c9.z + :3:0024:0024[6386800dx_10261023x] mad.f32 r3.y, c8.w, r3.y, c9.z + :2:0025:0025[42700010x_20080013x] sub.s r4.x, r4.w, 8 + :3:0026:0026[6387000ex_10261023x] mad.f32 r3.z, c8.w, r3.z, c9.z + :2:0027:0027[4010001bx_40141066x] add.f r6.w, c25.z, (neg)r5.x + :2:0028:0028[40700016x_00141025x] mul.f r5.z, c9.y, r5.x + :4:0029:0029[80100014x_00000014x] rcp r5.x, r5.x + :2:0030:0030[46f00008x_20040008x] shr.b r2.x, r2.x, 4 + :4:0031:0031[80900000x_00000004x] sin r0.x, r1.x + :2:0032:0032[40101000x_10270000x] (ss)add.f r0.x, r0.x, c9.w + :4:0033:0033[80b00004x_0000000dx] cos r1.x, r3.y + :2:0034:0034[4078001bx_1025001bx] (nop2) mul.f r6.w, r6.w, c9.y + :2:0035:0037[40700400x_10280000x] (sat)mul.f r0.x, r0.x, c10.x + :4:0036:0038[8090100dx_0000000ex] (ss)sin r3.y, r3.z + :2:0037:0039[46f0100ex_20040010x] (ss)shr.b r3.z, r4.x, 4 + :2:0038:0040[40700010x_00041031x] mul.f r4.x, c12.y, r1.x + :1:0039:0041[200c4008x_00000008x] cov.u32f32 r2.x, r2.x + :2:0040:0042[40700012x_1021000dx] mul.f r4.z, r3.y, c8.y + :1:0041:0043[200c4004x_0000000ex] cov.u32f32 r1.x, r3.z + :2:0042:0044[4070000ex_00001021x] mul.f r3.z, c8.y, r0.x + :2:0043:0045[4070000dx_000d1031x] mul.f r3.y, c12.y, r3.y + :2:0044:0046[40100008x_10250008x] add.f r2.x, r2.x, c9.y + :2:0045:0047[40100013x_10250004x] add.f r4.w, r1.x, c9.y + :2:0046:0048[40180804x_400e1029x] (nop3) add.f r1.x, c10.y, (neg)r3.z + :2:0047:0052[40700004x_00040000x] mul.f r1.x, r0.x, r1.x + :2:0048:0053[40100017x_40160013x] add.f r5.w, r4.w, (neg)r5.z + :2:0049:0054[40100013x_401b0013x] add.f r4.w, r4.w, (neg)r6.w + :3:0050:0055[63840008x_10091008x] mad.f32 r2.x, c2.x, r2.x, c2.y + :2:0051:0056[4070000ex_00040000x] mul.f r3.z, r0.x, r1.x + :1:0052:0057[204cc004x_3fc00000x] mov.u32u32 r1.x, 0x3fc00000 + :1:0053:0058[200cc003x_0000000fx] mov.u32u32 r0.w, r3.w + :1:0054:0059[2024400fx_00000003x] mov.f32f32 r3.w, c0.w + :2:0055:0060[40700013x_00140013x] mul.f r4.w, r4.w, r5.x + :2:0056:0061[40100016x_40161004x] add.f r5.z, c1.x, (neg)r5.z + :1:0057:0062[200cc000x_00000003x] mov.u32u32 r0.x, r0.w + :3:0058:0063[6387801ax_10251024x] mad.f32 r6.z, c9.x, r3.w, c9.y + :2:0059:0064[40700019x_000f1032x] mul.f r6.y, c12.z, r3.w + :2:0060:0065[40700015x_000f1035x] mul.f r5.y, c13.y, r3.w + :1:0061:0066[200cc002x_00000000x] mov.u32u32 r0.z, r0.x + :2:0062:0067[4130001cx_0000001ax] floor.f r7.x, r6.z + :3:0063:0068[638c8019x_10251024x] mad.f32 r6.y, c9.x, r6.y, c9.y + :3:0064:0069[638a8015x_10251024x] mad.f32 r5.y, c9.x, r5.y, c9.y + :1:0065:0070[200cc000x_00000002x] mov.u32u32 r0.x, r0.z + :2:0066:0071[4018081ax_401c001ax] (nop3) add.f r6.z, r6.z, (neg)r7.x + :3:0067:0075[638d001ax_10261023x] mad.f32 r6.z, c8.w, r6.z, c9.z + :2:0068:0076[41300018x_00000015x] floor.f r6.x, r5.y + :1:0069:0077[200cc001x_00000000x] mov.u32u32 r0.y, r0.x + :0:0070:0078[00000300x_00000000x] (rpt3)nop + :4:0071:0082[80900014x_0000001ax] sin r5.x, r6.z + :2:0072:0083[4130101ax_00000019x] (ss)floor.f r6.z, r6.y + :2:0073:0084[40100015x_40180015x] add.f r5.y, r5.y, (neg)r6.x + :1:0074:0085[200cc000x_00000001x] mov.u32u32 r0.x, r0.y + :2:0075:0086[40700014x_10250014x] mul.f r5.x, r5.x, c9.y + :2:0076:0087[40100019x_401a0019x] add.f r6.y, r6.y, (neg)r6.z + :3:0077:0088[638a8015x_10269023x] (nop2) mad.f32 r5.y, c8.w, r5.y, c9.z + :3:0078:0091[638c8819x_10269023x] (nop3) mad.f32 r6.y, c8.w, r6.y, c9.z + :0:0079:0095[00000200x_00000000x] (rpt2)nop + :4:0080:0098[80900019x_00000019x] sin r6.y, r6.y + :4:0081:0099[80b00015x_00000015x] cos r5.y, r5.y + :3:0082:0100[638c9014x_00141031x] (ss)mad.f32 r5.x, c12.y, r6.y, r5.x + :3:0083:0101[638a8010x_80101031x] mad.f32 r4.x, c12.y, r5.y, (neg)r4.x + :2:0084:0102[40700815x_00151031x] (nop1) mul.f r5.y, c12.y, r5.y + :2:0085:0104[4010000dx_400d0014x] add.f r3.y, r5.x, (neg)r3.y + :2:0086:0105[40780018x_00100010x] (nop2) mul.f r6.x, r4.x, r4.x + :3:0087:0108[63868818x_0018000dx] (nop1) mad.f32 r6.x, r3.y, r3.y, r6.x + :3:0088:0110[63860818x_0018800cx] (nop3) mad.f32 r6.x, r3.x, r3.x, r6.x + :0:0089:0114[00000200x_00000000x] (rpt2)nop + :4:0090:0117[80300018x_00000018x] rsq r6.x, r6.x + :2:0091:0118[4070100cx_0018000cx] (ss)mul.f r3.x, r3.x, r6.x + :2:0092:0119[40700010x_00180010x] mul.f r4.x, r4.x, r6.x + :2:0093:0120[4070080dx_0018000dx] (nop1) mul.f r3.y, r3.y, r6.x + :2:0094:0122[40700818x_000c000cx] (nop1) mul.f r6.x, r3.x, r3.x + :3:0095:0124[63868818x_0018800dx] (nop3) mad.f32 r6.x, r3.y, r3.y, r6.x + :0:0096:0128[00000200x_00000000x] (rpt2)nop + :4:0097:0131[80300018x_00000018x] rsq r6.x, r6.x + :2:0098:0132[40701019x_0018000cx] (ss)mul.f r6.y, r3.x, r6.x + :2:0099:0133[40780018x_0018000dx] (nop2) mul.f r6.x, r3.y, r6.x + :2:0100:0136[4070001ax_000c0019x] mul.f r6.z, r6.y, r3.x + :2:0101:0137[40700019x_00100019x] mul.f r6.y, r6.y, r4.x + :3:0102:0138[6386801ax_001a0018x] mad.f32 r6.z, r6.x, r3.y, r6.z + :2:0103:0139[40780018x_00100018x] (nop2) mul.f r6.x, r6.x, r4.x + :2:0104:0142[4070081bx_001a001ax] (nop1) mul.f r6.w, r6.z, r6.z + :3:0105:0144[638c081bx_401b4018x] (nop1) mad.f32 r6.w, (neg)r6.x, (neg)r6.x, r6.w + :3:0106:0146[638c881bx_401bc019x] (nop3) mad.f32 r6.w, (neg)r6.y, (neg)r6.y, r6.w + :0:0107:0150[00000200x_00000000x] (rpt2)nop + :4:0108:0153[8030001bx_0000001bx] rsq r6.w, r6.w + :2:0109:0154[40701018x_001b0018x] (ss)mul.f r6.x, r6.x, r6.w + :2:0110:0155[4070001ax_001b001ax] mul.f r6.z, r6.z, r6.w + :2:0111:0156[40700819x_001b0019x] (nop1) mul.f r6.y, r6.y, r6.w + :2:0112:0158[4070001bx_000c0018x] mul.f r6.w, r6.x, r3.x + :2:0113:0159[4070001ex_000d001ax] mul.f r7.z, r6.z, r3.y + :2:0114:0160[4070001dx_00100019x] mul.f r7.y, r6.y, r4.x + :3:0115:0161[6386801bx_001b4019x] mad.f32 r6.w, (neg)r6.y, r3.y, r6.w + :3:0116:0162[6386001dx_001d001ax] mad.f32 r7.y, r6.z, r3.x, r7.y + :3:0117:0163[6388081ex_801e4018x] (nop1) mad.f32 r7.z, (neg)r6.x, r4.x, (neg)r7.z + :2:0118:0165[4070081cx_001b001bx] (nop1) mul.f r7.x, r6.w, r6.w + :3:0119:0167[638e881cx_001c001dx] (nop1) mad.f32 r7.x, r7.y, r7.y, r7.x + :3:0120:0169[638f081cx_001c801ex] (nop3) mad.f32 r7.x, r7.z, r7.z, r7.x + :0:0121:0173[00000200x_00000000x] (rpt2)nop + :4:0122:0176[8030001cx_0000001cx] rsq r7.x, r7.x + :2:0123:0177[4070101bx_001c001bx] (ss)mul.f r6.w, r6.w, r7.x + :2:0124:0178[4070001ex_001c001ex] mul.f r7.z, r7.z, r7.x + :2:0125:0179[4070001cx_001c001dx] mul.f r7.x, r7.y, r7.x + :1:0126:0180[2024401dx_00000001x] mov.f32f32 r7.y, c0.y + :0:0127:0181[00000200x_00000000x] (rpt2)nop + :2:0128:0184[4078001fx_001d1025x] (nop2) mul.f r7.w, c9.y, r7.y + :4:0129:0187[80100021x_0000001dx] rcp r8.y, r7.y + :2:0130:0188[4010101dx_401d1067x] (ss)add.f r7.y, c25.w, (neg)r7.y + :2:0131:0189[40100020x_401f0008x] add.f r8.x, r2.x, (neg)r7.w + :2:0132:0190[4010001fx_401f1005x] add.f r7.w, c1.y, (neg)r7.w + :2:0133:0191[40700017x_00210017x] mul.f r5.w, r5.w, r8.y + :2:0134:0192[4070001dx_1025001dx] mul.f r7.y, r7.y, c9.y + :2:0135:0193[40700020x_00210020x] mul.f r8.x, r8.x, r8.y + :2:0136:0194[40780016x_00210016x] (nop2) mul.f r5.z, r5.z, r8.y + :2:0137:0197[4070001ax_001a0020x] mul.f r6.z, r8.x, r6.z + :2:0138:0198[40700019x_00200019x] mul.f r6.y, r6.y, r8.x + :2:0139:0199[40700018x_00200018x] mul.f r6.x, r6.x, r8.x + :3:0140:0200[638d801ax_001a0017x] mad.f32 r6.z, r5.w, r6.w, r6.z + :3:0141:0201[638f0019x_80190017x] mad.f32 r6.y, r5.w, r7.z, (neg)r6.y + :3:0142:0202[638e0017x_80180017x] mad.f32 r5.w, r5.w, r7.x, (neg)r6.x + :2:0143:0203[40100008x_401d0008x] add.f r2.x, r2.x, (neg)r7.y + :2:0144:0204[40100010x_4010001ax] add.f r4.x, r6.z, (neg)r4.x + :3:0145:0205[63890012x_4016102dx] mad.f32 r4.z, c11.y, (neg)r4.z, r5.z + :2:0146:0206[4010000dx_400d0017x] add.f r3.y, r5.w, (neg)r3.y + :2:0147:0207[40700017x_00210008x] mul.f r5.w, r2.x, r8.y + :2:0148:0208[40700008x_10210016x] mul.f r2.x, r5.z, c8.y + :2:0149:0209[40700016x_00100010x] mul.f r5.z, r4.x, r4.x + :2:0150:0210[4010000cx_400c0019x] add.f r3.x, r6.y, (neg)r3.x + :3:0151:0211[63868016x_0016000dx] mad.f32 r5.z, r3.y, r3.y, r5.z + :2:0152:0212[40100014x_40080014x] add.f r5.x, r5.x, (neg)r2.x + :3:0153:0213[63890012x_10251024x] mad.f32 r4.z, c9.x, r4.z, c9.y + :3:0154:0214[63860808x_0016800cx] (nop3) mad.f32 r2.x, r3.x, r3.x, r5.z + :0:0155:0218[00000200x_00000000x] (rpt2)nop + :4:0156:0221[80300008x_00000008x] rsq r2.x, r2.x + :2:0157:0222[40701010x_00080010x] (ss)mul.f r4.x, r4.x, r2.x + :2:0158:0223[4070000cx_0008000cx] mul.f r3.x, r3.x, r2.x + :2:0159:0224[40700008x_0008000dx] mul.f r2.x, r3.y, r2.x + :2:0160:0225[4138080dx_00000012x] (nop3) floor.f r3.y, r4.z + :2:0161:0229[4018080dx_400d0012x] (nop3) add.f r3.y, r4.z, (neg)r3.y + :3:0162:0233[6386880dx_10269023x] (nop3) mad.f32 r3.y, c8.w, r3.y, c9.z + :0:0163:0237[00000200x_00000000x] (rpt2)nop + :4:0164:0240[80b00012x_0000000dx] cos r4.z, r3.y + :4:0165:0241[8090100dx_0000000dx] (ss)sin r3.y, r3.y + :2:0166:0242[40700816x_00120010x] (nop1) mul.f r5.z, r4.x, r4.z + :3:0167:0244[63869016x_40160008x] (ss)mad.f32 r5.z, r2.x, (neg)r3.y, r5.z + :2:0168:0245[4070080dx_000d0010x] (nop1) mul.f r3.y, r4.x, r3.y + :3:0169:0247[6389000dx_000d0008x] mad.f32 r3.y, r2.x, r4.z, r3.y + :1:0170:0248[280cc008x_00000006x] (jp)mov.u32u32 r2.x, r1.z + :0:0171:0249[00000200x_00000000x] (rpt2)nop + :2:0172:0252[42bb08f8x_20820008x] (nop3) cmps.s.ge p0.x, r2.x, 130 + :0:0173:0256[00000200x_00000000x] (rpt2)nop + :0:0174:0259[00800000x_00000464x] br p0.x, #1124 + :1:0175:0260[280cc008x_00000003x] (jp)mov.u32u32 r2.x, r0.w + :0:0176:0261[00000200x_00000000x] (rpt2)nop + :2:0177:0264[40b808f8x_0008106ex] (nop3) cmps.f.lt p0.x, c27.z, r2.x + :0:0178:0268[00000200x_00000000x] (rpt2)nop + :0:0179:0271[00800000x_0000045fx] br p0.x, #1119 + :1:0180:0272[280cc012x_00000004x] (jp)mov.u32u32 r4.z, r1.x + :1:0181:0273[200cc018x_00000004x] mov.u32u32 r6.x, r1.x + :1:0182:0274[200cc019x_00000004x] mov.u32u32 r6.y, r1.x + :3:0183:0275[63870010x_1037102ax] mad.f32 r4.x, c10.z, r3.z, c13.w + :3:0184:0276[63868012x_00140012x] mad.f32 r4.z, r4.z, r3.y, r5.x + :3:0185:0277[638b0018x_00150018x] mad.f32 r6.x, r6.x, r5.z, r5.y + :3:0186:0278[63860019x_00110019x] mad.f32 r6.y, r6.y, r3.x, r4.y + :3:0187:0279[63870008x_1037902dx] (nop2) mad.f32 r2.x, c11.y, r3.z, c13.w + :2:0188:0282[4070001cx_10360019x] mul.f r7.x, r6.y, c13.z + :2:0189:0283[4010001ax_10030019x] add.f r6.z, r6.y, c0.w + :2:0190:0284[4070001dx_10340019x] mul.f r7.y, r6.y, c13.x + :2:0191:0285[4070001bx_10380019x] mul.f r6.w, r6.y, c14.x + :3:0192:0286[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :3:0193:0287[638d001ax_10251024x] mad.f32 r6.z, c9.x, r6.z, c9.y + :3:0194:0288[638e881dx_10251024x] (nop1) mad.f32 r7.y, c9.x, r7.y, c9.y + :2:0195:0290[41300020x_0000001cx] floor.f r8.x, r7.x + :2:0196:0291[4130001ex_0000001ax] floor.f r7.z, r6.z + :2:0197:0292[41300822x_0000001dx] (nop1) floor.f r8.z, r7.y + :2:0198:0294[4010001cx_4020001cx] add.f r7.x, r7.x, (neg)r8.x + :2:0199:0295[4010001ax_401e001ax] add.f r6.z, r6.z, (neg)r7.z + :2:0200:0296[4010001dx_4022001dx] add.f r7.y, r7.y, (neg)r8.z + :1:0201:0297[204cc01ex_3f4ccccdx] mov.u32u32 r7.z, 0x3f4ccccd + :3:0202:0298[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :3:0203:0299[638d001ax_10261023x] mad.f32 r6.z, c8.w, r6.z, c9.z + :3:0204:0300[638e801dx_10261023x] mad.f32 r7.y, c8.w, r7.y, c9.z + :2:0205:0301[4070001ex_001e1003x] mul.f r7.z, c0.w, r7.z + :2:0206:0302[40700022x_000f104ax] mul.f r8.z, c18.z, r3.w + :3:0207:0303[638d801bx_001e1039x] mad.f32 r6.w, c14.y, r6.w, r7.z + :2:0208:0304[40700020x_000f104dx] mul.f r8.x, c19.y, r3.w + :4:0209:0305[80b0001cx_0000001cx] cos r7.x, r7.x + :2:0210:0306[4070101cx_1021001cx] (ss)mul.f r7.x, r7.x, c8.y + :4:0211:0307[8090001ax_0000001ax] sin r6.z, r6.z + :0:0212:0308[00000000x_00000000x] nop + :4:0213:0309[8090001dx_0000001dx] sin r7.y, r7.y + :3:0214:0310[638d881bx_10251024x] (nop1) mad.f32 r6.w, c9.x, r6.w, c9.y + :2:0215:0312[4010001cx_401c0018x] add.f r7.x, r6.x, (neg)r7.x + :2:0216:0313[4078101dx_1021001dx] (ss)(nop2) mul.f r7.y, r7.y, c8.y + :2:0217:0316[4070001cx_001c001cx] mul.f r7.x, r7.x, r7.x + :2:0218:0317[4018081dx_401d0012x] (nop3) add.f r7.y, r4.z, (neg)r7.y + :3:0219:0321[638e801cx_001c001dx] mad.f32 r7.x, r7.y, r7.y, r7.x + :1:0220:0322[204cc01dx_3db851ecx] mov.u32u32 r7.y, 0x3db851ec + :0:0221:0323[00000200x_00000000x] (rpt2)nop + :2:0222:0326[4070081dx_001d1003x] (nop1) mul.f r7.y, c0.w, r7.y + :3:0223:0328[6388081ax_001d801ax] (nop3) mad.f32 r6.z, r6.z, r4.x, r7.y + :3:0224:0332[638d081ax_10259024x] (nop3) mad.f32 r6.z, c9.x, r6.z, c9.y + :2:0225:0336[41380823x_0000001ax] (nop3) floor.f r8.w, r6.z + :2:0226:0340[4018081ax_4023001ax] (nop3) add.f r6.z, r6.z, (neg)r8.w + :3:0227:0344[638d081ax_10269023x] (nop3) mad.f32 r6.z, c8.w, r6.z, c9.z + :0:0228:0348[00000200x_00000000x] (rpt2)nop + :4:0229:0351[80900023x_0000001ax] sin r8.w, r6.z + :4:0230:0352[80b0101ax_0000001ax] (ss)cos r6.z, r6.z + :2:0231:0353[40700824x_00230018x] (nop1) mul.f r9.x, r6.x, r8.w + :3:0232:0355[638d1024x_00240012x] (ss)mad.f32 r9.x, r4.z, r6.z, r9.x + :2:0233:0356[4070081ax_001a0018x] (nop1) mul.f r6.z, r6.x, r6.z + :3:0234:0358[6391801ax_401a0012x] mad.f32 r6.z, r4.z, (neg)r8.w, r6.z + :2:0235:0359[40780023x_10380024x] (nop2) mul.f r8.w, r9.x, c14.x + :2:0236:0362[40700025x_1038001ax] mul.f r9.y, r6.z, c14.x + :3:0237:0363[63918023x_001e9039x] (nop2) mad.f32 r8.w, c14.y, r8.w, r7.z + :3:0238:0366[63928025x_001e1039x] mad.f32 r9.y, c14.y, r9.y, r7.z + :3:0239:0367[63918023x_10259024x] (nop2) mad.f32 r8.w, c9.x, r8.w, c9.y + :3:0240:0370[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :2:0241:0371[41380026x_00000023x] (nop2) floor.f r9.z, r8.w + :2:0242:0374[41300027x_00000025x] floor.f r9.w, r9.y + :2:0243:0375[40180023x_40260023x] (nop2) add.f r8.w, r8.w, (neg)r9.z + :2:0244:0378[40100025x_40270025x] add.f r9.y, r9.y, (neg)r9.w + :3:0245:0379[63918023x_10269023x] (nop2) mad.f32 r8.w, c8.w, r8.w, c9.z + :3:0246:0382[63928825x_10269023x] (nop3) mad.f32 r9.y, c8.w, r9.y, c9.z + :0:0247:0386[00000200x_00000000x] (rpt2)nop + :4:0248:0389[80900025x_00000025x] sin r9.y, r9.y + :4:0249:0390[80900023x_00000023x] sin r8.w, r8.w + :2:0250:0391[40701823x_00080023x] (ss)(nop1) mul.f r8.w, r8.w, r2.x + :3:0251:0393[638d001ax_00231038x] mad.f32 r6.z, c14.x, r6.z, r8.w + :2:0252:0394[40780023x_00080025x] (nop2) mul.f r8.w, r9.y, r2.x + :2:0253:0397[40700026x_103b001ax] mul.f r9.z, r6.z, c14.w + :2:0254:0398[40700027x_103f001ax] mul.f r9.w, r6.z, c15.w + :3:0255:0399[638c8023x_00231038x] mad.f32 r8.w, c14.x, r6.y, r8.w + :2:0256:0400[40700025x_1042001ax] mul.f r9.y, r6.z, c16.z + :3:0257:0401[638d081ax_10251024x] (nop1) mad.f32 r6.z, c9.x, r6.z, c9.y + :3:0258:0403[63918828x_10251024x] (nop1) mad.f32 r10.x, c9.x, r8.w, c9.y + :2:0259:0405[41300829x_0000001ax] (nop1) floor.f r10.y, r6.z + :2:0260:0407[4130082ax_00000028x] (nop1) floor.f r10.z, r10.x + :2:0261:0409[4010081ax_4029001ax] (nop1) add.f r6.z, r6.z, (neg)r10.y + :2:0262:0411[40100828x_402a0028x] (nop1) add.f r10.x, r10.x, (neg)r10.z + :3:0263:0413[638d081ax_10261023x] (nop1) mad.f32 r6.z, c8.w, r6.z, c9.z + :3:0264:0415[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0265:0419[00000000x_00000000x] nop + :4:0266:0420[80b00029x_0000001ax] cos r10.y, r6.z + :4:0267:0421[8090101ax_0000001ax] (ss)sin r6.z, r6.z + :0:0268:0422[00000100x_00000000x] (rpt1)nop + :4:0269:0424[8090002ax_00000028x] sin r10.z, r10.x + :4:0270:0425[80b01028x_00000028x] (ss)cos r10.x, r10.x + :2:0271:0426[40700029x_002a0029x] mul.f r10.y, r10.y, r10.z + :2:0272:0427[4138082ax_0000001bx] (nop3) floor.f r10.z, r6.w + :2:0273:0431[4018081bx_402a001bx] (nop3) add.f r6.w, r6.w, (neg)r10.z + :3:0274:0435[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:0275:0439[00000200x_00000000x] (rpt2)nop + :4:0276:0442[8090001bx_0000001bx] sin r6.w, r6.w + :2:0277:0443[4070181bx_0008001bx] (ss)(nop1) mul.f r6.w, r6.w, r2.x + :3:0278:0445[6392081bx_001b9038x] (nop3) mad.f32 r6.w, c14.x, r9.x, r6.w + :3:0279:0449[638d8024x_00251043x] mad.f32 r9.x, c16.w, r6.w, r9.y + :3:0280:0450[638d8025x_0026103cx] mad.f32 r9.y, c15.x, r6.w, r9.z + :3:0281:0451[63918024x_00241044x] mad.f32 r9.x, c17.x, r8.w, r9.x + :3:0282:0452[63918025x_0025103dx] mad.f32 r9.y, c15.y, r8.w, r9.y + :3:0283:0453[638d8026x_00271040x] mad.f32 r9.z, c16.x, r6.w, r9.w + :3:0284:0454[638d801bx_10251024x] mad.f32 r6.w, c9.x, r6.w, c9.y + :3:0285:0455[63918023x_00269041x] (nop2) mad.f32 r8.w, c16.y, r8.w, r9.z + :2:0286:0458[41380826x_0000001bx] (nop3) floor.f r9.z, r6.w + :2:0287:0462[4018081bx_4026001bx] (nop3) add.f r6.w, r6.w, (neg)r9.z + :3:0288:0466[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:0289:0470[00000200x_00000000x] (rpt2)nop + :4:0290:0473[80b00026x_0000001bx] cos r9.z, r6.w + :4:0291:0474[8090101bx_0000001bx] (ss)sin r6.w, r6.w + :3:0292:0475[638d081ax_00290026x] (nop1) mad.f32 r6.z, r9.z, r6.z, r10.y + :3:0293:0477[638d901ax_001a0028x] (ss)mad.f32 r6.z, r10.x, r6.w, r6.z + :2:0294:0478[4070081bx_000f103ex] (nop1) mul.f r6.w, c15.z, r3.w + :3:0295:0480[63920026x_001b103ax] mad.f32 r9.z, c14.z, r9.x, r6.w + :3:0296:0481[63928027x_001b103ax] mad.f32 r9.w, c14.z, r9.y, r6.w + :3:0297:0482[63918828x_001b103ax] (nop1) mad.f32 r10.x, c14.z, r8.w, r6.w + :3:0298:0484[63930026x_10251024x] mad.f32 r9.z, c9.x, r9.z, c9.y + :3:0299:0485[63938027x_10251024x] mad.f32 r9.w, c9.x, r9.w, c9.y + :3:0300:0486[63940828x_10251024x] (nop1) mad.f32 r10.x, c9.x, r10.x, c9.y + :2:0301:0488[41300029x_00000026x] floor.f r10.y, r9.z + :2:0302:0489[4138002ax_00000027x] (nop2) floor.f r10.z, r9.w + :2:0303:0492[40100026x_40290026x] add.f r9.z, r9.z, (neg)r10.y + :2:0304:0493[40180027x_402a0027x] (nop2) add.f r9.w, r9.w, (neg)r10.z + :3:0305:0496[63930026x_10261023x] mad.f32 r9.z, c8.w, r9.z, c9.z + :3:0306:0497[63938827x_10269023x] (nop3) mad.f32 r9.w, c8.w, r9.w, c9.z + :0:0307:0501[00000100x_00000000x] (rpt1)nop + :4:0308:0503[80900026x_00000026x] sin r9.z, r9.z + :3:0309:0504[63841025x_00250026x] (ss)mad.f32 r9.y, r9.z, r2.x, r9.y + :4:0310:0505[80900027x_00000027x] sin r9.w, r9.w + :3:0311:0506[63841023x_00238027x] (ss)(nop2) mad.f32 r8.w, r9.w, r2.x, r8.w + :2:0312:0509[40700026x_10420025x] mul.f r9.z, r9.y, c16.z + :2:0313:0510[40700029x_103f0025x] mul.f r10.y, r9.y, c15.w + :2:0314:0511[40700027x_103b0025x] mul.f r9.w, r9.y, c14.w + :3:0315:0512[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :3:0316:0513[6391802ax_10259024x] (nop2) mad.f32 r10.z, c9.x, r8.w, c9.y + :2:0317:0516[4130002bx_00000025x] floor.f r10.w, r9.y + :2:0318:0517[4138002cx_0000002ax] (nop2) floor.f r11.x, r10.z + :2:0319:0520[40100025x_402b0025x] add.f r9.y, r9.y, (neg)r10.w + :2:0320:0521[4018002ax_402c002ax] (nop2) add.f r10.z, r10.z, (neg)r11.x + :3:0321:0524[63928025x_10261023x] mad.f32 r9.y, c8.w, r9.y, c9.z + :3:0322:0525[6395082ax_10269023x] (nop3) mad.f32 r10.z, c8.w, r10.z, c9.z + :0:0323:0529[00000100x_00000000x] (rpt1)nop + :4:0324:0531[80b0002bx_00000025x] cos r10.w, r9.y + :4:0325:0532[80901025x_00000025x] (ss)sin r9.y, r9.y + :0:0326:0533[00000000x_00000000x] nop + :4:0327:0534[8090002cx_0000002ax] sin r11.x, r10.z + :4:0328:0535[80b0102ax_0000002ax] (ss)cos r10.z, r10.z + :2:0329:0536[4070002bx_002c002bx] mul.f r10.w, r10.w, r11.x + :2:0330:0537[4138082cx_00000028x] (nop3) floor.f r11.x, r10.x + :2:0331:0541[40180828x_402c0028x] (nop3) add.f r10.x, r10.x, (neg)r11.x + :3:0332:0545[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0333:0549[00000200x_00000000x] (rpt2)nop + :4:0334:0552[80900028x_00000028x] sin r10.x, r10.x + :3:0335:0553[63841824x_00248028x] (ss)(nop3) mad.f32 r9.x, r10.x, r2.x, r9.x + :3:0336:0557[63920026x_00261043x] mad.f32 r9.z, c16.w, r9.x, r9.z + :3:0337:0558[63920027x_0027103cx] mad.f32 r9.w, c15.x, r9.x, r9.w + :3:0338:0559[63920028x_00291040x] mad.f32 r10.x, c16.x, r9.x, r10.y + :3:0339:0560[63920024x_10251024x] mad.f32 r9.x, c9.x, r9.x, c9.y + :3:0340:0561[63918026x_00261044x] mad.f32 r9.z, c17.x, r8.w, r9.z + :3:0341:0562[63918027x_0027103dx] mad.f32 r9.w, c15.y, r8.w, r9.w + :3:0342:0563[63918023x_00281041x] mad.f32 r8.w, c16.y, r8.w, r10.x + :2:0343:0564[41380828x_00000024x] (nop3) floor.f r10.x, r9.x + :2:0344:0568[40180824x_40280024x] (nop3) add.f r9.x, r9.x, (neg)r10.x + :3:0345:0572[63920824x_10269023x] (nop3) mad.f32 r9.x, c8.w, r9.x, c9.z + :0:0346:0576[00000200x_00000000x] (rpt2)nop + :4:0347:0579[80b00028x_00000024x] cos r10.x, r9.x + :4:0348:0580[80901024x_00000024x] (ss)sin r9.x, r9.x + :3:0349:0581[63928825x_002b0028x] (nop1) mad.f32 r9.y, r10.x, r9.y, r10.w + :3:0350:0583[63921824x_0025802ax] (ss)(nop3) mad.f32 r9.x, r10.z, r9.x, r9.y + :2:0351:0587[40780824x_10450024x] (nop3) mul.f r9.x, r9.x, c17.y + :2:0352:0591[4010001ax_c024c01ax] add.f r6.z, (absneg)r6.z, (absneg)r9.x + :2:0353:0592[40700824x_000f1047x] (nop1) mul.f r9.x, c17.w, r3.w + :3:0354:0594[63930025x_00241046x] mad.f32 r9.y, c17.z, r9.z, r9.x + :3:0355:0595[63938028x_00241046x] mad.f32 r10.x, c17.z, r9.w, r9.x + :3:0356:0596[63918829x_00241046x] (nop1) mad.f32 r10.y, c17.z, r8.w, r9.x + :3:0357:0598[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :3:0358:0599[63940028x_10251024x] mad.f32 r10.x, c9.x, r10.x, c9.y + :3:0359:0600[63948829x_10251024x] (nop1) mad.f32 r10.y, c9.x, r10.y, c9.y + :2:0360:0602[4130002ax_00000025x] floor.f r10.z, r9.y + :2:0361:0603[4138002bx_00000028x] (nop2) floor.f r10.w, r10.x + :2:0362:0606[40100025x_402a0025x] add.f r9.y, r9.y, (neg)r10.z + :2:0363:0607[40180028x_402b0028x] (nop2) add.f r10.x, r10.x, (neg)r10.w + :3:0364:0610[63928025x_10261023x] mad.f32 r9.y, c8.w, r9.y, c9.z + :3:0365:0611[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0366:0615[00000100x_00000000x] (rpt1)nop + :4:0367:0617[80900025x_00000025x] sin r9.y, r9.y + :3:0368:0618[63841025x_00270025x] (ss)mad.f32 r9.y, r9.y, r2.x, r9.w + :4:0369:0619[80900028x_00000028x] sin r10.x, r10.x + :3:0370:0620[63841023x_00238028x] (ss)(nop2) mad.f32 r8.w, r10.x, r2.x, r8.w + :2:0371:0623[40700027x_10420025x] mul.f r9.w, r9.y, c16.z + :2:0372:0624[4070002ax_103f0025x] mul.f r10.z, r9.y, c15.w + :2:0373:0625[40700028x_103b0025x] mul.f r10.x, r9.y, c14.w + :3:0374:0626[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :3:0375:0627[6391802bx_10259024x] (nop2) mad.f32 r10.w, c9.x, r8.w, c9.y + :2:0376:0630[4130002cx_00000025x] floor.f r11.x, r9.y + :2:0377:0631[4138002dx_0000002bx] (nop2) floor.f r11.y, r10.w + :2:0378:0634[40100025x_402c0025x] add.f r9.y, r9.y, (neg)r11.x + :2:0379:0635[4018002bx_402d002bx] (nop2) add.f r10.w, r10.w, (neg)r11.y + :3:0380:0638[63928025x_10261023x] mad.f32 r9.y, c8.w, r9.y, c9.z + :3:0381:0639[6395882bx_10269023x] (nop3) mad.f32 r10.w, c8.w, r10.w, c9.z + :0:0382:0643[00000100x_00000000x] (rpt1)nop + :4:0383:0645[80b0002cx_00000025x] cos r11.x, r9.y + :4:0384:0646[80901025x_00000025x] (ss)sin r9.y, r9.y + :0:0385:0647[00000000x_00000000x] nop + :4:0386:0648[8090002dx_0000002bx] sin r11.y, r10.w + :4:0387:0649[80b0102bx_0000002bx] (ss)cos r10.w, r10.w + :2:0388:0650[4070002cx_002d002cx] mul.f r11.x, r11.x, r11.y + :2:0389:0651[4138082dx_00000029x] (nop3) floor.f r11.y, r10.y + :2:0390:0655[40180829x_402d0029x] (nop3) add.f r10.y, r10.y, (neg)r11.y + :3:0391:0659[63948829x_10269023x] (nop3) mad.f32 r10.y, c8.w, r10.y, c9.z + :0:0392:0663[00000200x_00000000x] (rpt2)nop + :4:0393:0666[80900029x_00000029x] sin r10.y, r10.y + :3:0394:0667[63841826x_00268029x] (ss)(nop3) mad.f32 r9.z, r10.y, r2.x, r9.z + :3:0395:0671[63930027x_00271043x] mad.f32 r9.w, c16.w, r9.z, r9.w + :3:0396:0672[63930028x_0028103cx] mad.f32 r10.x, c15.x, r9.z, r10.x + :3:0397:0673[63930029x_002a1040x] mad.f32 r10.y, c16.x, r9.z, r10.z + :3:0398:0674[63918027x_00271044x] mad.f32 r9.w, c17.x, r8.w, r9.w + :3:0399:0675[63918028x_0028103dx] mad.f32 r10.x, c15.y, r8.w, r10.x + :3:0400:0676[63918023x_00291041x] mad.f32 r8.w, c16.y, r8.w, r10.y + :3:0401:0677[63930026x_10251024x] mad.f32 r9.z, c9.x, r9.z, c9.y + :3:0402:0678[63938029x_00221049x] mad.f32 r10.y, c18.y, r9.w, r8.z + :3:0403:0679[6394002ax_00221049x] mad.f32 r10.z, c18.y, r10.x, r8.z + :3:0404:0680[6391882dx_00221049x] (nop1) mad.f32 r11.y, c18.y, r8.w, r8.z + :3:0405:0682[63948029x_10251024x] mad.f32 r10.y, c9.x, r10.y, c9.y + :3:0406:0683[6395002ax_10251024x] mad.f32 r10.z, c9.x, r10.z, c9.y + :3:0407:0684[6396882dx_10251024x] (nop1) mad.f32 r11.y, c9.x, r11.y, c9.y + :2:0408:0686[4130002ex_00000029x] floor.f r11.z, r10.y + :2:0409:0687[4138002fx_0000002ax] (nop2) floor.f r11.w, r10.z + :2:0410:0690[40100029x_402e0029x] add.f r10.y, r10.y, (neg)r11.z + :2:0411:0691[4018002ax_402f002ax] (nop2) add.f r10.z, r10.z, (neg)r11.w + :3:0412:0694[63948029x_10261023x] mad.f32 r10.y, c8.w, r10.y, c9.z + :3:0413:0695[6395082ax_10269023x] (nop3) mad.f32 r10.z, c8.w, r10.z, c9.z + :0:0414:0699[00000100x_00000000x] (rpt1)nop + :4:0415:0701[80900029x_00000029x] sin r10.y, r10.y + :3:0416:0702[63841028x_00280029x] (ss)mad.f32 r10.x, r10.y, r2.x, r10.x + :4:0417:0703[8090002ax_0000002ax] sin r10.z, r10.z + :3:0418:0704[63841023x_0023802ax] (ss)(nop2) mad.f32 r8.w, r10.z, r2.x, r8.w + :2:0419:0707[40700029x_10420028x] mul.f r10.y, r10.x, c16.z + :2:0420:0708[4070002ex_103f0028x] mul.f r11.z, r10.x, c15.w + :3:0421:0709[6391802fx_10251024x] mad.f32 r11.w, c9.x, r8.w, c9.y + :2:0422:0710[4070002ax_103b0028x] mul.f r10.z, r10.x, c14.w + :3:0423:0711[63940828x_10251024x] (nop1) mad.f32 r10.x, c9.x, r10.x, c9.y + :2:0424:0713[41300831x_0000002fx] (nop1) floor.f r12.y, r11.w + :2:0425:0715[41300830x_00000028x] (nop1) floor.f r12.x, r10.x + :2:0426:0717[4010082fx_4031002fx] (nop1) add.f r11.w, r11.w, (neg)r12.y + :2:0427:0719[40100828x_40300028x] (nop1) add.f r10.x, r10.x, (neg)r12.x + :3:0428:0721[6397882fx_10261023x] (nop1) mad.f32 r11.w, c8.w, r11.w, c9.z + :3:0429:0723[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0430:0727[00000000x_00000000x] nop + :4:0431:0728[80900031x_0000002fx] sin r12.y, r11.w + :4:0432:0729[80b0102fx_0000002fx] (ss)cos r11.w, r11.w + :0:0433:0730[00000100x_00000000x] (rpt1)nop + :4:0434:0732[80b00030x_00000028x] cos r12.x, r10.x + :4:0435:0733[80901028x_00000028x] (ss)sin r10.x, r10.x + :2:0436:0734[40700030x_00310030x] mul.f r12.x, r12.x, r12.y + :2:0437:0735[41380831x_0000002dx] (nop3) floor.f r12.y, r11.y + :2:0438:0739[4018082dx_4031002dx] (nop3) add.f r11.y, r11.y, (neg)r12.y + :3:0439:0743[6396882dx_10269023x] (nop3) mad.f32 r11.y, c8.w, r11.y, c9.z + :0:0440:0747[00000200x_00000000x] (rpt2)nop + :4:0441:0750[8090002dx_0000002dx] sin r11.y, r11.y + :3:0442:0751[63841827x_0027802dx] (ss)(nop3) mad.f32 r9.w, r11.y, r2.x, r9.w + :3:0443:0755[63938029x_00291043x] mad.f32 r10.y, c16.w, r9.w, r10.y + :3:0444:0756[6393802ax_002a103cx] mad.f32 r10.z, c15.x, r9.w, r10.z + :3:0445:0757[6393802dx_002e1040x] mad.f32 r11.y, c16.x, r9.w, r11.z + :3:0446:0758[63918029x_00291044x] mad.f32 r10.y, c17.x, r8.w, r10.y + :3:0447:0759[6391802ax_002a103dx] mad.f32 r10.z, c15.y, r8.w, r10.z + :3:0448:0760[63918023x_002d1041x] mad.f32 r8.w, c16.y, r8.w, r11.y + :3:0449:0761[63938027x_10251024x] mad.f32 r9.w, c9.x, r9.w, c9.y + :3:0450:0762[6394802dx_0020104cx] mad.f32 r11.y, c19.x, r10.y, r8.x + :3:0451:0763[6395002ex_0020104cx] mad.f32 r11.z, c19.x, r10.z, r8.x + :3:0452:0764[63918831x_0020104cx] (nop1) mad.f32 r12.y, c19.x, r8.w, r8.x + :3:0453:0766[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :3:0454:0767[6397002ex_10251024x] mad.f32 r11.z, c9.x, r11.z, c9.y + :3:0455:0768[63988831x_10251024x] (nop1) mad.f32 r12.y, c9.x, r12.y, c9.y + :2:0456:0770[41300032x_0000002dx] floor.f r12.z, r11.y + :2:0457:0771[41380033x_0000002ex] (nop2) floor.f r12.w, r11.z + :2:0458:0774[4010002dx_4032002dx] add.f r11.y, r11.y, (neg)r12.z + :2:0459:0775[4018002ex_4033002ex] (nop2) add.f r11.z, r11.z, (neg)r12.w + :3:0460:0778[6396802dx_10261023x] mad.f32 r11.y, c8.w, r11.y, c9.z + :3:0461:0779[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:0462:0783[00000100x_00000000x] (rpt1)nop + :4:0463:0785[8090002dx_0000002dx] sin r11.y, r11.y + :3:0464:0786[6384102ax_002a002dx] (ss)mad.f32 r10.z, r11.y, r2.x, r10.z + :4:0465:0787[8090002ex_0000002ex] sin r11.z, r11.z + :3:0466:0788[63841023x_0023802ex] (ss)(nop2) mad.f32 r8.w, r11.z, r2.x, r8.w + :3:0467:0791[6395002ax_10251024x] mad.f32 r10.z, c9.x, r10.z, c9.y + :3:0468:0792[63918023x_10259024x] (nop2) mad.f32 r8.w, c9.x, r8.w, c9.y + :2:0469:0795[4130002dx_0000002ax] floor.f r11.y, r10.z + :2:0470:0796[4138002ex_00000023x] (nop2) floor.f r11.z, r8.w + :2:0471:0799[4010002ax_402d002ax] add.f r10.z, r10.z, (neg)r11.y + :2:0472:0800[40180023x_402e0023x] (nop2) add.f r8.w, r8.w, (neg)r11.z + :3:0473:0803[6395002ax_10261023x] mad.f32 r10.z, c8.w, r10.z, c9.z + :3:0474:0804[63918823x_10269023x] (nop3) mad.f32 r8.w, c8.w, r8.w, c9.z + :0:0475:0808[00000100x_00000000x] (rpt1)nop + :4:0476:0810[80b0002dx_0000002ax] cos r11.y, r10.z + :4:0477:0811[8090102ax_0000002ax] (ss)sin r10.z, r10.z + :0:0478:0812[00000000x_00000000x] nop + :4:0479:0813[8090002ex_00000023x] sin r11.z, r8.w + :4:0480:0814[80b01023x_00000023x] (ss)cos r8.w, r8.w + :2:0481:0815[4070002dx_002e002dx] mul.f r11.y, r11.y, r11.z + :2:0482:0816[4138082ex_00000031x] (nop3) floor.f r11.z, r12.y + :2:0483:0820[4018082ex_402e0031x] (nop3) add.f r11.z, r12.y, (neg)r11.z + :3:0484:0824[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:0485:0828[00000200x_00000000x] (rpt2)nop + :4:0486:0831[8090002ex_0000002ex] sin r11.z, r11.z + :3:0487:0832[63841829x_0029802ex] (ss)(nop3) mad.f32 r10.y, r11.z, r2.x, r10.y + :3:0488:0836[63948829x_10259024x] (nop3) mad.f32 r10.y, c9.x, r10.y, c9.y + :2:0489:0840[4138082ex_00000029x] (nop3) floor.f r11.z, r10.y + :2:0490:0844[40180829x_402e0029x] (nop3) add.f r10.y, r10.y, (neg)r11.z + :3:0491:0848[63948829x_10269023x] (nop3) mad.f32 r10.y, c8.w, r10.y, c9.z + :0:0492:0852[00000200x_00000000x] (rpt2)nop + :4:0493:0855[80b0002ex_00000029x] cos r11.z, r10.y + :4:0494:0856[80901029x_00000029x] (ss)sin r10.y, r10.y + :3:0495:0857[6395082ax_002d002ex] (nop1) mad.f32 r10.z, r11.z, r10.z, r11.y + :3:0496:0859[63949023x_002a0023x] (ss)mad.f32 r8.w, r8.w, r10.y, r10.z + :2:0497:0860[41380829x_00000027x] (nop3) floor.f r10.y, r9.w + :2:0498:0864[40100027x_40290027x] add.f r9.w, r9.w, (neg)r10.y + :2:0499:0865[40780023x_104e0023x] (nop2) mul.f r8.w, r8.w, c19.z + :3:0500:0868[63938827x_10269023x] (nop3) mad.f32 r9.w, c8.w, r9.w, c9.z + :0:0501:0872[00000200x_00000000x] (rpt2)nop + :4:0502:0875[80b00029x_00000027x] cos r10.y, r9.w + :4:0503:0876[80901027x_00000027x] (ss)sin r9.w, r9.w + :3:0504:0877[63940828x_00300029x] (nop1) mad.f32 r10.x, r10.y, r10.x, r12.x + :3:0505:0879[63939027x_0028002fx] (ss)mad.f32 r9.w, r11.w, r9.w, r10.x + :2:0506:0880[41380828x_00000026x] (nop3) floor.f r10.x, r9.z + :2:0507:0884[40100026x_40280026x] add.f r9.z, r9.z, (neg)r10.x + :2:0508:0885[40780027x_104b0027x] (nop2) mul.f r9.w, r9.w, c18.w + :3:0509:0888[63930826x_10269023x] (nop3) mad.f32 r9.z, c8.w, r9.z, c9.z + :0:0510:0892[00000200x_00000000x] (rpt2)nop + :4:0511:0895[80b00028x_00000026x] cos r10.x, r9.z + :4:0512:0896[80901026x_00000026x] (ss)sin r9.z, r9.z + :3:0513:0897[63928825x_002c0028x] (nop1) mad.f32 r9.y, r10.x, r9.y, r11.x + :3:0514:0899[63931825x_0025802bx] (ss)(nop3) mad.f32 r9.y, r10.w, r9.z, r9.y + :2:0515:0903[40780825x_10480025x] (nop3) mul.f r9.y, r9.y, c18.x + :2:0516:0907[4018081ax_c025001ax] (nop3) add.f r6.z, r6.z, (absneg)r9.y + :2:0517:0911[4018081ax_c027001ax] (nop3) add.f r6.z, r6.z, (absneg)r9.w + :2:0518:0915[4010081ax_c023001ax] (nop1) add.f r6.z, r6.z, (absneg)r8.w + :3:0519:0917[6387081ax_001a9029x] (nop3) mad.f32 r6.z, c10.y, r3.z, r6.z + :2:0520:0921[4010081ax_104f801ax] (nop1) add.f r6.z, (abs)r6.z, c19.w + :3:0521:0923[6387081ax_001a1050x] (nop1) mad.f32 r6.z, c20.x, r3.z, r6.z + :3:0522:0925[6390881ax_001a001fx] (nop1) mad.f32 r6.z, r7.w, r8.y, r6.z + :3:0523:0927[638e081ax_001a902dx] (nop3) mad.f32 r6.z, c11.y, r7.x, r6.z + :2:0524:0931[40100025x_1056001ax] add.f r9.y, r6.z, c21.z + :2:0525:0932[40180023x_001a106fx] (nop2) add.f r8.w, c27.w, r6.z + :2:0526:0935[40b000f8x_0025106cx] cmps.f.lt p0.x, c27.x, r9.y + :2:0527:0936[40100425x_001a1030x] (sat)add.f r9.y, c12.x, r6.z + :2:0528:0937[40580023x_10700023x] (nop2) max.f r8.w, r8.w, c28.x + :2:0529:0940[40700026x_103e0025x] mul.f r9.z, r9.y, c15.z + :2:0530:0941[40300023x_10290023x] min.f r8.w, r8.w, c10.y + :0:0531:0942[00900000x_000002cdx] br !p0.x, #717 + :2:0532:0943[48100028x_10550019x] (jp)add.f r10.x, r6.y, c21.y + :2:0533:0944[40700029x_10270019x] mul.f r10.y, r6.y, c9.w + :2:0534:0945[40100019x_10590019x] add.f r6.y, r6.y, c22.y + :2:0535:0946[40700027x_00260026x] mul.f r9.w, r9.z, r9.z + :2:0536:0947[4010002ax_10590018x] add.f r10.z, r6.x, c22.y + :3:0537:0948[63948029x_10251024x] mad.f32 r10.y, c9.x, r10.y, c9.y + :2:0538:0949[4010002cx_10030019x] add.f r11.x, r6.y, c0.w + :2:0539:0950[4010002bx_10030028x] add.f r10.w, r10.x, c0.w + :2:0540:0951[40700027x_00260027x] mul.f r9.w, r9.w, r9.z + :2:0541:0952[4130002ex_00000029x] floor.f r11.z, r10.y + :3:0542:0953[6396002cx_10251024x] mad.f32 r11.x, c9.x, r11.x, c9.y + :2:0543:0954[40100018x_10550018x] add.f r6.x, r6.x, c21.y + :3:0544:0955[6395802bx_10251024x] mad.f32 r10.w, c9.x, r10.w, c9.y + :2:0545:0956[40100029x_402e0029x] add.f r10.y, r10.y, (neg)r11.z + :2:0546:0957[4130002ex_0000002cx] floor.f r11.z, r11.x + :2:0547:0958[40700007x_0027102fx] mul.f r1.w, c11.w, r9.w + :2:0548:0959[4130002fx_0000002bx] floor.f r11.w, r10.w + :3:0549:0960[63948029x_10261023x] mad.f32 r10.y, c8.w, r10.y, c9.z + :2:0550:0961[4010002cx_402e002cx] add.f r11.x, r11.x, (neg)r11.z + :2:0551:0962[4010001ax_001a1051x] add.f r6.z, c20.y, r6.z + :2:0552:0963[4010002bx_402f002bx] add.f r10.w, r10.w, (neg)r11.w + :2:0553:0964[4070002dx_10380019x] mul.f r11.y, r6.y, c14.x + :3:0554:0965[6396002cx_10261023x] mad.f32 r11.x, c8.w, r11.x, c9.z + :2:0555:0966[4070041ax_1052001ax] (sat)mul.f r6.z, r6.z, c20.z + :4:0556:0967[80900029x_00000029x] sin r10.y, r10.y + :3:0557:0968[6395802bx_10261023x] mad.f32 r10.w, c8.w, r10.w, c9.z + :3:0558:0969[6396802dx_001e1039x] mad.f32 r11.y, c14.y, r11.y, r7.z + :3:0559:0970[6394902ex_10211025x] (ss)mad.f32 r11.z, c9.y, r10.y, c8.y + :2:0560:0971[4070001ax_1053001ax] mul.f r6.z, r6.z, c20.w + :3:0561:0972[63948031x_105b1025x] mad.f32 r12.y, c9.y, r10.y, c22.w + :4:0562:0973[8090002cx_0000002cx] sin r11.x, r11.x + :3:0563:0974[638e002ex_002e1037x] mad.f32 r11.z, c13.w, r7.x, r11.z + :3:0564:0975[638e0031x_00311037x] mad.f32 r12.y, c13.w, r7.x, r12.y + :4:0565:0976[8090002bx_0000002bx] sin r10.w, r10.w + :3:0566:0977[63948029x_105e1025x] mad.f32 r10.y, c9.y, r10.y, c23.z + :3:0567:0978[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :3:0568:0979[638e001cx_00291037x] mad.f32 r7.x, c13.w, r7.x, r10.y + :3:0569:0980[63988029x_10251024x] mad.f32 r10.y, c9.x, r12.y, c9.y + :3:0570:0981[6388102bx_001d002bx] (ss)mad.f32 r10.w, r10.w, r4.x, r7.y + :3:0571:0982[63880010x_001d002cx] mad.f32 r4.x, r11.x, r4.x, r7.y + :3:0572:0983[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :2:0573:0984[41300031x_00000029x] floor.f r12.y, r10.y + :3:0574:0985[6395802bx_10251024x] mad.f32 r10.w, c9.x, r10.w, c9.y + :3:0575:0986[6397001dx_10251024x] mad.f32 r7.y, c9.x, r11.z, c9.y + :2:0576:0987[41300032x_0000001cx] floor.f r12.z, r7.x + :2:0577:0988[40100029x_40310029x] add.f r10.y, r10.y, (neg)r12.y + :2:0578:0989[40100031x_10550012x] add.f r12.y, r4.z, c21.y + :2:0579:0990[4130002cx_0000001dx] floor.f r11.x, r7.y + :2:0580:0991[4010001cx_4032001cx] add.f r7.x, r7.x, (neg)r12.z + :3:0581:0992[63948029x_10261023x] mad.f32 r10.y, c8.w, r10.y, c9.z + :3:0582:0993[63880010x_10251024x] mad.f32 r4.x, c9.x, r4.x, c9.y + :2:0583:0994[4010001dx_402c001dx] add.f r7.y, r7.y, (neg)r11.x + :3:0584:0995[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :2:0585:0996[4130002cx_0000002bx] floor.f r11.x, r10.w + :2:0586:0997[40100012x_10590012x] add.f r4.z, r4.z, c22.y + :3:0587:0998[638e801dx_10261023x] mad.f32 r7.y, c8.w, r7.y, c9.z + :4:0588:0999[80900029x_00000029x] sin r10.y, r10.y + :2:0589:1000[4130002ex_00000010x] floor.f r11.z, r4.x + :2:0590:1001[4010002bx_402c002bx] add.f r10.w, r10.w, (neg)r11.x + :3:0591:1002[63949029x_10251025x] (ss)mad.f32 r10.y, c9.y, r10.y, c9.y + :4:0592:1003[8090001cx_0000001cx] sin r7.x, r7.x + :3:0593:1004[638e101cx_10251025x] (ss)mad.f32 r7.x, c9.y, r7.x, c9.y + :2:0594:1005[40100010x_402e0010x] add.f r4.x, r4.x, (neg)r11.z + :3:0595:1006[6395802bx_10261023x] mad.f32 r10.w, c8.w, r10.w, c9.z + :4:0596:1007[8090001dx_0000001dx] sin r7.y, r7.y + :2:0597:1008[40700029x_00270029x] mul.f r10.y, r10.y, r9.w + :2:0598:1009[4070001cx_0027001cx] mul.f r7.x, r7.x, r9.w + :3:0599:1010[63880010x_10261023x] mad.f32 r4.x, c8.w, r4.x, c9.z + :3:0600:1011[638e901dx_10251025x] (ss)mad.f32 r7.y, c9.y, r7.y, c9.y + :2:0601:1012[40700829x_001a0029x] (nop1) mul.f r10.y, r10.y, r6.z + :4:0602:1014[8090002cx_0000002bx] sin r11.x, r10.w + :4:0603:1015[80b0102bx_0000002bx] (ss)cos r10.w, r10.w + :0:0604:1016[00000000x_00000000x] nop + :2:0605:1017[4070001dx_0027001dx] mul.f r7.y, r7.y, r9.w + :2:0606:1018[40700027x_002c0018x] mul.f r9.w, r6.x, r11.x + :4:0607:1019[8090002ex_00000010x] sin r11.z, r4.x + :4:0608:1020[80b01010x_00000010x] (ss)cos r4.x, r4.x + :0:0609:1021[00000000x_00000000x] nop + :3:0610:1022[63958027x_00270031x] mad.f32 r9.w, r12.y, r10.w, r9.w + :2:0611:1023[4070001dx_001a001dx] mul.f r7.y, r7.y, r6.z + :2:0612:1024[4070001ax_001a001cx] mul.f r6.z, r7.x, r6.z + :2:0613:1025[4130001cx_0000002dx] floor.f r7.x, r11.y + :2:0614:1026[4070002fx_002e002ax] mul.f r11.w, r10.z, r11.z + :2:0615:1027[40701030x_0010002ax] (ss)mul.f r12.x, r10.z, r4.x + :3:0616:1028[63880010x_002f0012x] mad.f32 r4.x, r4.z, r4.x, r11.w + :2:0617:1029[4010001cx_401c002dx] add.f r7.x, r11.y, (neg)r7.x + :2:0618:1030[4070002dx_002b0018x] mul.f r11.y, r6.x, r10.w + :3:0619:1031[6397002ex_40300012x] mad.f32 r11.z, r4.z, (neg)r11.z, r12.x + :3:0620:1032[6396002bx_402d0031x] mad.f32 r10.w, r12.y, (neg)r11.x, r11.y + :2:0621:1033[4070002cx_10380027x] mul.f r11.x, r9.w, c14.x + :3:0622:1034[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :2:0623:1035[40700030x_1038002ex] mul.f r12.x, r11.z, c14.x + :2:0624:1036[4070002dx_1038002bx] mul.f r11.y, r10.w, c14.x + :3:0625:1037[6396002cx_001e9039x] (nop2) mad.f32 r11.x, c14.y, r11.x, r7.z + :3:0626:1040[6396802dx_001e1039x] mad.f32 r11.y, c14.y, r11.y, r7.z + :4:0627:1041[8090001cx_0000001cx] sin r7.x, r7.x + :3:0628:1042[6396002cx_10251024x] mad.f32 r11.x, c9.x, r11.x, c9.y + :2:0629:1043[4070181cx_0008001cx] (ss)(nop1) mul.f r7.x, r7.x, r2.x + :3:0630:1045[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :2:0631:1046[41300032x_0000002cx] floor.f r12.z, r11.x + :3:0632:1047[6388001cx_001c1038x] mad.f32 r7.x, c14.x, r4.x, r7.x + :2:0633:1048[40700010x_10380010x] mul.f r4.x, r4.x, c14.x + :2:0634:1049[41300033x_0000002dx] floor.f r12.w, r11.y + :2:0635:1050[4018002cx_4032002cx] (nop2) add.f r11.x, r11.x, (neg)r12.z + :2:0636:1053[4010002dx_4033002dx] add.f r11.y, r11.y, (neg)r12.w + :3:0637:1054[6396002cx_10261023x] mad.f32 r11.x, c8.w, r11.x, c9.z + :3:0638:1055[63880810x_001e1039x] (nop1) mad.f32 r4.x, c14.y, r4.x, r7.z + :3:0639:1057[6396882dx_10269023x] (nop3) mad.f32 r11.y, c8.w, r11.y, c9.z + :4:0640:1061[8090002cx_0000002cx] sin r11.x, r11.x + :3:0641:1062[63880010x_10251024x] mad.f32 r4.x, c9.x, r4.x, c9.y + :2:0642:1063[4070182cx_0008002cx] (ss)(nop1) mul.f r11.x, r11.x, r2.x + :4:0643:1065[8090002dx_0000002dx] sin r11.y, r11.y + :3:0644:1066[6395802bx_002c1038x] mad.f32 r10.w, c14.x, r10.w, r11.x + :2:0645:1067[41300037x_00000010x] floor.f r13.w, r4.x + :2:0646:1068[4070182cx_0008002dx] (ss)(nop1) mul.f r11.x, r11.y, r2.x + :3:0647:1070[6394002cx_002c1038x] mad.f32 r11.x, c14.x, r10.x, r11.x + :2:0648:1071[40700032x_103b002bx] mul.f r12.z, r10.w, c14.w + :2:0649:1072[40700033x_103f002bx] mul.f r12.w, r10.w, c15.w + :2:0650:1073[4070002dx_1042002bx] mul.f r11.y, r10.w, c16.z + :3:0651:1074[63960034x_10251024x] mad.f32 r13.x, c9.x, r11.x, c9.y + :3:0652:1075[6395802bx_10251024x] mad.f32 r10.w, c9.x, r10.w, c9.y + :2:0653:1076[40100810x_40370010x] (nop1) add.f r4.x, r4.x, (neg)r13.w + :2:0654:1078[41300036x_00000034x] floor.f r13.z, r13.x + :2:0655:1079[41300035x_0000002bx] floor.f r13.y, r10.w + :3:0656:1080[63880810x_10261023x] (nop1) mad.f32 r4.x, c8.w, r4.x, c9.z + :2:0657:1082[40100034x_40360034x] add.f r13.x, r13.x, (neg)r13.z + :2:0658:1083[4018002bx_4035002bx] (nop2) add.f r10.w, r10.w, (neg)r13.y + :3:0659:1086[639a0034x_10261023x] mad.f32 r13.x, c8.w, r13.x, c9.z + :4:0660:1087[80900010x_00000010x] sin r4.x, r4.x + :3:0661:1088[6395802bx_10261023x] mad.f32 r10.w, c8.w, r10.w, c9.z + :2:0662:1089[40781810x_00080010x] (ss)(nop3) mul.f r4.x, r4.x, r2.x + :0:0663:1093[00000000x_00000000x] nop + :4:0664:1094[80900036x_00000034x] sin r13.z, r13.x + :4:0665:1095[80b01034x_00000034x] (ss)cos r13.x, r13.x + :0:0666:1096[00000000x_00000000x] nop + :4:0667:1097[80b00035x_0000002bx] cos r13.y, r10.w + :4:0668:1098[8090102bx_0000002bx] (ss)sin r10.w, r10.w + :3:0669:1099[63970010x_00101038x] mad.f32 r4.x, c14.x, r11.z, r4.x + :2:0670:1100[40700035x_00360035x] mul.f r13.y, r13.y, r13.z + :2:0671:1101[40780836x_10380028x] (nop3) mul.f r13.z, r10.x, c14.x + :3:0672:1105[639b0036x_001e1039x] mad.f32 r13.z, c14.y, r13.z, r7.z + :3:0673:1106[6398001ex_001e1039x] mad.f32 r7.z, c14.y, r12.x, r7.z + :2:0674:1107[40700037x_103b0010x] mul.f r13.w, r4.x, c14.w + :2:0675:1108[4070002ex_10420010x] mul.f r11.z, r4.x, c16.z + :3:0676:1109[638e0037x_0037103cx] mad.f32 r13.w, c15.x, r7.x, r13.w + :3:0677:1110[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :2:0678:1111[40700038x_103f0010x] mul.f r14.x, r4.x, c15.w + :3:0679:1112[638e0030x_10251024x] mad.f32 r12.x, c9.x, r7.x, c9.y + :3:0680:1113[638e002ex_002e1043x] mad.f32 r11.z, c16.w, r7.x, r11.z + :2:0681:1114[41300039x_0000001ex] floor.f r14.y, r7.z + :3:0682:1115[638e001cx_00381040x] mad.f32 r7.x, c16.x, r7.x, r14.x + :3:0683:1116[639b002fx_10251024x] mad.f32 r11.w, c9.x, r13.z, c9.y + :2:0684:1117[41300036x_00000030x] floor.f r13.z, r12.x + :2:0685:1118[4010001ex_4039001ex] add.f r7.z, r7.z, (neg)r14.y + :3:0686:1119[63880010x_10259024x] (nop2) mad.f32 r4.x, c9.x, r4.x, c9.y + :3:0687:1122[638f001ex_10261023x] mad.f32 r7.z, c8.w, r7.z, c9.z + :2:0688:1123[40100030x_40360030x] add.f r12.x, r12.x, (neg)r13.z + :2:0689:1124[41380838x_00000010x] (nop3) floor.f r14.x, r4.x + :0:0690:1128[00000000x_00000000x] nop + :4:0691:1129[8090001ex_0000001ex] sin r7.z, r7.z + :3:0692:1130[63980030x_10261023x] mad.f32 r12.x, c8.w, r12.x, c9.z + :2:0693:1131[40100010x_40380010x] add.f r4.x, r4.x, (neg)r14.x + :2:0694:1132[4070181ex_0008001ex] (ss)(nop1) mul.f r7.z, r7.z, r2.x + :3:0695:1134[638c801ex_001e1038x] mad.f32 r7.z, c14.x, r6.y, r7.z + :3:0696:1135[63880010x_10269023x] (nop2) mad.f32 r4.x, c8.w, r4.x, c9.z + :3:0697:1138[638f0037x_0037103dx] mad.f32 r13.w, c15.y, r7.z, r13.w + :4:0698:1139[80b00036x_00000030x] cos r13.z, r12.x + :4:0699:1140[80901030x_00000030x] (ss)sin r12.x, r12.x + :3:0700:1141[638f002ex_002e1044x] mad.f32 r11.z, c17.x, r7.z, r11.z + :3:0701:1142[638f081cx_001c1041x] (nop1) mad.f32 r7.x, c16.y, r7.z, r7.x + :4:0702:1144[80b00038x_00000010x] cos r14.x, r4.x + :4:0703:1145[80901010x_00000010x] (ss)sin r4.x, r4.x + :3:0704:1146[639b803ax_001b103ax] mad.f32 r14.z, c14.z, r13.w, r6.w + :3:0705:1147[63970039x_001b103ax] mad.f32 r14.y, c14.z, r11.z, r6.w + :3:0706:1148[638e003bx_001b103ax] mad.f32 r14.w, c14.z, r7.x, r6.w + :3:0707:1149[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :3:0708:1150[639d003ax_10251024x] mad.f32 r14.z, c9.x, r14.z, c9.y + :3:0709:1151[639c8039x_10251024x] mad.f32 r14.y, c9.x, r14.y, c9.y + :3:0710:1152[639d883bx_10251024x] (nop1) mad.f32 r14.w, c9.x, r14.w, c9.y + :2:0711:1154[4130003dx_0000003ax] floor.f r15.y, r14.z + :2:0712:1155[4138003cx_00000039x] (nop2) floor.f r15.x, r14.y + :2:0713:1158[4010003ax_403d003ax] add.f r14.z, r14.z, (neg)r15.y + :2:0714:1159[40180039x_403c0039x] (nop2) add.f r14.y, r14.y, (neg)r15.x + :3:0715:1162[639d003ax_10261023x] mad.f32 r14.z, c8.w, r14.z, c9.z + :3:0716:1163[639c8839x_10269023x] (nop3) mad.f32 r14.y, c8.w, r14.y, c9.z + :0:0717:1167[00000100x_00000000x] (rpt1)nop + :4:0718:1169[8090003ax_0000003ax] sin r14.z, r14.z + :3:0719:1170[6384101cx_001c003ax] (ss)mad.f32 r7.x, r14.z, r2.x, r7.x + :4:0720:1171[80900039x_00000039x] sin r14.y, r14.y + :3:0721:1172[63841037x_00378039x] (ss)(nop2) mad.f32 r13.w, r14.y, r2.x, r13.w + :3:0722:1175[638e003dx_10251024x] mad.f32 r15.y, c9.x, r7.x, c9.y + :2:0723:1176[40700039x_10420037x] mul.f r14.y, r13.w, c16.z + :2:0724:1177[4070003ax_103b0037x] mul.f r14.z, r13.w, c14.w + :2:0725:1178[4070003cx_103f0037x] mul.f r15.x, r13.w, c15.w + :2:0726:1179[4130003fx_0000003dx] floor.f r15.w, r15.y + :3:0727:1180[639b8037x_10259024x] (nop2) mad.f32 r13.w, c9.x, r13.w, c9.y + :2:0728:1183[4010003dx_403f003dx] add.f r15.y, r15.y, (neg)r15.w + :2:0729:1184[4138003ex_00000037x] (nop2) floor.f r15.z, r13.w + :3:0730:1187[639e803dx_10261023x] mad.f32 r15.y, c8.w, r15.y, c9.z + :2:0731:1188[40180837x_403e0037x] (nop3) add.f r13.w, r13.w, (neg)r15.z + :0:0732:1192[00000100x_00000000x] (rpt1)nop + :4:0733:1194[8090003fx_0000003dx] sin r15.w, r15.y + :4:0734:1195[80b0103dx_0000003dx] (ss)cos r15.y, r15.y + :3:0735:1196[639b8837x_10269023x] (nop3) mad.f32 r13.w, c8.w, r13.w, c9.z + :0:0736:1200[00000200x_00000000x] (rpt2)nop + :4:0737:1203[80b0003ex_00000037x] cos r15.z, r13.w + :4:0738:1204[80901037x_00000037x] (ss)sin r13.w, r13.w + :2:0739:1205[4070003ex_003f003ex] mul.f r15.z, r15.z, r15.w + :2:0740:1206[4138083fx_0000003bx] (nop3) floor.f r15.w, r14.w + :2:0741:1210[4018083bx_403f003bx] (nop3) add.f r14.w, r14.w, (neg)r15.w + :3:0742:1214[639d883bx_10269023x] (nop3) mad.f32 r14.w, c8.w, r14.w, c9.z + :0:0743:1218[00000200x_00000000x] (rpt2)nop + :4:0744:1221[8090003bx_0000003bx] sin r14.w, r14.w + :3:0745:1222[6384182ex_002e803bx] (ss)(nop3) mad.f32 r11.z, r14.w, r2.x, r11.z + :3:0746:1226[63970039x_00391043x] mad.f32 r14.y, c16.w, r11.z, r14.y + :3:0747:1227[6397003ax_003a103cx] mad.f32 r14.z, c15.x, r11.z, r14.z + :3:0748:1228[6397003bx_003c1040x] mad.f32 r14.w, c16.x, r11.z, r15.x + :3:0749:1229[638e0039x_00391044x] mad.f32 r14.y, c17.x, r7.x, r14.y + :3:0750:1230[638e003ax_003a103dx] mad.f32 r14.z, c15.y, r7.x, r14.z + :3:0751:1231[638e001cx_003b1041x] mad.f32 r7.x, c16.y, r7.x, r14.w + :3:0752:1232[6397002ex_10251024x] mad.f32 r11.z, c9.x, r11.z, c9.y + :3:0753:1233[639c803bx_00241046x] mad.f32 r14.w, c17.z, r14.y, r9.x + :3:0754:1234[639d003cx_00241046x] mad.f32 r15.x, c17.z, r14.z, r9.x + :3:0755:1235[638e083fx_00241046x] (nop1) mad.f32 r15.w, c17.z, r7.x, r9.x + :3:0756:1237[639d803bx_10251024x] mad.f32 r14.w, c9.x, r14.w, c9.y + :3:0757:1238[639e003cx_10251024x] mad.f32 r15.x, c9.x, r15.x, c9.y + :3:0758:1239[639f883fx_10251024x] (nop1) mad.f32 r15.w, c9.x, r15.w, c9.y + :2:0759:1241[41300040x_0000003bx] floor.f r16.x, r14.w + :2:0760:1242[41380041x_0000003cx] (nop2) floor.f r16.y, r15.x + :2:0761:1245[4010003bx_4040003bx] add.f r14.w, r14.w, (neg)r16.x + :2:0762:1246[4018003cx_4041003cx] (nop2) add.f r15.x, r15.x, (neg)r16.y + :3:0763:1249[639d803bx_10261023x] mad.f32 r14.w, c8.w, r14.w, c9.z + :3:0764:1250[639e083cx_10269023x] (nop3) mad.f32 r15.x, c8.w, r15.x, c9.z + :0:0765:1254[00000100x_00000000x] (rpt1)nop + :4:0766:1256[8090003bx_0000003bx] sin r14.w, r14.w + :3:0767:1257[6384103ax_003a003bx] (ss)mad.f32 r14.z, r14.w, r2.x, r14.z + :4:0768:1258[8090003cx_0000003cx] sin r15.x, r15.x + :3:0769:1259[6384101cx_001c803cx] (ss)(nop2) mad.f32 r7.x, r15.x, r2.x, r7.x + :2:0770:1262[4070003bx_1042003ax] mul.f r14.w, r14.z, c16.z + :2:0771:1263[40700040x_103f003ax] mul.f r16.x, r14.z, c15.w + :2:0772:1264[4070003cx_103b003ax] mul.f r15.x, r14.z, c14.w + :3:0773:1265[639d003ax_10251024x] mad.f32 r14.z, c9.x, r14.z, c9.y + :3:0774:1266[638e0041x_10259024x] (nop2) mad.f32 r16.y, c9.x, r7.x, c9.y + :2:0775:1269[41300042x_0000003ax] floor.f r16.z, r14.z + :2:0776:1270[41380043x_00000041x] (nop2) floor.f r16.w, r16.y + :2:0777:1273[4010003ax_4042003ax] add.f r14.z, r14.z, (neg)r16.z + :2:0778:1274[40180041x_40430041x] (nop2) add.f r16.y, r16.y, (neg)r16.w + :3:0779:1277[639d003ax_10261023x] mad.f32 r14.z, c8.w, r14.z, c9.z + :3:0780:1278[63a08841x_10269023x] (nop3) mad.f32 r16.y, c8.w, r16.y, c9.z + :0:0781:1282[00000100x_00000000x] (rpt1)nop + :4:0782:1284[80b00042x_0000003ax] cos r16.z, r14.z + :4:0783:1285[8090103ax_0000003ax] (ss)sin r14.z, r14.z + :0:0784:1286[00000000x_00000000x] nop + :4:0785:1287[80900043x_00000041x] sin r16.w, r16.y + :4:0786:1288[80b01041x_00000041x] (ss)cos r16.y, r16.y + :2:0787:1289[40700042x_00430042x] mul.f r16.z, r16.z, r16.w + :2:0788:1290[41380843x_0000003fx] (nop3) floor.f r16.w, r15.w + :2:0789:1294[4018083fx_4043003fx] (nop3) add.f r15.w, r15.w, (neg)r16.w + :3:0790:1298[639f883fx_10269023x] (nop3) mad.f32 r15.w, c8.w, r15.w, c9.z + :0:0791:1302[00000200x_00000000x] (rpt2)nop + :4:0792:1305[8090003fx_0000003fx] sin r15.w, r15.w + :3:0793:1306[63841839x_0039803fx] (ss)(nop3) mad.f32 r14.y, r15.w, r2.x, r14.y + :3:0794:1310[639c803bx_003b1043x] mad.f32 r14.w, c16.w, r14.y, r14.w + :3:0795:1311[639c803cx_003c103cx] mad.f32 r15.x, c15.x, r14.y, r15.x + :3:0796:1312[639c803fx_00401040x] mad.f32 r15.w, c16.x, r14.y, r16.x + :3:0797:1313[638e003bx_003b1044x] mad.f32 r14.w, c17.x, r7.x, r14.w + :3:0798:1314[638e003cx_003c103dx] mad.f32 r15.x, c15.y, r7.x, r15.x + :3:0799:1315[638e001cx_003f1041x] mad.f32 r7.x, c16.y, r7.x, r15.w + :3:0800:1316[639c8039x_10251024x] mad.f32 r14.y, c9.x, r14.y, c9.y + :3:0801:1317[639d803fx_00221049x] mad.f32 r15.w, c18.y, r14.w, r8.z + :3:0802:1318[639e0040x_00221049x] mad.f32 r16.x, c18.y, r15.x, r8.z + :3:0803:1319[638e0843x_00221049x] (nop1) mad.f32 r16.w, c18.y, r7.x, r8.z + :3:0804:1321[639f803fx_10251024x] mad.f32 r15.w, c9.x, r15.w, c9.y + :3:0805:1322[63a00040x_10251024x] mad.f32 r16.x, c9.x, r16.x, c9.y + :3:0806:1323[63a18843x_10251024x] (nop1) mad.f32 r16.w, c9.x, r16.w, c9.y + :2:0807:1325[41300044x_0000003fx] floor.f r17.x, r15.w + :2:0808:1326[41380045x_00000040x] (nop2) floor.f r17.y, r16.x + :2:0809:1329[4010003fx_4044003fx] add.f r15.w, r15.w, (neg)r17.x + :2:0810:1330[40180040x_40450040x] (nop2) add.f r16.x, r16.x, (neg)r17.y + :3:0811:1333[639f803fx_10261023x] mad.f32 r15.w, c8.w, r15.w, c9.z + :3:0812:1334[63a00840x_10269023x] (nop3) mad.f32 r16.x, c8.w, r16.x, c9.z + :0:0813:1338[00000100x_00000000x] (rpt1)nop + :4:0814:1340[8090003fx_0000003fx] sin r15.w, r15.w + :3:0815:1341[6384103cx_003c003fx] (ss)mad.f32 r15.x, r15.w, r2.x, r15.x + :4:0816:1342[80900040x_00000040x] sin r16.x, r16.x + :3:0817:1343[6384101cx_001c8040x] (ss)(nop2) mad.f32 r7.x, r16.x, r2.x, r7.x + :2:0818:1346[4070003fx_1042003cx] mul.f r15.w, r15.x, c16.z + :2:0819:1347[40700044x_103f003cx] mul.f r17.x, r15.x, c15.w + :2:0820:1348[40700040x_103b003cx] mul.f r16.x, r15.x, c14.w + :3:0821:1349[639e003cx_10251024x] mad.f32 r15.x, c9.x, r15.x, c9.y + :3:0822:1350[638e0045x_10259024x] (nop2) mad.f32 r17.y, c9.x, r7.x, c9.y + :2:0823:1353[41300046x_0000003cx] floor.f r17.z, r15.x + :2:0824:1354[41380047x_00000045x] (nop2) floor.f r17.w, r17.y + :2:0825:1357[4010003cx_4046003cx] add.f r15.x, r15.x, (neg)r17.z + :2:0826:1358[40180045x_40470045x] (nop2) add.f r17.y, r17.y, (neg)r17.w + :3:0827:1361[639e003cx_10261023x] mad.f32 r15.x, c8.w, r15.x, c9.z + :3:0828:1362[63a28845x_10269023x] (nop3) mad.f32 r17.y, c8.w, r17.y, c9.z + :0:0829:1366[00000100x_00000000x] (rpt1)nop + :4:0830:1368[80b00046x_0000003cx] cos r17.z, r15.x + :4:0831:1369[8090103cx_0000003cx] (ss)sin r15.x, r15.x + :0:0832:1370[00000000x_00000000x] nop + :4:0833:1371[80900047x_00000045x] sin r17.w, r17.y + :4:0834:1372[80b01045x_00000045x] (ss)cos r17.y, r17.y + :2:0835:1373[40700046x_00470046x] mul.f r17.z, r17.z, r17.w + :2:0836:1374[41380847x_00000043x] (nop3) floor.f r17.w, r16.w + :2:0837:1378[40180843x_40470043x] (nop3) add.f r16.w, r16.w, (neg)r17.w + :3:0838:1382[63a18843x_10269023x] (nop3) mad.f32 r16.w, c8.w, r16.w, c9.z + :0:0839:1386[00000200x_00000000x] (rpt2)nop + :4:0840:1389[80900043x_00000043x] sin r16.w, r16.w + :3:0841:1390[6384183bx_003b8043x] (ss)(nop3) mad.f32 r14.w, r16.w, r2.x, r14.w + :3:0842:1394[639d803fx_003f1043x] mad.f32 r15.w, c16.w, r14.w, r15.w + :3:0843:1395[639d8040x_0040103cx] mad.f32 r16.x, c15.x, r14.w, r16.x + :3:0844:1396[639d8043x_00441040x] mad.f32 r16.w, c16.x, r14.w, r17.x + :3:0845:1397[639d803bx_10251024x] mad.f32 r14.w, c9.x, r14.w, c9.y + :3:0846:1398[638e003fx_003f1044x] mad.f32 r15.w, c17.x, r7.x, r15.w + :3:0847:1399[638e0040x_0040103dx] mad.f32 r16.x, c15.y, r7.x, r16.x + :3:0848:1400[638e001cx_00439041x] (nop2) mad.f32 r7.x, c16.y, r7.x, r16.w + :3:0849:1403[63a00044x_0020104cx] mad.f32 r17.x, c19.x, r16.x, r8.x + :3:0850:1404[638e0047x_0020104cx] mad.f32 r17.w, c19.x, r7.x, r8.x + :3:0851:1405[639f8843x_0020104cx] (nop1) mad.f32 r16.w, c19.x, r15.w, r8.x + :3:0852:1407[63a20044x_10251024x] mad.f32 r17.x, c9.x, r17.x, c9.y + :3:0853:1408[63a38047x_10251024x] mad.f32 r17.w, c9.x, r17.w, c9.y + :3:0854:1409[63a18843x_10251024x] (nop1) mad.f32 r16.w, c9.x, r16.w, c9.y + :2:0855:1411[41300849x_00000044x] (nop1) floor.f r18.y, r17.x + :2:0856:1413[41300848x_00000043x] (nop1) floor.f r18.x, r16.w + :2:0857:1415[40100844x_40490044x] (nop1) add.f r17.x, r17.x, (neg)r18.y + :2:0858:1417[40100843x_40480043x] (nop1) add.f r16.w, r16.w, (neg)r18.x + :3:0859:1419[63a20844x_10261023x] (nop1) mad.f32 r17.x, c8.w, r17.x, c9.z + :3:0860:1421[63a18843x_10269023x] (nop3) mad.f32 r16.w, c8.w, r16.w, c9.z + :0:0861:1425[00000000x_00000000x] nop + :4:0862:1426[80900044x_00000044x] sin r17.x, r17.x + :3:0863:1427[6384181cx_001c0044x] (ss)(nop1) mad.f32 r7.x, r17.x, r2.x, r7.x + :4:0864:1429[80900043x_00000043x] sin r16.w, r16.w + :3:0865:1430[63841840x_00400043x] (ss)(nop1) mad.f32 r16.x, r16.w, r2.x, r16.x + :3:0866:1432[638e081cx_10251024x] (nop1) mad.f32 r7.x, c9.x, r7.x, c9.y + :3:0867:1434[63a00840x_10251024x] (nop1) mad.f32 r16.x, c9.x, r16.x, c9.y + :2:0868:1436[41300844x_0000001cx] (nop1) floor.f r17.x, r7.x + :2:0869:1438[41300843x_00000040x] (nop1) floor.f r16.w, r16.x + :2:0870:1440[4010081cx_4044001cx] (nop1) add.f r7.x, r7.x, (neg)r17.x + :2:0871:1442[40100840x_40430040x] (nop1) add.f r16.x, r16.x, (neg)r16.w + :3:0872:1444[638e081cx_10261023x] (nop1) mad.f32 r7.x, c8.w, r7.x, c9.z + :3:0873:1446[63a00840x_10269023x] (nop3) mad.f32 r16.x, c8.w, r16.x, c9.z + :0:0874:1450[00000000x_00000000x] nop + :4:0875:1451[80900044x_0000001cx] sin r17.x, r7.x + :4:0876:1452[80b0101cx_0000001cx] (ss)cos r7.x, r7.x + :0:0877:1453[00000100x_00000000x] (rpt1)nop + :4:0878:1455[80b00043x_00000040x] cos r16.w, r16.x + :4:0879:1456[80901040x_00000040x] (ss)sin r16.x, r16.x + :2:0880:1457[40700043x_00440043x] mul.f r16.w, r16.w, r17.x + :2:0881:1458[41380844x_00000047x] (nop3) floor.f r17.x, r17.w + :2:0882:1462[40180844x_40440047x] (nop3) add.f r17.x, r17.w, (neg)r17.x + :3:0883:1466[63a20844x_10269023x] (nop3) mad.f32 r17.x, c8.w, r17.x, c9.z + :0:0884:1470[00000200x_00000000x] (rpt2)nop + :4:0885:1473[80900044x_00000044x] sin r17.x, r17.x + :3:0886:1474[6384183fx_003f8044x] (ss)(nop3) mad.f32 r15.w, r17.x, r2.x, r15.w + :3:0887:1478[639f883fx_10259024x] (nop3) mad.f32 r15.w, c9.x, r15.w, c9.y + :2:0888:1482[41380844x_0000003fx] (nop3) floor.f r17.x, r15.w + :2:0889:1486[4018083fx_4044003fx] (nop3) add.f r15.w, r15.w, (neg)r17.x + :3:0890:1490[639f883fx_10269023x] (nop3) mad.f32 r15.w, c8.w, r15.w, c9.z + :0:0891:1494[00000200x_00000000x] (rpt2)nop + :4:0892:1497[80b00044x_0000003fx] cos r17.x, r15.w + :4:0893:1498[8090103fx_0000003fx] (ss)sin r15.w, r15.w + :3:0894:1499[63a00840x_00430044x] (nop1) mad.f32 r16.x, r17.x, r16.x, r16.w + :3:0895:1501[639f901cx_0040001cx] (ss)mad.f32 r7.x, r7.x, r15.w, r16.x + :2:0896:1502[4138083fx_0000003bx] (nop3) floor.f r15.w, r14.w + :2:0897:1506[4010003bx_403f003bx] add.f r14.w, r14.w, (neg)r15.w + :2:0898:1507[4078001cx_104e001cx] (nop2) mul.f r7.x, r7.x, c19.z + :3:0899:1510[639d883bx_10269023x] (nop3) mad.f32 r14.w, c8.w, r14.w, c9.z + :0:0900:1514[00000200x_00000000x] (rpt2)nop + :4:0901:1517[80b0003fx_0000003bx] cos r15.w, r14.w + :4:0902:1518[8090103bx_0000003bx] (ss)sin r14.w, r14.w + :3:0903:1519[639e083cx_0046003fx] (nop1) mad.f32 r15.x, r15.w, r15.x, r17.z + :3:0904:1521[639d903bx_003c0045x] (ss)mad.f32 r14.w, r17.y, r14.w, r15.x + :2:0905:1522[4138083cx_00000039x] (nop3) floor.f r15.x, r14.y + :2:0906:1526[40100039x_403c0039x] add.f r14.y, r14.y, (neg)r15.x + :2:0907:1527[4078003bx_104b003bx] (nop2) mul.f r14.w, r14.w, c18.w + :3:0908:1530[639c8839x_10269023x] (nop3) mad.f32 r14.y, c8.w, r14.y, c9.z + :0:0909:1534[00000200x_00000000x] (rpt2)nop + :4:0910:1537[80b0003cx_00000039x] cos r15.x, r14.y + :4:0911:1538[80901039x_00000039x] (ss)sin r14.y, r14.y + :3:0912:1539[639d083ax_0042003cx] (nop1) mad.f32 r14.z, r15.x, r14.z, r16.z + :3:0913:1541[639c9039x_003a0041x] (ss)mad.f32 r14.y, r16.y, r14.y, r14.z + :2:0914:1542[4138083ax_0000002ex] (nop3) floor.f r14.z, r11.z + :2:0915:1546[4010002ex_403a002ex] add.f r11.z, r11.z, (neg)r14.z + :2:0916:1547[40780039x_10480039x] (nop2) mul.f r14.y, r14.y, c18.x + :3:0917:1550[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:0918:1554[00000200x_00000000x] (rpt2)nop + :4:0919:1557[80b0003ax_0000002ex] cos r14.z, r11.z + :4:0920:1558[8090102ex_0000002ex] (ss)sin r11.z, r11.z + :3:0921:1559[639b8837x_003e003ax] (nop1) mad.f32 r13.w, r14.z, r13.w, r15.z + :3:0922:1561[6397102ex_0037003dx] (ss)mad.f32 r11.z, r15.y, r11.z, r13.w + :2:0923:1562[41380837x_0000001ex] (nop3) floor.f r13.w, r7.z + :2:0924:1566[4010001ex_4037001ex] add.f r7.z, r7.z, (neg)r13.w + :2:0925:1567[4078002ex_1045002ex] (nop2) mul.f r11.z, r11.z, c17.y + :3:0926:1570[638f081ex_10269023x] (nop3) mad.f32 r7.z, c8.w, r7.z, c9.z + :0:0927:1574[00000200x_00000000x] (rpt2)nop + :4:0928:1577[80900037x_0000001ex] sin r13.w, r7.z + :4:0929:1578[80b0101ex_0000001ex] (ss)cos r7.z, r7.z + :2:0930:1579[40700837x_00370038x] (nop1) mul.f r13.w, r14.x, r13.w + :3:0931:1581[63880810x_00370036x] (nop1) mad.f32 r4.x, r13.z, r4.x, r13.w + :3:0932:1583[63981810x_0010801ex] (ss)(nop3) mad.f32 r4.x, r7.z, r12.x, r4.x + :2:0933:1587[40180810x_c02ec010x] (nop3) add.f r4.x, (absneg)r4.x, (absneg)r11.z + :2:0934:1591[40180810x_c0390010x] (nop3) add.f r4.x, r4.x, (absneg)r14.y + :2:0935:1595[40180810x_c03b0010x] (nop3) add.f r4.x, r4.x, (absneg)r14.w + :2:0936:1599[40100010x_c01c0010x] add.f r4.x, r4.x, (absneg)r7.x + :2:0937:1600[4130001cx_0000002fx] floor.f r7.x, r11.w + :3:0938:1601[63870010x_00109029x] (nop2) mad.f32 r4.x, c10.y, r3.z, r4.x + :2:0939:1604[4010001cx_401c002fx] add.f r7.x, r11.w, (neg)r7.x + :2:0940:1605[40180010x_104f8010x] (nop2) add.f r4.x, (abs)r4.x, c19.w + :3:0941:1608[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :3:0942:1609[63870810x_00109050x] (nop3) mad.f32 r4.x, c20.x, r3.z, r4.x + :0:0943:1613[00000100x_00000000x] (rpt1)nop + :4:0944:1615[8090001cx_0000001cx] sin r7.x, r7.x + :3:0945:1616[63908010x_0010001fx] mad.f32 r4.x, r7.w, r8.y, r4.x + :2:0946:1617[4070181cx_0008001cx] (ss)(nop1) mul.f r7.x, r7.x, r2.x + :3:0947:1619[6393801cx_001c1038x] mad.f32 r7.x, c14.x, r9.w, r7.x + :2:0948:1620[40180010x_10560010x] (nop2) add.f r4.x, r4.x, c21.z + :3:0949:1623[638e0027x_0032103cx] mad.f32 r9.w, c15.x, r7.x, r12.z + :3:0950:1624[638e001ex_002d1043x] mad.f32 r7.z, c16.w, r7.x, r11.y + :3:0951:1625[63960027x_0027103dx] mad.f32 r9.w, c15.y, r11.x, r9.w + :3:0952:1626[638e002dx_00331040x] mad.f32 r11.y, c16.x, r7.x, r12.w + :3:0953:1627[6396001ex_001e1044x] mad.f32 r7.z, c17.x, r11.x, r7.z + :3:0954:1628[6396002cx_002d1041x] mad.f32 r11.x, c16.y, r11.x, r11.y + :3:0955:1629[6393802ex_001b103ax] mad.f32 r11.z, c14.z, r9.w, r6.w + :3:0956:1630[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :3:0957:1631[638f002dx_001b103ax] mad.f32 r11.y, c14.z, r7.z, r6.w + :3:0958:1632[6396001bx_001b103ax] mad.f32 r6.w, c14.z, r11.x, r6.w + :3:0959:1633[6397082ex_10259024x] (nop3) mad.f32 r11.z, c9.x, r11.z, c9.y + :2:0960:1637[41300030x_0000002ex] floor.f r12.x, r11.z + :3:0961:1638[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :3:0962:1639[638d881bx_10251024x] (nop1) mad.f32 r6.w, c9.x, r6.w, c9.y + :2:0963:1641[4010002ex_4030002ex] add.f r11.z, r11.z, (neg)r12.x + :2:0964:1642[4138002fx_0000002dx] (nop2) floor.f r11.w, r11.y + :3:0965:1645[6397002ex_10261023x] mad.f32 r11.z, c8.w, r11.z, c9.z + :2:0966:1646[4018082dx_402f002dx] (nop3) add.f r11.y, r11.y, (neg)r11.w + :0:0967:1650[00000100x_00000000x] (rpt1)nop + :4:0968:1652[8090002ex_0000002ex] sin r11.z, r11.z + :3:0969:1653[6396802dx_10261023x] mad.f32 r11.y, c8.w, r11.y, c9.z + :3:0970:1654[6384182cx_002c802ex] (ss)(nop3) mad.f32 r11.x, r11.z, r2.x, r11.x + :3:0971:1658[63960830x_10259024x] (nop3) mad.f32 r12.x, c9.x, r11.x, c9.y + :2:0972:1662[41300033x_00000030x] floor.f r12.w, r12.x + :4:0973:1663[8090002dx_0000002dx] sin r11.y, r11.y + :3:0974:1664[63841027x_0027802dx] (ss)(nop2) mad.f32 r9.w, r11.y, r2.x, r9.w + :2:0975:1667[40100030x_40330030x] add.f r12.x, r12.x, (neg)r12.w + :2:0976:1668[4070002dx_10420027x] mul.f r11.y, r9.w, c16.z + :2:0977:1669[4070002ex_103b0027x] mul.f r11.z, r9.w, c14.w + :2:0978:1670[4070002fx_103f0027x] mul.f r11.w, r9.w, c15.w + :3:0979:1671[63980030x_10261023x] mad.f32 r12.x, c8.w, r12.x, c9.z + :3:0980:1672[63938827x_10259024x] (nop3) mad.f32 r9.w, c9.x, r9.w, c9.y + :0:0981:1676[00000100x_00000000x] (rpt1)nop + :4:0982:1678[80900033x_00000030x] sin r12.w, r12.x + :4:0983:1679[80b01030x_00000030x] (ss)cos r12.x, r12.x + :2:0984:1680[41380832x_00000027x] (nop3) floor.f r12.z, r9.w + :2:0985:1684[40180827x_40320027x] (nop3) add.f r9.w, r9.w, (neg)r12.z + :3:0986:1688[63938827x_10269023x] (nop3) mad.f32 r9.w, c8.w, r9.w, c9.z + :0:0987:1692[00000200x_00000000x] (rpt2)nop + :4:0988:1695[80b00032x_00000027x] cos r12.z, r9.w + :4:0989:1696[80901027x_00000027x] (ss)sin r9.w, r9.w + :2:0990:1697[40700032x_00330032x] mul.f r12.z, r12.z, r12.w + :2:0991:1698[41380833x_0000001bx] (nop3) floor.f r12.w, r6.w + :2:0992:1702[4018081bx_4033001bx] (nop3) add.f r6.w, r6.w, (neg)r12.w + :3:0993:1706[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:0994:1710[00000200x_00000000x] (rpt2)nop + :4:0995:1713[8090001bx_0000001bx] sin r6.w, r6.w + :3:0996:1714[6384181bx_001e801bx] (ss)(nop3) mad.f32 r6.w, r6.w, r2.x, r7.z + :3:0997:1718[638d801ex_002d1043x] mad.f32 r7.z, c16.w, r6.w, r11.y + :3:0998:1719[638d802dx_002e103cx] mad.f32 r11.y, c15.x, r6.w, r11.z + :3:0999:1720[6396001ex_001e1044x] mad.f32 r7.z, c17.x, r11.x, r7.z + :3:1000:1721[6396002dx_002d103dx] mad.f32 r11.y, c15.y, r11.x, r11.y + :3:1001:1722[638d802ex_002f1040x] mad.f32 r11.z, c16.x, r6.w, r11.w + :3:1002:1723[638d801bx_10251024x] mad.f32 r6.w, c9.x, r6.w, c9.y + :3:1003:1724[6396002cx_002e1041x] mad.f32 r11.x, c16.y, r11.x, r11.z + :3:1004:1725[6396802fx_00241046x] mad.f32 r11.w, c17.z, r11.y, r9.x + :3:1005:1726[638f002ex_00249046x] (nop2) mad.f32 r11.z, c17.z, r7.z, r9.x + :3:1006:1729[6397802fx_10251024x] mad.f32 r11.w, c9.x, r11.w, c9.y + :3:1007:1730[63960024x_00241046x] mad.f32 r9.x, c17.z, r11.x, r9.x + :3:1008:1731[6397082ex_10251024x] (nop1) mad.f32 r11.z, c9.x, r11.z, c9.y + :2:1009:1733[41300036x_0000002fx] floor.f r13.z, r11.w + :3:1010:1734[63920024x_10251024x] mad.f32 r9.x, c9.x, r9.x, c9.y + :2:1011:1735[41300833x_0000002ex] (nop1) floor.f r12.w, r11.z + :2:1012:1737[4018082fx_4036002fx] (nop3) add.f r11.w, r11.w, (neg)r13.z + :3:1013:1741[6397802fx_10261023x] mad.f32 r11.w, c8.w, r11.w, c9.z + :2:1014:1742[4018082ex_4033002ex] (nop3) add.f r11.z, r11.z, (neg)r12.w + :0:1015:1746[00000100x_00000000x] (rpt1)nop + :4:1016:1748[8090002fx_0000002fx] sin r11.w, r11.w + :3:1017:1749[6397002ex_10261023x] mad.f32 r11.z, c8.w, r11.z, c9.z + :3:1018:1750[6384182cx_002c802fx] (ss)(nop3) mad.f32 r11.x, r11.w, r2.x, r11.x + :3:1019:1754[63960836x_10259024x] (nop3) mad.f32 r13.z, c9.x, r11.x, c9.y + :2:1020:1758[41300038x_00000036x] floor.f r14.x, r13.z + :4:1021:1759[8090002ex_0000002ex] sin r11.z, r11.z + :3:1022:1760[6384102dx_002d802ex] (ss)(nop2) mad.f32 r11.y, r11.z, r2.x, r11.y + :2:1023:1763[40100036x_40380036x] add.f r13.z, r13.z, (neg)r14.x + :2:1024:1764[4070002ex_1042002dx] mul.f r11.z, r11.y, c16.z + :2:1025:1765[4070002fx_103b002dx] mul.f r11.w, r11.y, c14.w + :2:1026:1766[40700033x_103f002dx] mul.f r12.w, r11.y, c15.w + :3:1027:1767[639b0036x_10261023x] mad.f32 r13.z, c8.w, r13.z, c9.z + :3:1028:1768[6396882dx_10259024x] (nop3) mad.f32 r11.y, c9.x, r11.y, c9.y + :0:1029:1772[00000100x_00000000x] (rpt1)nop + :4:1030:1774[80900038x_00000036x] sin r14.x, r13.z + :4:1031:1775[80b01036x_00000036x] (ss)cos r13.z, r13.z + :2:1032:1776[41380837x_0000002dx] (nop3) floor.f r13.w, r11.y + :2:1033:1780[4018082dx_4037002dx] (nop3) add.f r11.y, r11.y, (neg)r13.w + :3:1034:1784[6396882dx_10269023x] (nop3) mad.f32 r11.y, c8.w, r11.y, c9.z + :0:1035:1788[00000200x_00000000x] (rpt2)nop + :4:1036:1791[80b00037x_0000002dx] cos r13.w, r11.y + :4:1037:1792[8090102dx_0000002dx] (ss)sin r11.y, r11.y + :2:1038:1793[40700037x_00380037x] mul.f r13.w, r13.w, r14.x + :2:1039:1794[41380838x_00000024x] (nop3) floor.f r14.x, r9.x + :2:1040:1798[40180824x_40380024x] (nop3) add.f r9.x, r9.x, (neg)r14.x + :3:1041:1802[63920824x_10269023x] (nop3) mad.f32 r9.x, c8.w, r9.x, c9.z + :0:1042:1806[00000200x_00000000x] (rpt2)nop + :4:1043:1809[80900024x_00000024x] sin r9.x, r9.x + :3:1044:1810[6384181ex_001e8024x] (ss)(nop3) mad.f32 r7.z, r9.x, r2.x, r7.z + :3:1045:1814[638f0024x_002e1043x] mad.f32 r9.x, c16.w, r7.z, r11.z + :3:1046:1815[638f002ex_002f103cx] mad.f32 r11.z, c15.x, r7.z, r11.w + :3:1047:1816[638f002fx_00331040x] mad.f32 r11.w, c16.x, r7.z, r12.w + :3:1048:1817[6396002ex_002e103dx] mad.f32 r11.z, c15.y, r11.x, r11.z + :3:1049:1818[63960024x_00241044x] mad.f32 r9.x, c17.x, r11.x, r9.x + :3:1050:1819[6396002cx_002f1041x] mad.f32 r11.x, c16.y, r11.x, r11.w + :3:1051:1820[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :3:1052:1821[63970033x_00221049x] mad.f32 r12.w, c18.y, r11.z, r8.z + :3:1053:1822[6392002fx_00221049x] mad.f32 r11.w, c18.y, r9.x, r8.z + :3:1054:1823[63960822x_00221049x] (nop1) mad.f32 r8.z, c18.y, r11.x, r8.z + :3:1055:1825[63998033x_10251024x] mad.f32 r12.w, c9.x, r12.w, c9.y + :3:1056:1826[6397802fx_10251024x] mad.f32 r11.w, c9.x, r11.w, c9.y + :3:1057:1827[63910822x_10251024x] (nop1) mad.f32 r8.z, c9.x, r8.z, c9.y + :2:1058:1829[41300039x_00000033x] floor.f r14.y, r12.w + :2:1059:1830[41380038x_0000002fx] (nop2) floor.f r14.x, r11.w + :2:1060:1833[40100033x_40390033x] add.f r12.w, r12.w, (neg)r14.y + :2:1061:1834[4018002fx_4038002fx] (nop2) add.f r11.w, r11.w, (neg)r14.x + :3:1062:1837[63998033x_10261023x] mad.f32 r12.w, c8.w, r12.w, c9.z + :3:1063:1838[6397882fx_10269023x] (nop3) mad.f32 r11.w, c8.w, r11.w, c9.z + :0:1064:1842[00000100x_00000000x] (rpt1)nop + :4:1065:1844[80900033x_00000033x] sin r12.w, r12.w + :3:1066:1845[6384102cx_002c0033x] (ss)mad.f32 r11.x, r12.w, r2.x, r11.x + :4:1067:1846[8090002fx_0000002fx] sin r11.w, r11.w + :3:1068:1847[6384102ex_002e802fx] (ss)(nop2) mad.f32 r11.z, r11.w, r2.x, r11.z + :3:1069:1850[63960039x_10251024x] mad.f32 r14.y, c9.x, r11.x, c9.y + :2:1070:1851[4070002fx_1042002ex] mul.f r11.w, r11.z, c16.z + :2:1071:1852[40700033x_103b002ex] mul.f r12.w, r11.z, c14.w + :2:1072:1853[40700038x_103f002ex] mul.f r14.x, r11.z, c15.w + :2:1073:1854[4130003bx_00000039x] floor.f r14.w, r14.y + :3:1074:1855[6397002ex_10259024x] (nop2) mad.f32 r11.z, c9.x, r11.z, c9.y + :2:1075:1858[40100039x_403b0039x] add.f r14.y, r14.y, (neg)r14.w + :2:1076:1859[4138003ax_0000002ex] (nop2) floor.f r14.z, r11.z + :3:1077:1862[639c8039x_10261023x] mad.f32 r14.y, c8.w, r14.y, c9.z + :2:1078:1863[4018082ex_403a002ex] (nop3) add.f r11.z, r11.z, (neg)r14.z + :0:1079:1867[00000100x_00000000x] (rpt1)nop + :4:1080:1869[8090003bx_00000039x] sin r14.w, r14.y + :4:1081:1870[80b01039x_00000039x] (ss)cos r14.y, r14.y + :3:1082:1871[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:1083:1875[00000200x_00000000x] (rpt2)nop + :4:1084:1878[80b0003ax_0000002ex] cos r14.z, r11.z + :4:1085:1879[8090102ex_0000002ex] (ss)sin r11.z, r11.z + :2:1086:1880[4070003ax_003b003ax] mul.f r14.z, r14.z, r14.w + :2:1087:1881[4138083bx_00000022x] (nop3) floor.f r14.w, r8.z + :2:1088:1885[40180822x_403b0022x] (nop3) add.f r8.z, r8.z, (neg)r14.w + :3:1089:1889[63910822x_10269023x] (nop3) mad.f32 r8.z, c8.w, r8.z, c9.z + :0:1090:1893[00000200x_00000000x] (rpt2)nop + :4:1091:1896[80900022x_00000022x] sin r8.z, r8.z + :3:1092:1897[63841822x_00248022x] (ss)(nop3) mad.f32 r8.z, r8.z, r2.x, r9.x + :3:1093:1901[63910024x_002f1043x] mad.f32 r9.x, c16.w, r8.z, r11.w + :3:1094:1902[6391002fx_0033103cx] mad.f32 r11.w, c15.x, r8.z, r12.w + :3:1095:1903[63960024x_00241044x] mad.f32 r9.x, c17.x, r11.x, r9.x + :3:1096:1904[63910033x_00381040x] mad.f32 r12.w, c16.x, r8.z, r14.x + :3:1097:1905[6396002fx_002f103dx] mad.f32 r11.w, c15.y, r11.x, r11.w + :3:1098:1906[6396002cx_00331041x] mad.f32 r11.x, c16.y, r11.x, r12.w + :3:1099:1907[63920033x_0020104cx] mad.f32 r12.w, c19.x, r9.x, r8.x + :3:1100:1908[63910022x_10251024x] mad.f32 r8.z, c9.x, r8.z, c9.y + :3:1101:1909[63978038x_0020104cx] mad.f32 r14.x, c19.x, r11.w, r8.x + :3:1102:1910[63960020x_0020104cx] mad.f32 r8.x, c19.x, r11.x, r8.x + :3:1103:1911[63998833x_10251024x] (nop1) mad.f32 r12.w, c9.x, r12.w, c9.y + :3:1104:1913[639c0038x_10251024x] mad.f32 r14.x, c9.x, r14.x, c9.y + :3:1105:1914[63900020x_10251024x] mad.f32 r8.x, c9.x, r8.x, c9.y + :2:1106:1915[4130083bx_00000033x] (nop1) floor.f r14.w, r12.w + :2:1107:1917[4130083cx_00000038x] (nop1) floor.f r15.x, r14.x + :2:1108:1919[40100833x_403b0033x] (nop1) add.f r12.w, r12.w, (neg)r14.w + :2:1109:1921[40100838x_403c0038x] (nop1) add.f r14.x, r14.x, (neg)r15.x + :3:1110:1923[63998833x_10261023x] (nop1) mad.f32 r12.w, c8.w, r12.w, c9.z + :3:1111:1925[639c0838x_10269023x] (nop3) mad.f32 r14.x, c8.w, r14.x, c9.z + :0:1112:1929[00000000x_00000000x] nop + :4:1113:1930[80900033x_00000033x] sin r12.w, r12.w + :3:1114:1931[6384182fx_002f0033x] (ss)(nop1) mad.f32 r11.w, r12.w, r2.x, r11.w + :4:1115:1933[80900038x_00000038x] sin r14.x, r14.x + :3:1116:1934[6384182cx_002c0038x] (ss)(nop1) mad.f32 r11.x, r14.x, r2.x, r11.x + :3:1117:1936[6397882fx_10251024x] (nop1) mad.f32 r11.w, c9.x, r11.w, c9.y + :3:1118:1938[6396082cx_10251024x] (nop1) mad.f32 r11.x, c9.x, r11.x, c9.y + :2:1119:1940[41300833x_0000002fx] (nop1) floor.f r12.w, r11.w + :2:1120:1942[41300838x_0000002cx] (nop1) floor.f r14.x, r11.x + :2:1121:1944[4010082fx_4033002fx] (nop1) add.f r11.w, r11.w, (neg)r12.w + :2:1122:1946[4010082cx_4038002cx] (nop1) add.f r11.x, r11.x, (neg)r14.x + :3:1123:1948[6397882fx_10261023x] (nop1) mad.f32 r11.w, c8.w, r11.w, c9.z + :3:1124:1950[6396082cx_10269023x] (nop3) mad.f32 r11.x, c8.w, r11.x, c9.z + :0:1125:1954[00000000x_00000000x] nop + :4:1126:1955[80b00033x_0000002fx] cos r12.w, r11.w + :4:1127:1956[8090102fx_0000002fx] (ss)sin r11.w, r11.w + :0:1128:1957[00000100x_00000000x] (rpt1)nop + :4:1129:1959[80900038x_0000002cx] sin r14.x, r11.x + :4:1130:1960[80b0102cx_0000002cx] (ss)cos r11.x, r11.x + :2:1131:1961[40700033x_00380033x] mul.f r12.w, r12.w, r14.x + :2:1132:1962[41380838x_00000020x] (nop3) floor.f r14.x, r8.x + :2:1133:1966[40180820x_40380020x] (nop3) add.f r8.x, r8.x, (neg)r14.x + :3:1134:1970[63900820x_10269023x] (nop3) mad.f32 r8.x, c8.w, r8.x, c9.z + :0:1135:1974[00000200x_00000000x] (rpt2)nop + :4:1136:1977[80900020x_00000020x] sin r8.x, r8.x + :3:1137:1978[63841808x_00248020x] (ss)(nop3) mad.f32 r2.x, r8.x, r2.x, r9.x + :3:1138:1982[63840808x_10259024x] (nop3) mad.f32 r2.x, c9.x, r2.x, c9.y + :2:1139:1986[41380820x_00000008x] (nop3) floor.f r8.x, r2.x + :2:1140:1990[40180808x_40200008x] (nop3) add.f r2.x, r2.x, (neg)r8.x + :3:1141:1994[63840808x_10269023x] (nop3) mad.f32 r2.x, c8.w, r2.x, c9.z + :0:1142:1998[00000200x_00000000x] (rpt2)nop + :4:1143:2001[80b00020x_00000008x] cos r8.x, r2.x + :4:1144:2002[80901008x_00000008x] (ss)sin r2.x, r2.x + :3:1145:2003[63978820x_00330020x] (nop1) mad.f32 r8.x, r8.x, r11.w, r12.w + :3:1146:2005[63841008x_0020002cx] (ss)mad.f32 r2.x, r11.x, r2.x, r8.x + :2:1147:2006[41380820x_00000022x] (nop3) floor.f r8.x, r8.z + :2:1148:2010[40100020x_40200022x] add.f r8.x, r8.z, (neg)r8.x + :2:1149:2011[40780008x_104e0008x] (nop2) mul.f r2.x, r2.x, c19.z + :3:1150:2014[63900820x_10269023x] (nop3) mad.f32 r8.x, c8.w, r8.x, c9.z + :0:1151:2018[00000200x_00000000x] (rpt2)nop + :4:1152:2021[80b00022x_00000020x] cos r8.z, r8.x + :4:1153:2022[80901020x_00000020x] (ss)sin r8.x, r8.x + :3:1154:2023[63970822x_003a0022x] (nop1) mad.f32 r8.z, r8.z, r11.z, r14.z + :3:1155:2025[63901020x_00220039x] (ss)mad.f32 r8.x, r14.y, r8.x, r8.z + :2:1156:2026[41380822x_0000001ex] (nop3) floor.f r8.z, r7.z + :2:1157:2030[4010001ex_4022001ex] add.f r7.z, r7.z, (neg)r8.z + :2:1158:2031[40780020x_104b0020x] (nop2) mul.f r8.x, r8.x, c18.w + :3:1159:2034[638f081ex_10269023x] (nop3) mad.f32 r7.z, c8.w, r7.z, c9.z + :0:1160:2038[00000200x_00000000x] (rpt2)nop + :4:1161:2041[80b00022x_0000001ex] cos r8.z, r7.z + :4:1162:2042[8090101ex_0000001ex] (ss)sin r7.z, r7.z + :3:1163:2043[63968822x_00370022x] (nop1) mad.f32 r8.z, r8.z, r11.y, r13.w + :3:1164:2045[638f101ex_00220036x] (ss)mad.f32 r7.z, r13.z, r7.z, r8.z + :2:1165:2046[41380822x_0000001bx] (nop3) floor.f r8.z, r6.w + :2:1166:2050[4010001bx_4022001bx] add.f r6.w, r6.w, (neg)r8.z + :2:1167:2051[4078001ex_1048001ex] (nop2) mul.f r7.z, r7.z, c18.x + :3:1168:2054[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:1169:2058[00000200x_00000000x] (rpt2)nop + :4:1170:2061[80b00022x_0000001bx] cos r8.z, r6.w + :4:1171:2062[8090101bx_0000001bx] (ss)sin r6.w, r6.w + :3:1172:2063[63938822x_00320022x] (nop1) mad.f32 r8.z, r8.z, r9.w, r12.z + :3:1173:2065[638d901bx_00220030x] (ss)mad.f32 r6.w, r12.x, r6.w, r8.z + :2:1174:2066[41380822x_0000001cx] (nop3) floor.f r8.z, r7.x + :2:1175:2070[4010001cx_4022001cx] add.f r7.x, r7.x, (neg)r8.z + :2:1176:2071[4078001bx_1045001bx] (nop2) mul.f r6.w, r6.w, c17.y + :3:1177:2074[638e081cx_10269023x] (nop3) mad.f32 r7.x, c8.w, r7.x, c9.z + :0:1178:2078[00000200x_00000000x] (rpt2)nop + :4:1179:2081[80b00022x_0000001cx] cos r8.z, r7.x + :4:1180:2082[8090101cx_0000001cx] (ss)sin r7.x, r7.x + :3:1181:2083[63958822x_00350022x] (nop1) mad.f32 r8.z, r8.z, r10.w, r13.y + :3:1182:2085[638e181cx_00228034x] (ss)(nop3) mad.f32 r7.x, r13.x, r7.x, r8.z + :2:1183:2089[4010001bx_c01bc01cx] add.f r6.w, (absneg)r7.x, (absneg)r6.w + :2:1184:2090[4070001cx_10360019x] mul.f r7.x, r6.y, c13.z + :2:1185:2091[40700819x_10340019x] (nop1) mul.f r6.y, r6.y, c13.x + :2:1186:2093[4010001bx_c01e001bx] add.f r6.w, r6.w, (absneg)r7.z + :3:1187:2094[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :3:1188:2095[638c8019x_10251024x] mad.f32 r6.y, c9.x, r6.y, c9.y + :2:1189:2096[4070001ex_10340028x] mul.f r7.z, r10.x, c13.x + :2:1190:2097[4010001bx_c020001bx] add.f r6.w, r6.w, (absneg)r8.x + :2:1191:2098[41300022x_0000001cx] floor.f r8.z, r7.x + :2:1192:2099[41300024x_00000019x] floor.f r9.x, r6.y + :3:1193:2100[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :2:1194:2101[40100008x_c008001bx] add.f r2.x, r6.w, (absneg)r2.x + :2:1195:2102[4070001bx_10360028x] mul.f r6.w, r10.x, c13.z + :2:1196:2103[40100019x_40240019x] add.f r6.y, r6.y, (neg)r9.x + :2:1197:2104[4010001cx_4022001cx] add.f r7.x, r7.x, (neg)r8.z + :3:1198:2105[63870008x_00081029x] mad.f32 r2.x, c10.y, r3.z, r2.x + :3:1199:2106[638d801bx_10251024x] mad.f32 r6.w, c9.x, r6.w, c9.y + :3:1200:2107[638c8019x_10261023x] mad.f32 r6.y, c8.w, r6.y, c9.z + :3:1201:2108[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :2:1202:2109[40100008x_104f8008x] add.f r2.x, (abs)r2.x, c19.w + :2:1203:2110[41300020x_0000001bx] floor.f r8.x, r6.w + :3:1204:2111[63870008x_00089050x] (nop2) mad.f32 r2.x, c20.x, r3.z, r2.x + :2:1205:2114[4010001bx_4020001bx] add.f r6.w, r6.w, (neg)r8.x + :4:1206:2115[80900019x_00000019x] sin r6.y, r6.y + :4:1207:2116[80b0001cx_0000001cx] cos r7.x, r7.x + :3:1208:2117[63908008x_0008001fx] mad.f32 r2.x, r7.w, r8.y, r2.x + :2:1209:2118[40701819x_10210019x] (ss)(nop1) mul.f r6.y, r6.y, c8.y + :3:1210:2120[638d801bx_10261023x] mad.f32 r6.w, c8.w, r6.w, c9.z + :2:1211:2121[4070001cx_1021001cx] mul.f r7.x, r7.x, c8.y + :2:1212:2122[40100008x_10560008x] add.f r2.x, r2.x, c21.z + :2:1213:2123[40180812x_40190012x] (nop3) add.f r4.z, r4.z, (neg)r6.y + :4:1214:2127[80b0001bx_0000001bx] cos r6.w, r6.w + :2:1215:2128[4078181bx_1021001bx] (ss)(nop3) mul.f r6.w, r6.w, c8.y + :2:1216:2132[40100018x_401b0018x] add.f r6.x, r6.x, (neg)r6.w + :2:1217:2133[4018081bx_401c002ax] (nop3) add.f r6.w, r10.z, (neg)r7.x + :2:1218:2137[4070001bx_001b001bx] mul.f r6.w, r6.w, r6.w + :2:1219:2138[40700018x_00180018x] mul.f r6.x, r6.x, r6.x + :3:1220:2139[63890812x_001b8012x] (nop3) mad.f32 r4.z, r4.z, r4.z, r6.w + :3:1221:2143[63890010x_0010102dx] mad.f32 r4.x, c11.y, r4.z, r4.x + :2:1222:2144[41300012x_0000001ex] floor.f r4.z, r7.z + :3:1223:2145[63928010x_8010903ex] (nop2) mad.f32 r4.x, c15.z, r9.y, (neg)r4.x + :2:1224:2148[40100012x_4012001ex] add.f r4.z, r7.z, (neg)r4.z + :2:1225:2149[40780010x_10270010x] (nop2) mul.f r4.x, r4.x, c9.w + :3:1226:2152[63890012x_10261023x] mad.f32 r4.z, c8.w, r4.z, c9.z + :2:1227:2153[40580c10x_10580010x] (sat)(nop3) max.f r4.x, r4.x, c22.x + :0:1228:2157[00000100x_00000000x] (rpt1)nop + :4:1229:2159[80900012x_00000012x] sin r4.z, r4.z + :2:1230:2160[40781812x_10210012x] (ss)(nop3) mul.f r4.z, r4.z, c8.y + :2:1231:2164[40180812x_40120031x] (nop3) add.f r4.z, r12.y, (neg)r4.z + :3:1232:2168[63890812x_00188012x] (nop3) mad.f32 r4.z, r4.z, r4.z, r6.x + :3:1233:2172[63890808x_0008102dx] (nop1) mad.f32 r2.x, c11.y, r4.z, r2.x + :3:1234:2174[63928808x_8008903ex] (nop3) mad.f32 r2.x, c15.z, r9.y, (neg)r2.x + :2:1235:2178[40780808x_10570008x] (nop3) mul.f r2.x, r2.x, c21.w + :2:1236:2182[40580c08x_10580008x] (sat)(nop3) max.f r2.x, r2.x, c22.x + :2:1237:2186[40180808x_00100008x] (nop3) add.f r2.x, r2.x, r4.x + :3:1238:2190[63840010x_1060105fx] mad.f32 r4.x, c23.w, r2.x, c24.x + :3:1239:2191[63840012x_105a1054x] mad.f32 r4.z, c21.x, r2.x, c22.z + :3:1240:2192[63840808x_105d105cx] (nop1) mad.f32 r2.x, c23.x, r2.x, c23.y + :2:1241:2194[40700010x_00100026x] mul.f r4.x, r9.z, r4.x + :2:1242:2195[40700012x_00120026x] mul.f r4.z, r9.z, r4.z + :2:1243:2196[40700818x_00080026x] (nop1) mul.f r6.x, r9.z, r2.x + :2:1244:2198[40700808x_0010001ax] (nop1) mul.f r2.x, r6.z, r4.x + :2:1245:2200[40700009x_00180029x] mul.f r2.y, r10.y, r6.x + :2:1246:2201[4070000ax_0012001dx] mul.f r2.z, r7.y, r4.z + :0:1247:2202[01000000x_0000000ex] jump #14 + :1:1248:2203[284cc007x_00000000x] (jp)mov.u32u32 r1.w, 0x00000000 + :0:1249:2204[00000200x_00000000x] (rpt2)nop + :1:1250:2207[200cc010x_00000007x] mov.u32u32 r4.x, r1.w + :0:1251:2208[00000200x_00000000x] (rpt2)nop + :1:1252:2211[200cc00ax_00000010x] mov.u32u32 r2.z, r4.x + :0:1253:2212[00000200x_00000000x] (rpt2)nop + :1:1254:2215[200cc010x_0000000ax] mov.u32u32 r4.x, r2.z + :0:1255:2216[00000200x_00000000x] (rpt2)nop + :1:1256:2219[200cc009x_00000010x] mov.u32u32 r2.y, r4.x + :0:1257:2220[00000200x_00000000x] (rpt2)nop + :1:1258:2223[200cc010x_00000009x] mov.u32u32 r4.x, r2.y + :0:1259:2224[00000200x_00000000x] (rpt2)nop + :1:1260:2227[200cc008x_00000010x] mov.u32u32 r2.x, r4.x + :1:1261:2228[280cc012x_00000004x] (jp)mov.u32u32 r4.z, r1.x + :1:1262:2229[200cc019x_00000009x] mov.u32u32 r6.y, r2.y + :1:1263:2230[200cc01ax_0000000ax] mov.u32u32 r6.z, r2.z + :1:1264:2231[200cc01bx_00000007x] mov.u32u32 r6.w, r1.w + :3:1265:2232[63890012x_102c102dx] mad.f32 r4.z, c11.y, r4.z, c11.x + :1:1266:2233[200cc01cx_00000003x] mov.u32u32 r7.x, r0.w + :1:1267:2234[200cc01dx_00000000x] mov.u32u32 r7.y, r0.x + :1:1268:2235[200cc01ex_00000001x] mov.u32u32 r7.z, r0.y + :2:1269:2236[40700012x_102e0012x] mul.f r4.z, r4.z, c11.z + :2:1270:2237[4010001cx_401c1022x] add.f r7.x, c8.z, (neg)r7.x + :1:1271:2238[200cc020x_00000002x] mov.u32u32 r8.x, r0.z + :2:1272:2239[40780810x_102a0023x] (nop3) mul.f r4.x, r8.w, c10.z + :4:1273:2243[8070000bx_00000012x] exp2 r2.w, r4.z + :2:1274:2244[40700010x_00230010x] mul.f r4.x, r4.x, r8.w + :1:1275:2245[200cd012x_0000000bx] (ss)mov.u32u32 r4.z, r2.w + :1:1276:2246[200cc018x_00000005x] mov.u32u32 r6.x, r1.y + :0:1277:2247[00000200x_00000000x] (rpt2)nop + :2:1278:2250[40100412x_40180012x] (sat)add.f r4.z, r4.z, (neg)r6.x + :2:1279:2251[40100010x_40101025x] add.f r4.x, c9.y, (neg)r4.x + :1:1280:2252[200cc018x_00000003x] mov.u32u32 r6.x, r0.w + :1:1281:2253[200cc022x_00000004x] mov.u32u32 r8.z, r1.x + :3:1282:2254[63890008x_0008102bx] mad.f32 r2.x, c10.w, r4.z, r2.x + :3:1283:2255[63890019x_00191061x] mad.f32 r6.y, c24.y, r4.z, r6.y + :3:1284:2256[6389001bx_001b1037x] mad.f32 r6.w, c13.w, r4.z, r6.w + :2:1285:2257[40500010x_10710010x] max.f r4.x, r4.x, c28.y + :3:1286:2258[638e0000x_001d0008x] mad.f32 r0.x, r2.x, r7.x, r7.y + :3:1287:2259[63890008x_001a1061x] mad.f32 r2.x, c24.y, r4.z, r6.z + :3:1288:2260[638e0001x_001e0019x] mad.f32 r0.y, r6.y, r7.x, r7.z + :2:1289:2261[40300010x_10500010x] min.f r4.x, r4.x, c20.x + :1:1290:2262[200cc023x_00000006x] mov.u32u32 r8.w, r1.z + :3:1291:2263[638e0002x_00200008x] mad.f32 r0.z, r2.x, r7.x, r8.x + :3:1292:2264[638e0003x_0018001bx] mad.f32 r0.w, r6.w, r7.x, r6.x + :2:1293:2265[40100004x_00100022x] add.f r1.x, r8.z, r4.x + :1:1294:2266[200cc024x_0000000bx] mov.u32u32 r9.x, r2.w + :2:1295:2267[42180006x_20010023x] (nop2) add.u r1.z, r8.w, 1 + :1:1296:2270[200cc005x_00000024x] mov.u32u32 r1.y, r9.x + :0:1297:2271[01000000x_fffffb99x] jump #-1127 + :2:1298:2272[48500401x_00010001x] (jp)(sat)max.f r0.y, r0.y, r0.y + :2:1299:2273[40500402x_00020002x] (sat)max.f r0.z, r0.z, r0.z + :2:1300:2274[40100003x_400e1022x] add.f r0.w, c8.z, (neg)r3.z + :2:1301:2275[40500400x_00000000x] (sat)max.f r0.x, r0.x, r0.x + :2:1302:2276[4070000fx_00010001x] mul.f r3.w, r0.y, r0.y + :2:1303:2277[40500006x_00010002x] max.f r1.z, r0.z, r0.y + :2:1304:2278[40500403x_102a0003x] (sat)max.f r0.w, r0.w, c10.z + :2:1305:2279[40500004x_00010000x] max.f r1.x, r0.x, r0.y + :2:1306:2280[40100005x_40020000x] add.f r1.y, r0.x, (neg)r0.z + :2:1307:2281[40300007x_00010000x] min.f r1.w, r0.x, r0.y + :2:1308:2282[4010000ex_40000002x] add.f r3.z, r0.z, (neg)r0.x + :2:1309:2283[40500004x_00020004x] max.f r1.x, r1.x, r0.z + :3:1310:2284[63828005x_00020003x] mad.f32 r1.y, r0.w, r1.y, r0.z + :2:1311:2285[40300007x_00020007x] min.f r1.w, r1.w, r0.z + :2:1312:2286[40500006x_00000006x] max.f r1.z, r1.z, r0.x + :3:1313:2287[6387000ex_00000003x] mad.f32 r3.z, r0.w, r3.z, r0.x + :2:1314:2288[40100008x_10630004x] add.f r2.x, r1.x, c24.w + :2:1315:2289[40100005x_10620005x] add.f r1.y, r1.y, c24.z + :2:1316:2290[40300002x_00010002x] min.f r0.z, r0.z, r0.y + :2:1317:2291[40100004x_40070004x] add.f r1.x, r1.x, (neg)r1.w + :3:1318:2292[6380800ax_80051021x] mad.f32 r2.z, c8.y, r0.y, (neg)r1.y + :3:1319:2293[6382800fx_000f0005x] mad.f32 r3.w, r1.y, r1.y, r3.w + :2:1320:2294[40300000x_00000002x] min.f r0.x, r0.z, r0.x + :4:1321:2295[80100008x_00000008x] rcp r2.x, r2.x + :2:1322:2296[40500007x_00010005x] max.f r1.w, r1.y, r0.y + :2:1323:2297[40100002x_400e000ax] add.f r0.z, r2.z, (neg)r3.z + :2:1324:2298[4030000cx_00010005x] min.f r3.x, r1.y, r0.y + :3:1325:2299[6387000ax_000f000ex] mad.f32 r2.z, r3.z, r3.z, r3.w + :2:1326:2300[40500007x_000e0007x] max.f r1.w, r1.w, r3.z + :2:1327:2301[40100009x_10630006x] add.f r2.y, r1.z, c24.w + :2:1328:2302[4030000cx_000e000cx] min.f r3.x, r3.x, r3.z + :2:1329:2303[40100000x_40000006x] add.f r0.x, r1.z, (neg)r0.x + :2:1330:2304[4010000fx_10630007x] add.f r3.w, r1.w, c24.w + :3:1331:2305[6382800dx_80011021x] mad.f32 r3.y, c8.y, r1.y, (neg)r0.y + :4:1332:2306[8030000ax_0000000ax] rsq r2.z, r2.z + :2:1333:2307[40100007x_400c0007x] add.f r1.w, r1.w, (neg)r3.x + :2:1334:2308[40700006x_00020002x] mul.f r1.z, r0.z, r0.z + :4:1335:2309[80100009x_00000009x] rcp r2.y, r2.y + :2:1336:2310[4010000bx_00010005x] add.f r2.w, r1.y, r0.y + :2:1337:2311[4010000dx_400e000dx] add.f r3.y, r3.y, (neg)r3.z + :2:1338:2312[40701010x_000a0001x] (ss)mul.f r4.x, r0.y, r2.z + :4:1339:2313[8010000cx_0000000fx] rcp r3.x, r3.w + :2:1340:2314[4070100fx_00090000x] (ss)mul.f r3.w, r0.x, r2.y + :2:1341:2315[4010000bx_000b000ex] add.f r2.w, r3.z, r2.w + :3:1342:2316[63840004x_800f0004x] mad.f32 r1.x, r1.x, r2.x, (neg)r3.w + :3:1343:2317[63868006x_0006000dx] mad.f32 r1.z, r3.y, r3.y, r1.z + :2:1344:2318[40700008x_000a0005x] mul.f r2.x, r1.y, r2.z + :2:1345:2319[4070000ax_000a000ex] mul.f r2.z, r3.z, r2.z + :2:1346:2320[40700803x_00040003x] (nop1) mul.f r0.w, r0.w, r1.x + :3:1347:2322[63848000x_00030000x] mad.f32 r0.x, r0.x, r2.y, r0.w + :3:1348:2323[63870003x_80011021x] mad.f32 r0.w, c8.y, r3.z, (neg)r0.y + :3:1349:2324[63860000x_80008007x] (nop2) mad.f32 r0.x, r1.w, r3.x, (neg)r0.x + :2:1350:2327[40180803x_40050003x] (nop3) add.f r0.w, r0.w, (neg)r1.y + :3:1351:2331[63818804x_00068003x] (nop3) mad.f32 r1.x, r0.w, r0.w, r1.z + :0:1352:2335[00000200x_00000000x] (rpt2)nop + :4:1353:2338[80300004x_00000004x] rsq r1.x, r1.x + :2:1354:2339[40701003x_00040003x] (ss)mul.f r0.w, r0.w, r1.x + :2:1355:2340[40700002x_00040002x] mul.f r0.z, r0.z, r1.x + :2:1356:2341[40780004x_0004000dx] (nop2) mul.f r1.x, r3.y, r1.x + :2:1357:2344[40700007x_00100002x] mul.f r1.w, r0.z, r4.x + :2:1358:2345[40700006x_00031020x] mul.f r1.z, c8.x, r0.w + :3:1359:2346[63840007x_00070004x] mad.f32 r1.w, r1.x, r2.x, r1.w + :2:1360:2347[40700002x_00021020x] mul.f r0.z, c8.x, r0.z + :2:1361:2348[40700004x_00041020x] mul.f r1.x, c8.x, r1.x + :2:1362:2349[40700006x_80000006x] mul.f r1.z, r1.z, (abs)r0.x + :3:1363:2350[63850003x_00070003x] mad.f32 r0.w, r0.w, r2.z, r1.w + :2:1364:2351[40700002x_80000002x] mul.f r0.z, r0.z, (abs)r0.x + :2:1365:2352[40700000x_80000004x] mul.f r0.x, r1.x, (abs)r0.x + :1:1366:2353[204cc007x_3f800000x] mov.u32u32 r1.w, 0x3f800000 + :2:1367:2354[40700004x_00030006x] mul.f r1.x, r1.z, r0.w + :2:1368:2355[40700002x_00030002x] mul.f r0.z, r0.z, r0.w + :2:1369:2356[40780000x_00030000x] (nop2) mul.f r0.x, r0.x, r0.w + :3:1370:2359[63858401x_00010002x] (sat)mad.f32 r0.y, r0.z, r2.w, r0.y + :3:1371:2360[63858403x_000e0004x] (sat)mad.f32 r0.w, r1.x, r2.w, r3.z + :3:1372:2361[63858400x_00050000x] (sat)mad.f32 r0.x, r0.x, r2.w, r1.y + :2:1373:2362[40100004x_40171022x] add.f r1.x, c8.z, (neg)r5.w + :2:1374:2363[40180805x_40131022x] (nop3) add.f r1.y, c8.z, (neg)r4.w + :4:1375:2367[80500002x_00000003x] log2 r0.z, r0.w + :4:1376:2368[80500001x_00000001x] log2 r0.y, r0.y + :0:1377:2369[00000000x_00000000x] nop + :4:1378:2370[80500000x_00000000x] log2 r0.x, r0.x + :2:1379:2371[40701003x_00131065x] (ss)mul.f r0.w, c25.y, r4.w + :2:1380:2372[40700002x_106c0002x] mul.f r0.z, r0.z, c27.x + :2:1381:2373[40700001x_106a0001x] mul.f r0.y, r0.y, c26.z + :2:1382:2374[40700000x_10640000x] mul.f r0.x, r0.x, c25.x + :2:1383:2375[40780803x_00170003x] (nop3) mul.f r0.w, r0.w, r5.w + :2:1384:2379[40700003x_00050003x] mul.f r0.w, r0.w, r1.y + :4:1385:2380[80700002x_00000002x] exp2 r0.z, r0.z + :4:1386:2381[80700001x_00000001x] exp2 r0.y, r0.y + :0:1387:2382[00000000x_00000000x] nop + :4:1388:2383[80700000x_00000000x] exp2 r0.x, r0.x + :2:1389:2384[40701802x_106d0002x] (ss)(nop1) mul.f r0.z, r0.z, c27.y + :2:1390:2386[40700003x_00040003x] mul.f r0.w, r0.w, r1.x + :2:1391:2387[40780801x_106b0001x] (nop3) mul.f r0.y, r0.y, c26.w + :0:1392:2391[00000100x_00000000x] (rpt1)nop + :4:1393:2393[80500003x_00000003x] log2 r0.w, r0.w + :2:1394:2394[40781803x_10680003x] (ss)(nop3) mul.f r0.w, r0.w, c26.x + :0:1395:2398[00000200x_00000000x] (rpt2)nop + :4:1396:2401[80700003x_00000003x] exp2 r0.w, r0.w + :3:1397:2402[63819803x_10509069x] (ss)(nop3) mad.f32 r0.w, c26.y, r0.w, c20.x + :2:1398:2406[40700006x_00030002x] mul.f r1.z, r0.z, r0.w + :2:1399:2407[40700005x_00030001x] mul.f r1.y, r0.y, r0.w + :2:1400:2408[40700004x_00030000x] mul.f r1.x, r0.x, r0.w + :0:1401:2409[03000000x_00000000x] end + :0:1402:2410[00000000x_00000000x] nop + :0:1403:2411[00000000x_00000000x] nop + :0:1404:2412[00000000x_00000000x] nop + :0:1405:2413[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-73 (cnt=74, max=73) + - used (merged): 0-147 (cnt=148, max=147) + - input (half): (cnt=0, max=0) + - input (full): 19-20 (cnt=2, max=20) + - const (half): (cnt=0, max=0) + - const (full): 0-1 3-5 8-9 32-113 (cnt=89, max=113) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 4-7 (cnt=4, max=7) (estimated) + - shaderdb: 2414 instructions, 1355 nops, 1059 non-nops, (1406 instlen), 0 half, 19 full + - shaderdb: 140 (ss), 0 (sy) +0000000001120164: 0000: 70348003 16320000 01013000 00000000 +t4 write VFD_CONTROL_1 (a001) + VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | 0xfc000000 } + VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } + VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } + VFD_CONTROL_4: 0xfc + VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + VFD_CONTROL_6: { 0 } +0000000001120174: 0000: 40a00186 fcfcfcfc 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000 +t4 write RB_DEPTH_PLANE_CNTL (8870) + RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } +0000000001120190: 0000: 40887001 00000000 +t4 write GRAS_SU_DEPTH_PLANE_CNTL (8094) + GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } +0000000001120198: 0000: 48809401 00000000 +t7 opcode: CP_LOAD_STATE6_FRAG (34) (88 dwords) + { DST_OFF = 8 | STATE_TYPE = ST6_CONSTANTS | STATE_SRC = SS6_DIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 21 } + { EXT_SRC_ADDR = 0 } + { EXT_SRC_ADDR_HI = 0 } +00000000011201b0: 1.500000 2.000000 1.000000 6.283185 0.159155 0.500000 -3.141593 0.400000 +00000000011201d0: 1.250000 3.000000 0.050000 0.060000 -2.200000 0.200000 1.442695 0.080000 +00000000011201f0: -0.050000 1.700000 0.660000 3.500000 0.220000 0.525000 0.175000 0.100000 +0000000001120210: 0.610000 0.750000 1.050000 0.630164 -1.696219 -0.295734 1.120000 1.343203 +0000000001120230: 0.292627 1.183843 1.081456 0.643423 -1.386068 0.570000 1.470000 1.568000 +0000000001120250: 0.324900 2.058000 2.195200 0.185193 2.881200 3.073280 0.105560 -2.500000 +0000000001120270: 0.300000 -3.750000 -0.153846 2.300000 0.045000 0.800000 0.250000 0.111111 +0000000001120290: 0.001000 0.350000 0.075000 2.200000 0.105000 0.045000 6.800000 0.049500 +00000000011202b0: 0.005000 0.110000 0.000001 0.000000 0.550000 16.000000 2160.000000 1440.000000 +00000000011202d0: 0.120000 0.700000 0.650000 0.970000 0.600000 0.900000 0.990000 2.250000 +00000000011202f0: 0.000000 0.090000 0.000000 0.000000 +00000000011201b0: 0000: 3fc00000 40000000 3f800000 40c90fdb 3e22f983 3f000000 c0490fdb 3ecccccd +00000000011201d0: 0020: 3fa00000 40400000 3d4ccccd 3d75c28f c00ccccd 3e4ccccd 3fb8aa3b 3da3d70a +00000000011201f0: 0040: bd4cccd0 3fd9999a 3f28f5c2 40600000 3e6147ae 3f066666 3e333333 3dcccccd +0000000001120210: 0060: 3f1c28f6 3f400000 3f866666 3f215273 bfd91db5 be976a6f 3f8f5c29 3fabee11 +0000000001120230: 0080: 3e95d327 3f978829 3f8a6d28 3f24b766 bfb16aad 3f11eb85 3fbc28f5 3fc8b439 +0000000001120250: 00a0: 3ea6594b 4003b646 400c7e28 3e3da33c 40386594 4044b09f 3dd82fd9 c0200000 +0000000001120270: 00c0: 3e99999a c0700000 be1d89d9 40133333 3d3851eb 3f4ccccd 3e800000 3de38e39 +0000000001120290: 00e0: 3a83126f 3eb33333 3d99999a 400ccccd 3dd70a3e 3d3851ec 40d9999a 3d4ac083 +00000000011202b0: 0100: 3ba3d70a 3de147ae 358637bd 33d6bf95 3f0ccccd 41800000 45070000 44b40000 +00000000011202d0: 0120: 3df5c28f 3f333333 3f266666 3f7851ec 3f19999a 3f666666 3f7d70a4 40100000 +00000000011202f0: 0140: 00000000 3db851ec 00000000 07ee25f4 +00000000011201a0: 0000: 70340057 05704008 00000000 00000000 3fc00000 40000000 3f800000 40c90fdb +00000000011201c0: 0020: 3e22f983 3f000000 c0490fdb 3ecccccd 3fa00000 40400000 3d4ccccd 3d75c28f +00000000011201e0: 0040: c00ccccd 3e4ccccd 3fb8aa3b 3da3d70a bd4cccd0 3fd9999a 3f28f5c2 40600000 +0000000001120200: 0060: 3e6147ae 3f066666 3e333333 3dcccccd 3f1c28f6 3f400000 3f866666 3f215273 +0000000001120220: 0080: bfd91db5 be976a6f 3f8f5c29 3fabee11 3e95d327 3f978829 3f8a6d28 3f24b766 +0000000001120240: 00a0: bfb16aad 3f11eb85 3fbc28f5 3fc8b439 3ea6594b 4003b646 400c7e28 3e3da33c +0000000001120260: 00c0: 40386594 4044b09f 3dd82fd9 c0200000 3e99999a c0700000 be1d89d9 40133333 +0000000001120280: 00e0: 3d3851eb 3f4ccccd 3e800000 3de38e39 3a83126f 3eb33333 3d99999a 400ccccd +00000000011202a0: 0100: 3dd70a3e 3d3851ec 40d9999a 3d4ac083 3ba3d70a 3de147ae 358637bd 33d6bf95 +00000000011202c0: 0120: 3f0ccccd 41800000 45070000 44b40000 3df5c28f 3f333333 3f266666 3f7851ec +00000000011202e0: 0140: 3f19999a 3f666666 3f7d70a4 40100000 00000000 3db851ec 00000000 07ee25f4 + group_id: 2 + count: 95 + addr: 0000000001121000 + flags: 0 + enable_mask: 0x1 + skipped! + + group_id: 3 + count: 18 + addr: 0000000001122000 + flags: 0 + enable_mask: 0x6 +0000000001122000: 0000: 40920008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +0000000001122020: 0020: 00000000 48920808 00000000 00000000 00000000 00000000 00000000 00000000 +* +t4 write VPC_VARYING_INTERP[0].MODE (9200) + VPC_VARYING_INTERP[0].MODE: 0 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +0000000001122000: 0000: 40920008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t4 write VPC_VARYING_PS_REPL[0].MODE (9208) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +0000000001122024: 0000: 48920808 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* + group_id: 4 + count: 5 + addr: 0000000001116030 + flags: 0 + enable_mask: 0x6 +0000000001116030: 0000: 40880b02 00000000 00000001 48a98d01 00000001 +t4 write RB_FS_OUTPUT_CNTL0 (880b) + RB_FS_OUTPUT_CNTL0: { 0 } + RB_FS_OUTPUT_CNTL1: { MRT = 1 } +0000000001116030: 0000: 40880b02 00000000 00000001 +t4 write SP_FS_OUTPUT_CNTL1 (a98d) + SP_FS_OUTPUT_CNTL1: { MRT = 1 } +000000000111603c: 0000: 48a98d01 00000001 + group_id: 7 + count: 12 + addr: 0000000001116000 + flags: 0 + enable_mask: 0x7 +0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c 48a09002 c7400000 00000001 +0000000001116020: 0020: 40a0d001 0000000f 48a00001 00000101 +t4 write VFD_FETCH[0].BASE (a010) + VFD_FETCH[0].BASE: 0x1016000 + VFD_FETCH[0].BASE+0x1: 0 + VFD_FETCH[0].SIZE: 1048576 + VFD_FETCH[0].STRIDE: 12 +0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c +t4 write VFD_DECODE[0].INSTR (a090) + VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } + VFD_DECODE[0].STEP_RATE: 0x1 +0000000001116014: 0000: 48a09002 c7400000 00000001 +t4 write VFD_DEST_CNTL[0].INSTR (a0d0) + VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } +0000000001116020: 0000: 40a0d001 0000000f +t4 write VFD_CONTROL_0 (a000) + VFD_CONTROL_0: { FETCH_CNT = 1 | DECODE_CNT = 1 } +0000000001116028: 0000: 48a00001 00000101 + group_id: 12 + count: 20 + addr: 0000000001116050 + flags: 0 + enable_mask: 0x6 +0000000001116050: 0000: 70340013 01304000 00000000 00000000 44800000 44400000 00000000 00000000 +0000000001116070: 0020: 00000000 00000000 00000000 00000000 3f800000 00000000 bf800000 44b40000 +0000000001116090: 0040: 07e56cc8 07dd3ebc 00000000 00000000 +t7 opcode: CP_LOAD_STATE6_FRAG (34) (20 dwords) + { DST_OFF = 0 | STATE_TYPE = ST6_CONSTANTS | STATE_SRC = SS6_DIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 4 } + { EXT_SRC_ADDR = 0 } + { EXT_SRC_ADDR_HI = 0 } +0000000001116060: 1024.000000 768.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 +0000000001116080: 1.000000 0.000000 -1.000000 1440.000000 0.000000 0.000000 0.000000 0.000000 +0000000001116060: 0000: 44800000 44400000 00000000 00000000 00000000 00000000 00000000 00000000 +0000000001116080: 0020: 3f800000 00000000 bf800000 44b40000 07e56cc8 07dd3ebc 00000000 00000000 +0000000001116050: 0000: 70340013 01304000 00000000 00000000 44800000 44400000 00000000 00000000 +0000000001116070: 0020: 00000000 00000000 00000000 00000000 3f800000 00000000 bf800000 44b40000 +0000000001116090: 0040: 07e56cc8 07dd3ebc 00000000 00000000 + group_id: 20 + count: 9 + addr: 00000000011160a0 + flags: 0 + enable_mask: 0x6 +00000000011160a0: 0000: 70b68003 003a0000 011160a0 00000000 48ab1a02 011160a0 00000000 48ab2001 +* +t7 opcode: CP_LOAD_STATE6 (36) (4 dwords) + { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_IBO | NUM_UNIT = 0 } + { EXT_SRC_ADDR = 0x11160a0 } + { EXT_SRC_ADDR_HI = 0 } +00000000011160a0: 0000: 70b68003 003a0000 011160a0 00000000 +t4 write SP_IBO_LO (ab1a) + SP_IBO_LO: 0x11160a0 base=1116000, offset=160, size=388 + SP_IBO_HI: 0 base=1116000, offset=160, size=388 +00000000011160b0: 0000: 48ab1a02 011160a0 00000000 +t4 write SP_IBO_COUNT (ab20) + SP_IBO_COUNT: 0 +00000000011160bc: 0000: 48ab2001 00000000 + group_id: 21 + count: 14 + addr: 0000000001123000 + flags: 0 + enable_mask: 0x7 +0000000001123000: 0000: 40800002 00000080 00000000 40809001 00000014 48809102 00100010 00000010 +0000000001123020: 0020: 40809583 00000000 00000000 00000000 409b0001 00000002 +t4 write GRAS_CL_CNTL (8000) + GRAS_CL_CNTL: { VP_CLIP_CODE_IGNORE } + GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } +0000000001123000: 0000: 40800002 00000080 00000000 +t4 write GRAS_SU_CNTL (8090) + GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 } +000000000112300c: 0000: 40809001 00000014 +t4 write GRAS_SU_POINT_MINMAX (8091) + GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + GRAS_SU_POINT_SIZE: 1.000000 +0000000001123014: 0000: 48809102 00100010 00000010 +t4 write GRAS_SU_POLY_OFFSET_SCALE (8095) + GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000 +0000000001123020: 0000: 40809583 00000000 00000000 00000000 +t4 write PC_PRIMITIVE_CNTL_0 (9b00) + PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST } +0000000001123030: 0000: 409b0001 00000002 + group_id: 22 + count: 9 + addr: 000000000111e000 + flags: 0 + enable_mask: 0x7 +000000000111e000: 0000: 40886401 00000000 40888001 00000000 48887101 00000000 48888802 00000000 +* +t4 write RB_ALPHA_CONTROL (8864) + RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } +000000000111e000: 0000: 40886401 00000000 +t4 write RB_STENCIL_CONTROL (8880) + RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } +000000000111e008: 0000: 40888001 00000000 +t4 write RB_DEPTH_CNTL (8871) + RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER } +000000000111e010: 0000: 48887101 00000000 +t4 write RB_STENCILMASK (8888) + RB_STENCILMASK: { MASK = 0 | BFMASK = 0 } + RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 } +000000000111e018: 0000: 48888802 00000000 00000000 + group_id: 23 + count: 36 + addr: 0000000001124000 + flags: 0 + enable_mask: 0x6 +0000000001124000: 0000: 48882101 00000000 40882001 000007e0 40882901 00000000 48882801 000007e0 +0000000001124020: 0020: 40883101 00000000 48883001 000007e0 48883901 00000000 40883801 000007e0 +0000000001124040: 0040: 48884101 00000000 40884001 000007e0 40884901 00000000 48884801 000007e0 +0000000001124060: 0060: 40885101 00000000 48885001 000007e0 48885901 00000000 40885801 000007e0 +0000000001124080: 0080: 40880e01 00005555 40a98901 00000100 +t4 write RB_MRT[0].BLEND_CONTROL (8821) + RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +0000000001124000: 0000: 48882101 00000000 +t4 write RB_MRT[0].CONTROL (8820) + RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +0000000001124008: 0000: 40882001 000007e0 +t4 write RB_MRT[0x1].BLEND_CONTROL (8829) + RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +0000000001124010: 0000: 40882901 00000000 +t4 write RB_MRT[0x1].CONTROL (8828) + RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +0000000001124018: 0000: 48882801 000007e0 +t4 write RB_MRT[0x2].BLEND_CONTROL (8831) + RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +0000000001124020: 0000: 40883101 00000000 +t4 write RB_MRT[0x2].CONTROL (8830) + RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +0000000001124028: 0000: 48883001 000007e0 +t4 write RB_MRT[0x3].BLEND_CONTROL (8839) + RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +0000000001124030: 0000: 48883901 00000000 +t4 write RB_MRT[0x3].CONTROL (8838) + RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +0000000001124038: 0000: 40883801 000007e0 +t4 write RB_MRT[0x4].BLEND_CONTROL (8841) + RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +0000000001124040: 0000: 48884101 00000000 +t4 write RB_MRT[0x4].CONTROL (8840) + RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +0000000001124048: 0000: 40884001 000007e0 +t4 write RB_MRT[0x5].BLEND_CONTROL (8849) + RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +0000000001124050: 0000: 40884901 00000000 +t4 write RB_MRT[0x5].CONTROL (8848) + RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +0000000001124058: 0000: 48884801 000007e0 +t4 write RB_MRT[0x6].BLEND_CONTROL (8851) + RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +0000000001124060: 0000: 40885101 00000000 +t4 write RB_MRT[0x6].CONTROL (8850) + RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +0000000001124068: 0000: 48885001 000007e0 +t4 write RB_MRT[0x7].BLEND_CONTROL (8859) + RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +0000000001124070: 0000: 48885901 00000000 +t4 write RB_MRT[0x7].CONTROL (8858) + RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +0000000001124078: 0000: 40885801 000007e0 +t4 write RB_DITHER_CNTL (880e) + RB_DITHER_CNTL: { DITHER_MODE_MRT0 = DITHER_ALWAYS | DITHER_MODE_MRT1 = DITHER_ALWAYS | DITHER_MODE_MRT2 = DITHER_ALWAYS | DITHER_MODE_MRT3 = DITHER_ALWAYS | DITHER_MODE_MRT4 = DITHER_ALWAYS | DITHER_MODE_MRT5 = DITHER_ALWAYS | DITHER_MODE_MRT6 = DITHER_ALWAYS | DITHER_MODE_MRT7 = DITHER_ALWAYS } +0000000001124080: 0000: 40880e01 00005555 +t4 write SP_BLEND_CNTL (a989) + SP_BLEND_CNTL: { UNK8 } +0000000001124088: 0000: 40a98901 00000100 +t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + { PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 4 } + mode: RM6_GMEM + skip_ib2: g=1, l=0 + draw[2] register values + + 00000001 CP_SCRATCH[0x5].REG: 1 + :0,1,17,2 +!+ 00000011 CP_SCRATCH[0x6].REG: 17 + :0,1,17,2 +!+ 00000002 CP_SCRATCH[0x7].REG: 2 + :0,1,17,2 + + 00000080 GRAS_CL_CNTL: { VP_CLIP_CODE_IGNORE } + + 00000000 GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } +!+ 000003c8 GRAS_CNTL: { SIZE | COORD_MASK = 0xf } + + 00057537 GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 311 | VERT = 349 } + + 44870000 GRAS_CL_VPORT[0].XOFFSET: 1080.000000 + + 44870000 GRAS_CL_VPORT[0].XSCALE: 1080.000000 + + 44340000 GRAS_CL_VPORT[0].YOFFSET: 720.000000 + + 44340000 GRAS_CL_VPORT[0].YSCALE: 720.000000 + + 3f000000 GRAS_CL_VPORT[0].ZOFFSET: 0.500000 + + 3f000000 GRAS_CL_VPORT[0].ZSCALE: 0.500000 + + 00000014 GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 } + + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + + 00000010 GRAS_SU_POINT_SIZE: 1.000000 + + 00000000 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } + + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000 + + 00000000 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 } + + 059f086f GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 2159 | Y = 1439 } + + 00000000 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 } + + 059f086f GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 2159 | Y = 1439 } + + 00000000 GRAS_UNKNOWN_8101: 0 + + 00000000 GRAS_SAMPLE_CNTL: { 0 } +!+ 000003c8 RB_RENDER_CONTROL0: { SIZE | COORD_MASK = 0xf } + + 00000000 RB_RENDER_CONTROL1: { 0 } + + 00000000 RB_FS_OUTPUT_CNTL0: { 0 } +!+ 00000001 RB_FS_OUTPUT_CNTL1: { MRT = 1 } +!+ 00005555 RB_DITHER_CNTL: { DITHER_MODE_MRT0 = DITHER_ALWAYS | DITHER_MODE_MRT1 = DITHER_ALWAYS | DITHER_MODE_MRT2 = DITHER_ALWAYS | DITHER_MODE_MRT3 = DITHER_ALWAYS | DITHER_MODE_MRT4 = DITHER_ALWAYS | DITHER_MODE_MRT5 = DITHER_ALWAYS | DITHER_MODE_MRT6 = DITHER_ALWAYS | DITHER_MODE_MRT7 = DITHER_ALWAYS } + + 00000000 RB_SAMPLE_CNTL: { 0 } +!+ 000007e0 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 000007e0 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 000007e0 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 000007e0 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 000007e0 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 000007e0 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 000007e0 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 000007e0 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + + 00000000 RB_BLEND_RED_F32: 0.000000 + + 00000000 RB_BLEND_GREEN_F32: 0.000000 + + 00000000 RB_BLEND_BLUE_F32: 0.000000 + + 00000000 RB_BLEND_ALPHA_F32: 0.000000 + + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } + + ffff0000 RB_BLEND_CNTL: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + + 00000000 RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } + + 00000000 RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER } + + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + + 00000000 RB_STENCILREF: { REF = 0 | BFREF = 0 } + + 00000000 RB_STENCILMASK: { MASK = 0 | BFMASK = 0 } + + 00000000 RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 } + + 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } + + 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } + + 00000000 VPC_UNKNOWN_9107: 0 + + 00000000 VPC_VARYING_INTERP[0].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + + ffffffff VPC_VAR[0].DISABLE: 0xffffffff + + ffffffff VPC_VAR[0x1].DISABLE: 0xffffffff + + ffffffff VPC_VAR[0x2].DISABLE: 0xffffffff + + ffffffff VPC_VAR[0x3].DISABLE: 0xffffffff + + 00ff0004 VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 } + + ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | UNKLOC = 255 } + + ffffffff PC_RESTART_INDEX: 4294967295 + + 00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST } + + 00000004 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 4 | CLIP_MASK = 0 } + + 00000000 PC_PRIMITIVE_CNTL_3: 0 + + 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } + + 00000101 VFD_CONTROL_0: { FETCH_CNT = 1 | DECODE_CNT = 1 } + + fcfcfcfc VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | 0xfc000000 } + + 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } + + fcfcfcfc VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } + + 000000fc VFD_CONTROL_4: 0xfc + + 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } + + 00000000 VFD_CONTROL_6: { 0 } + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 VFD_INSTANCE_START_OFFSET: 0 + + 01016000 VFD_FETCH[0].BASE: 0x1016000 + + 00000000 VFD_FETCH[0].BASE+0x1: 0 + + 00100000 VFD_FETCH[0].SIZE: 1048576 + + 0000000c VFD_FETCH[0].STRIDE: 12 + + c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } + + 00000001 VFD_DECODE[0].STEP_RATE: 0x1 + + 0000000f VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } + + 80100080 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | MERGEDREGS } + + 00000001 SP_VS_PRIMITIVE_CNTL: { OUT = 1 } + + 00000f00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + + 00000000 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } +!+ 01012000 SP_VS_OBJ_START_LO: 0x1012000 base=1012000, offset=0, size=128 + + 00000000 SP_VS_OBJ_START_HI: 0 base=1012000, offset=0, size=128 +0000000001012000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 +* + :0:0000:0000[03000000x_00000000x] end + :0:0001:0001[00000000x_00000000x] nop + :0:0002:0002[00000000x_00000000x] nop + :0:0003:0003[00000000x_00000000x] nop + :0:0004:0004[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): (cnt=0, max=0) + - used (merged): (cnt=0, max=0) + - input (half): (cnt=0, max=0) + - input (full): (cnt=0, max=0) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): (cnt=0, max=0) (estimated) + - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full + - shaderdb: 0 (ss), 0 (sy) + + 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + + 00000001 SP_VS_INSTRLEN: 1 + + 00000000 SP_HS_UNKNOWN_A831: 0 + + 00000000 SP_HS_UNKNOWN_A833: 0 + + 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + + 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } + + 00000000 SP_GS_PRIM_SIZE: 0 + + 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } +!+ 81508980 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 19 | BRANCHSTACK = 2 | THREADSIZE = FOUR_QUADS | VARYING | MERGEDREGS | 0x1000000 } + + 00000000 SP_UNKNOWN_A982: 0 +!+ 01013000 SP_FS_OBJ_START_LO: 0x1013000 base=1013000, offset=0, size=11264 + + 00000000 SP_FS_OBJ_START_HI: 0 base=1013000, offset=0, size=11264 +0000000001013000: 0000: 40400000 204cc000 00000000 204cc006 3e99999a 204cc004 20080014 42700008 +0000000001013020: 0020: 10331003 6380000c 00000006 200cc00d 00041003 40700004 00000000 20244014 +0000000001013040: 0040: 1036000c 4070000e 0000000d 200cc005 1034000c 4070000f 10251024 63820004 +0000000001013060: 0060: 10251024 6387000d 800c1003 6380000c 10251024 6387800e 00000004 41300010 +0000000001013080: 0080: 0000000d 41300011 00000005 200cc00f 0000000e 41300012 40100004 40100004 +00000000010130a0: 00a0: 4011000d 4010000d 00001003 40700011 4012000e 4010000e 10261023 63820004 +00000000010130c0: 00c0: 10261023 6386800d 20080013 42700010 10261023 6387000e 40141066 4010001b +00000000010130e0: 00e0: 00141025 40700016 00000014 80100014 20040008 46f00008 00000004 80900000 + :1:0000:0000[204cc000x_40400000x] mov.u32u32 r0.x, 0x40400000 + :1:0001:0001[204cc006x_00000000x] mov.u32u32 r1.z, 0x00000000 + :1:0002:0002[204cc004x_3e99999ax] mov.u32u32 r1.x, 0x3e99999a + :2:0003:0003[42700008x_20080014x] sub.s r2.x, r5.x, 8 + :3:0004:0004[6380000cx_10331003x] mad.f32 r3.x, c0.w, r0.x, c12.w + :1:0005:0005[200cc00dx_00000006x] mov.u32u32 r3.y, r1.z + :2:0006:0006[40700004x_00041003x] mul.f r1.x, c0.w, r1.x + :1:0007:0007[20244014x_00000000x] mov.f32f32 r5.x, c0.x + :2:0008:0008[4070000ex_1036000cx] mul.f r3.z, r3.x, c13.z + :1:0009:0009[200cc005x_0000000dx] mov.u32u32 r1.y, r3.y + :2:0010:0010[4070000fx_1034000cx] mul.f r3.w, r3.x, c13.x + :3:0011:0011[63820004x_10251024x] mad.f32 r1.x, c9.x, r1.x, c9.y + :3:0012:0012[6387000dx_10251024x] mad.f32 r3.y, c9.x, r3.z, c9.y + :3:0013:0013[6380000cx_800c1003x] mad.f32 r3.x, c0.w, r0.x, (neg)r3.x + :3:0014:0014[6387800ex_10251024x] mad.f32 r3.z, c9.x, r3.w, c9.y + :2:0015:0015[41300010x_00000004x] floor.f r4.x, r1.x + :2:0016:0016[41300011x_0000000dx] floor.f r4.y, r3.y + :1:0017:0017[200cc00fx_00000005x] mov.u32u32 r3.w, r1.y + :2:0018:0018[41300012x_0000000ex] floor.f r4.z, r3.z + :2:0019:0019[40100004x_40100004x] add.f r1.x, r1.x, (neg)r4.x + :2:0020:0020[4010000dx_4011000dx] add.f r3.y, r3.y, (neg)r4.y + :2:0021:0021[40700011x_00001003x] mul.f r4.y, c0.w, r0.x + :2:0022:0022[4010000ex_4012000ex] add.f r3.z, r3.z, (neg)r4.z + :3:0023:0023[63820004x_10261023x] mad.f32 r1.x, c8.w, r1.x, c9.z + :3:0024:0024[6386800dx_10261023x] mad.f32 r3.y, c8.w, r3.y, c9.z + :2:0025:0025[42700010x_20080013x] sub.s r4.x, r4.w, 8 + :3:0026:0026[6387000ex_10261023x] mad.f32 r3.z, c8.w, r3.z, c9.z + :2:0027:0027[4010001bx_40141066x] add.f r6.w, c25.z, (neg)r5.x + :2:0028:0028[40700016x_00141025x] mul.f r5.z, c9.y, r5.x + :4:0029:0029[80100014x_00000014x] rcp r5.x, r5.x + :2:0030:0030[46f00008x_20040008x] shr.b r2.x, r2.x, 4 + :4:0031:0031[80900000x_00000004x] sin r0.x, r1.x + :2:0032:0032[40101000x_10270000x] (ss)add.f r0.x, r0.x, c9.w + :4:0033:0033[80b00004x_0000000dx] cos r1.x, r3.y + :2:0034:0034[4078001bx_1025001bx] (nop2) mul.f r6.w, r6.w, c9.y + :2:0035:0037[40700400x_10280000x] (sat)mul.f r0.x, r0.x, c10.x + :4:0036:0038[8090100dx_0000000ex] (ss)sin r3.y, r3.z + :2:0037:0039[46f0100ex_20040010x] (ss)shr.b r3.z, r4.x, 4 + :2:0038:0040[40700010x_00041031x] mul.f r4.x, c12.y, r1.x + :1:0039:0041[200c4008x_00000008x] cov.u32f32 r2.x, r2.x + :2:0040:0042[40700012x_1021000dx] mul.f r4.z, r3.y, c8.y + :1:0041:0043[200c4004x_0000000ex] cov.u32f32 r1.x, r3.z + :2:0042:0044[4070000ex_00001021x] mul.f r3.z, c8.y, r0.x + :2:0043:0045[4070000dx_000d1031x] mul.f r3.y, c12.y, r3.y + :2:0044:0046[40100008x_10250008x] add.f r2.x, r2.x, c9.y + :2:0045:0047[40100013x_10250004x] add.f r4.w, r1.x, c9.y + :2:0046:0048[40180804x_400e1029x] (nop3) add.f r1.x, c10.y, (neg)r3.z + :2:0047:0052[40700004x_00040000x] mul.f r1.x, r0.x, r1.x + :2:0048:0053[40100017x_40160013x] add.f r5.w, r4.w, (neg)r5.z + :2:0049:0054[40100013x_401b0013x] add.f r4.w, r4.w, (neg)r6.w + :3:0050:0055[63840008x_10091008x] mad.f32 r2.x, c2.x, r2.x, c2.y + :2:0051:0056[4070000ex_00040000x] mul.f r3.z, r0.x, r1.x + :1:0052:0057[204cc004x_3fc00000x] mov.u32u32 r1.x, 0x3fc00000 + :1:0053:0058[200cc003x_0000000fx] mov.u32u32 r0.w, r3.w + :1:0054:0059[2024400fx_00000003x] mov.f32f32 r3.w, c0.w + :2:0055:0060[40700013x_00140013x] mul.f r4.w, r4.w, r5.x + :2:0056:0061[40100016x_40161004x] add.f r5.z, c1.x, (neg)r5.z + :1:0057:0062[200cc000x_00000003x] mov.u32u32 r0.x, r0.w + :3:0058:0063[6387801ax_10251024x] mad.f32 r6.z, c9.x, r3.w, c9.y + :2:0059:0064[40700019x_000f1032x] mul.f r6.y, c12.z, r3.w + :2:0060:0065[40700015x_000f1035x] mul.f r5.y, c13.y, r3.w + :1:0061:0066[200cc002x_00000000x] mov.u32u32 r0.z, r0.x + :2:0062:0067[4130001cx_0000001ax] floor.f r7.x, r6.z + :3:0063:0068[638c8019x_10251024x] mad.f32 r6.y, c9.x, r6.y, c9.y + :3:0064:0069[638a8015x_10251024x] mad.f32 r5.y, c9.x, r5.y, c9.y + :1:0065:0070[200cc000x_00000002x] mov.u32u32 r0.x, r0.z + :2:0066:0071[4018081ax_401c001ax] (nop3) add.f r6.z, r6.z, (neg)r7.x + :3:0067:0075[638d001ax_10261023x] mad.f32 r6.z, c8.w, r6.z, c9.z + :2:0068:0076[41300018x_00000015x] floor.f r6.x, r5.y + :1:0069:0077[200cc001x_00000000x] mov.u32u32 r0.y, r0.x + :0:0070:0078[00000300x_00000000x] (rpt3)nop + :4:0071:0082[80900014x_0000001ax] sin r5.x, r6.z + :2:0072:0083[4130101ax_00000019x] (ss)floor.f r6.z, r6.y + :2:0073:0084[40100015x_40180015x] add.f r5.y, r5.y, (neg)r6.x + :1:0074:0085[200cc000x_00000001x] mov.u32u32 r0.x, r0.y + :2:0075:0086[40700014x_10250014x] mul.f r5.x, r5.x, c9.y + :2:0076:0087[40100019x_401a0019x] add.f r6.y, r6.y, (neg)r6.z + :3:0077:0088[638a8015x_10269023x] (nop2) mad.f32 r5.y, c8.w, r5.y, c9.z + :3:0078:0091[638c8819x_10269023x] (nop3) mad.f32 r6.y, c8.w, r6.y, c9.z + :0:0079:0095[00000200x_00000000x] (rpt2)nop + :4:0080:0098[80900019x_00000019x] sin r6.y, r6.y + :4:0081:0099[80b00015x_00000015x] cos r5.y, r5.y + :3:0082:0100[638c9014x_00141031x] (ss)mad.f32 r5.x, c12.y, r6.y, r5.x + :3:0083:0101[638a8010x_80101031x] mad.f32 r4.x, c12.y, r5.y, (neg)r4.x + :2:0084:0102[40700815x_00151031x] (nop1) mul.f r5.y, c12.y, r5.y + :2:0085:0104[4010000dx_400d0014x] add.f r3.y, r5.x, (neg)r3.y + :2:0086:0105[40780018x_00100010x] (nop2) mul.f r6.x, r4.x, r4.x + :3:0087:0108[63868818x_0018000dx] (nop1) mad.f32 r6.x, r3.y, r3.y, r6.x + :3:0088:0110[63860818x_0018800cx] (nop3) mad.f32 r6.x, r3.x, r3.x, r6.x + :0:0089:0114[00000200x_00000000x] (rpt2)nop + :4:0090:0117[80300018x_00000018x] rsq r6.x, r6.x + :2:0091:0118[4070100cx_0018000cx] (ss)mul.f r3.x, r3.x, r6.x + :2:0092:0119[40700010x_00180010x] mul.f r4.x, r4.x, r6.x + :2:0093:0120[4070080dx_0018000dx] (nop1) mul.f r3.y, r3.y, r6.x + :2:0094:0122[40700818x_000c000cx] (nop1) mul.f r6.x, r3.x, r3.x + :3:0095:0124[63868818x_0018800dx] (nop3) mad.f32 r6.x, r3.y, r3.y, r6.x + :0:0096:0128[00000200x_00000000x] (rpt2)nop + :4:0097:0131[80300018x_00000018x] rsq r6.x, r6.x + :2:0098:0132[40701019x_0018000cx] (ss)mul.f r6.y, r3.x, r6.x + :2:0099:0133[40780018x_0018000dx] (nop2) mul.f r6.x, r3.y, r6.x + :2:0100:0136[4070001ax_000c0019x] mul.f r6.z, r6.y, r3.x + :2:0101:0137[40700019x_00100019x] mul.f r6.y, r6.y, r4.x + :3:0102:0138[6386801ax_001a0018x] mad.f32 r6.z, r6.x, r3.y, r6.z + :2:0103:0139[40780018x_00100018x] (nop2) mul.f r6.x, r6.x, r4.x + :2:0104:0142[4070081bx_001a001ax] (nop1) mul.f r6.w, r6.z, r6.z + :3:0105:0144[638c081bx_401b4018x] (nop1) mad.f32 r6.w, (neg)r6.x, (neg)r6.x, r6.w + :3:0106:0146[638c881bx_401bc019x] (nop3) mad.f32 r6.w, (neg)r6.y, (neg)r6.y, r6.w + :0:0107:0150[00000200x_00000000x] (rpt2)nop + :4:0108:0153[8030001bx_0000001bx] rsq r6.w, r6.w + :2:0109:0154[40701018x_001b0018x] (ss)mul.f r6.x, r6.x, r6.w + :2:0110:0155[4070001ax_001b001ax] mul.f r6.z, r6.z, r6.w + :2:0111:0156[40700819x_001b0019x] (nop1) mul.f r6.y, r6.y, r6.w + :2:0112:0158[4070001bx_000c0018x] mul.f r6.w, r6.x, r3.x + :2:0113:0159[4070001ex_000d001ax] mul.f r7.z, r6.z, r3.y + :2:0114:0160[4070001dx_00100019x] mul.f r7.y, r6.y, r4.x + :3:0115:0161[6386801bx_001b4019x] mad.f32 r6.w, (neg)r6.y, r3.y, r6.w + :3:0116:0162[6386001dx_001d001ax] mad.f32 r7.y, r6.z, r3.x, r7.y + :3:0117:0163[6388081ex_801e4018x] (nop1) mad.f32 r7.z, (neg)r6.x, r4.x, (neg)r7.z + :2:0118:0165[4070081cx_001b001bx] (nop1) mul.f r7.x, r6.w, r6.w + :3:0119:0167[638e881cx_001c001dx] (nop1) mad.f32 r7.x, r7.y, r7.y, r7.x + :3:0120:0169[638f081cx_001c801ex] (nop3) mad.f32 r7.x, r7.z, r7.z, r7.x + :0:0121:0173[00000200x_00000000x] (rpt2)nop + :4:0122:0176[8030001cx_0000001cx] rsq r7.x, r7.x + :2:0123:0177[4070101bx_001c001bx] (ss)mul.f r6.w, r6.w, r7.x + :2:0124:0178[4070001ex_001c001ex] mul.f r7.z, r7.z, r7.x + :2:0125:0179[4070001cx_001c001dx] mul.f r7.x, r7.y, r7.x + :1:0126:0180[2024401dx_00000001x] mov.f32f32 r7.y, c0.y + :0:0127:0181[00000200x_00000000x] (rpt2)nop + :2:0128:0184[4078001fx_001d1025x] (nop2) mul.f r7.w, c9.y, r7.y + :4:0129:0187[80100021x_0000001dx] rcp r8.y, r7.y + :2:0130:0188[4010101dx_401d1067x] (ss)add.f r7.y, c25.w, (neg)r7.y + :2:0131:0189[40100020x_401f0008x] add.f r8.x, r2.x, (neg)r7.w + :2:0132:0190[4010001fx_401f1005x] add.f r7.w, c1.y, (neg)r7.w + :2:0133:0191[40700017x_00210017x] mul.f r5.w, r5.w, r8.y + :2:0134:0192[4070001dx_1025001dx] mul.f r7.y, r7.y, c9.y + :2:0135:0193[40700020x_00210020x] mul.f r8.x, r8.x, r8.y + :2:0136:0194[40780016x_00210016x] (nop2) mul.f r5.z, r5.z, r8.y + :2:0137:0197[4070001ax_001a0020x] mul.f r6.z, r8.x, r6.z + :2:0138:0198[40700019x_00200019x] mul.f r6.y, r6.y, r8.x + :2:0139:0199[40700018x_00200018x] mul.f r6.x, r6.x, r8.x + :3:0140:0200[638d801ax_001a0017x] mad.f32 r6.z, r5.w, r6.w, r6.z + :3:0141:0201[638f0019x_80190017x] mad.f32 r6.y, r5.w, r7.z, (neg)r6.y + :3:0142:0202[638e0017x_80180017x] mad.f32 r5.w, r5.w, r7.x, (neg)r6.x + :2:0143:0203[40100008x_401d0008x] add.f r2.x, r2.x, (neg)r7.y + :2:0144:0204[40100010x_4010001ax] add.f r4.x, r6.z, (neg)r4.x + :3:0145:0205[63890012x_4016102dx] mad.f32 r4.z, c11.y, (neg)r4.z, r5.z + :2:0146:0206[4010000dx_400d0017x] add.f r3.y, r5.w, (neg)r3.y + :2:0147:0207[40700017x_00210008x] mul.f r5.w, r2.x, r8.y + :2:0148:0208[40700008x_10210016x] mul.f r2.x, r5.z, c8.y + :2:0149:0209[40700016x_00100010x] mul.f r5.z, r4.x, r4.x + :2:0150:0210[4010000cx_400c0019x] add.f r3.x, r6.y, (neg)r3.x + :3:0151:0211[63868016x_0016000dx] mad.f32 r5.z, r3.y, r3.y, r5.z + :2:0152:0212[40100014x_40080014x] add.f r5.x, r5.x, (neg)r2.x + :3:0153:0213[63890012x_10251024x] mad.f32 r4.z, c9.x, r4.z, c9.y + :3:0154:0214[63860808x_0016800cx] (nop3) mad.f32 r2.x, r3.x, r3.x, r5.z + :0:0155:0218[00000200x_00000000x] (rpt2)nop + :4:0156:0221[80300008x_00000008x] rsq r2.x, r2.x + :2:0157:0222[40701010x_00080010x] (ss)mul.f r4.x, r4.x, r2.x + :2:0158:0223[4070000cx_0008000cx] mul.f r3.x, r3.x, r2.x + :2:0159:0224[40700008x_0008000dx] mul.f r2.x, r3.y, r2.x + :2:0160:0225[4138080dx_00000012x] (nop3) floor.f r3.y, r4.z + :2:0161:0229[4018080dx_400d0012x] (nop3) add.f r3.y, r4.z, (neg)r3.y + :3:0162:0233[6386880dx_10269023x] (nop3) mad.f32 r3.y, c8.w, r3.y, c9.z + :0:0163:0237[00000200x_00000000x] (rpt2)nop + :4:0164:0240[80b00012x_0000000dx] cos r4.z, r3.y + :4:0165:0241[8090100dx_0000000dx] (ss)sin r3.y, r3.y + :2:0166:0242[40700816x_00120010x] (nop1) mul.f r5.z, r4.x, r4.z + :3:0167:0244[63869016x_40160008x] (ss)mad.f32 r5.z, r2.x, (neg)r3.y, r5.z + :2:0168:0245[4070080dx_000d0010x] (nop1) mul.f r3.y, r4.x, r3.y + :3:0169:0247[6389000dx_000d0008x] mad.f32 r3.y, r2.x, r4.z, r3.y + :1:0170:0248[280cc008x_00000006x] (jp)mov.u32u32 r2.x, r1.z + :0:0171:0249[00000200x_00000000x] (rpt2)nop + :2:0172:0252[42bb08f8x_20820008x] (nop3) cmps.s.ge p0.x, r2.x, 130 + :0:0173:0256[00000200x_00000000x] (rpt2)nop + :0:0174:0259[00800000x_00000464x] br p0.x, #1124 + :1:0175:0260[280cc008x_00000003x] (jp)mov.u32u32 r2.x, r0.w + :0:0176:0261[00000200x_00000000x] (rpt2)nop + :2:0177:0264[40b808f8x_0008106ex] (nop3) cmps.f.lt p0.x, c27.z, r2.x + :0:0178:0268[00000200x_00000000x] (rpt2)nop + :0:0179:0271[00800000x_0000045fx] br p0.x, #1119 + :1:0180:0272[280cc012x_00000004x] (jp)mov.u32u32 r4.z, r1.x + :1:0181:0273[200cc018x_00000004x] mov.u32u32 r6.x, r1.x + :1:0182:0274[200cc019x_00000004x] mov.u32u32 r6.y, r1.x + :3:0183:0275[63870010x_1037102ax] mad.f32 r4.x, c10.z, r3.z, c13.w + :3:0184:0276[63868012x_00140012x] mad.f32 r4.z, r4.z, r3.y, r5.x + :3:0185:0277[638b0018x_00150018x] mad.f32 r6.x, r6.x, r5.z, r5.y + :3:0186:0278[63860019x_00110019x] mad.f32 r6.y, r6.y, r3.x, r4.y + :3:0187:0279[63870008x_1037902dx] (nop2) mad.f32 r2.x, c11.y, r3.z, c13.w + :2:0188:0282[4070001cx_10360019x] mul.f r7.x, r6.y, c13.z + :2:0189:0283[4010001ax_10030019x] add.f r6.z, r6.y, c0.w + :2:0190:0284[4070001dx_10340019x] mul.f r7.y, r6.y, c13.x + :2:0191:0285[4070001bx_10380019x] mul.f r6.w, r6.y, c14.x + :3:0192:0286[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :3:0193:0287[638d001ax_10251024x] mad.f32 r6.z, c9.x, r6.z, c9.y + :3:0194:0288[638e881dx_10251024x] (nop1) mad.f32 r7.y, c9.x, r7.y, c9.y + :2:0195:0290[41300020x_0000001cx] floor.f r8.x, r7.x + :2:0196:0291[4130001ex_0000001ax] floor.f r7.z, r6.z + :2:0197:0292[41300822x_0000001dx] (nop1) floor.f r8.z, r7.y + :2:0198:0294[4010001cx_4020001cx] add.f r7.x, r7.x, (neg)r8.x + :2:0199:0295[4010001ax_401e001ax] add.f r6.z, r6.z, (neg)r7.z + :2:0200:0296[4010001dx_4022001dx] add.f r7.y, r7.y, (neg)r8.z + :1:0201:0297[204cc01ex_3f4ccccdx] mov.u32u32 r7.z, 0x3f4ccccd + :3:0202:0298[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :3:0203:0299[638d001ax_10261023x] mad.f32 r6.z, c8.w, r6.z, c9.z + :3:0204:0300[638e801dx_10261023x] mad.f32 r7.y, c8.w, r7.y, c9.z + :2:0205:0301[4070001ex_001e1003x] mul.f r7.z, c0.w, r7.z + :2:0206:0302[40700022x_000f104ax] mul.f r8.z, c18.z, r3.w + :3:0207:0303[638d801bx_001e1039x] mad.f32 r6.w, c14.y, r6.w, r7.z + :2:0208:0304[40700020x_000f104dx] mul.f r8.x, c19.y, r3.w + :4:0209:0305[80b0001cx_0000001cx] cos r7.x, r7.x + :2:0210:0306[4070101cx_1021001cx] (ss)mul.f r7.x, r7.x, c8.y + :4:0211:0307[8090001ax_0000001ax] sin r6.z, r6.z + :0:0212:0308[00000000x_00000000x] nop + :4:0213:0309[8090001dx_0000001dx] sin r7.y, r7.y + :3:0214:0310[638d881bx_10251024x] (nop1) mad.f32 r6.w, c9.x, r6.w, c9.y + :2:0215:0312[4010001cx_401c0018x] add.f r7.x, r6.x, (neg)r7.x + :2:0216:0313[4078101dx_1021001dx] (ss)(nop2) mul.f r7.y, r7.y, c8.y + :2:0217:0316[4070001cx_001c001cx] mul.f r7.x, r7.x, r7.x + :2:0218:0317[4018081dx_401d0012x] (nop3) add.f r7.y, r4.z, (neg)r7.y + :3:0219:0321[638e801cx_001c001dx] mad.f32 r7.x, r7.y, r7.y, r7.x + :1:0220:0322[204cc01dx_3db851ecx] mov.u32u32 r7.y, 0x3db851ec + :0:0221:0323[00000200x_00000000x] (rpt2)nop + :2:0222:0326[4070081dx_001d1003x] (nop1) mul.f r7.y, c0.w, r7.y + :3:0223:0328[6388081ax_001d801ax] (nop3) mad.f32 r6.z, r6.z, r4.x, r7.y + :3:0224:0332[638d081ax_10259024x] (nop3) mad.f32 r6.z, c9.x, r6.z, c9.y + :2:0225:0336[41380823x_0000001ax] (nop3) floor.f r8.w, r6.z + :2:0226:0340[4018081ax_4023001ax] (nop3) add.f r6.z, r6.z, (neg)r8.w + :3:0227:0344[638d081ax_10269023x] (nop3) mad.f32 r6.z, c8.w, r6.z, c9.z + :0:0228:0348[00000200x_00000000x] (rpt2)nop + :4:0229:0351[80900023x_0000001ax] sin r8.w, r6.z + :4:0230:0352[80b0101ax_0000001ax] (ss)cos r6.z, r6.z + :2:0231:0353[40700824x_00230018x] (nop1) mul.f r9.x, r6.x, r8.w + :3:0232:0355[638d1024x_00240012x] (ss)mad.f32 r9.x, r4.z, r6.z, r9.x + :2:0233:0356[4070081ax_001a0018x] (nop1) mul.f r6.z, r6.x, r6.z + :3:0234:0358[6391801ax_401a0012x] mad.f32 r6.z, r4.z, (neg)r8.w, r6.z + :2:0235:0359[40780023x_10380024x] (nop2) mul.f r8.w, r9.x, c14.x + :2:0236:0362[40700025x_1038001ax] mul.f r9.y, r6.z, c14.x + :3:0237:0363[63918023x_001e9039x] (nop2) mad.f32 r8.w, c14.y, r8.w, r7.z + :3:0238:0366[63928025x_001e1039x] mad.f32 r9.y, c14.y, r9.y, r7.z + :3:0239:0367[63918023x_10259024x] (nop2) mad.f32 r8.w, c9.x, r8.w, c9.y + :3:0240:0370[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :2:0241:0371[41380026x_00000023x] (nop2) floor.f r9.z, r8.w + :2:0242:0374[41300027x_00000025x] floor.f r9.w, r9.y + :2:0243:0375[40180023x_40260023x] (nop2) add.f r8.w, r8.w, (neg)r9.z + :2:0244:0378[40100025x_40270025x] add.f r9.y, r9.y, (neg)r9.w + :3:0245:0379[63918023x_10269023x] (nop2) mad.f32 r8.w, c8.w, r8.w, c9.z + :3:0246:0382[63928825x_10269023x] (nop3) mad.f32 r9.y, c8.w, r9.y, c9.z + :0:0247:0386[00000200x_00000000x] (rpt2)nop + :4:0248:0389[80900025x_00000025x] sin r9.y, r9.y + :4:0249:0390[80900023x_00000023x] sin r8.w, r8.w + :2:0250:0391[40701823x_00080023x] (ss)(nop1) mul.f r8.w, r8.w, r2.x + :3:0251:0393[638d001ax_00231038x] mad.f32 r6.z, c14.x, r6.z, r8.w + :2:0252:0394[40780023x_00080025x] (nop2) mul.f r8.w, r9.y, r2.x + :2:0253:0397[40700026x_103b001ax] mul.f r9.z, r6.z, c14.w + :2:0254:0398[40700027x_103f001ax] mul.f r9.w, r6.z, c15.w + :3:0255:0399[638c8023x_00231038x] mad.f32 r8.w, c14.x, r6.y, r8.w + :2:0256:0400[40700025x_1042001ax] mul.f r9.y, r6.z, c16.z + :3:0257:0401[638d081ax_10251024x] (nop1) mad.f32 r6.z, c9.x, r6.z, c9.y + :3:0258:0403[63918828x_10251024x] (nop1) mad.f32 r10.x, c9.x, r8.w, c9.y + :2:0259:0405[41300829x_0000001ax] (nop1) floor.f r10.y, r6.z + :2:0260:0407[4130082ax_00000028x] (nop1) floor.f r10.z, r10.x + :2:0261:0409[4010081ax_4029001ax] (nop1) add.f r6.z, r6.z, (neg)r10.y + :2:0262:0411[40100828x_402a0028x] (nop1) add.f r10.x, r10.x, (neg)r10.z + :3:0263:0413[638d081ax_10261023x] (nop1) mad.f32 r6.z, c8.w, r6.z, c9.z + :3:0264:0415[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0265:0419[00000000x_00000000x] nop + :4:0266:0420[80b00029x_0000001ax] cos r10.y, r6.z + :4:0267:0421[8090101ax_0000001ax] (ss)sin r6.z, r6.z + :0:0268:0422[00000100x_00000000x] (rpt1)nop + :4:0269:0424[8090002ax_00000028x] sin r10.z, r10.x + :4:0270:0425[80b01028x_00000028x] (ss)cos r10.x, r10.x + :2:0271:0426[40700029x_002a0029x] mul.f r10.y, r10.y, r10.z + :2:0272:0427[4138082ax_0000001bx] (nop3) floor.f r10.z, r6.w + :2:0273:0431[4018081bx_402a001bx] (nop3) add.f r6.w, r6.w, (neg)r10.z + :3:0274:0435[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:0275:0439[00000200x_00000000x] (rpt2)nop + :4:0276:0442[8090001bx_0000001bx] sin r6.w, r6.w + :2:0277:0443[4070181bx_0008001bx] (ss)(nop1) mul.f r6.w, r6.w, r2.x + :3:0278:0445[6392081bx_001b9038x] (nop3) mad.f32 r6.w, c14.x, r9.x, r6.w + :3:0279:0449[638d8024x_00251043x] mad.f32 r9.x, c16.w, r6.w, r9.y + :3:0280:0450[638d8025x_0026103cx] mad.f32 r9.y, c15.x, r6.w, r9.z + :3:0281:0451[63918024x_00241044x] mad.f32 r9.x, c17.x, r8.w, r9.x + :3:0282:0452[63918025x_0025103dx] mad.f32 r9.y, c15.y, r8.w, r9.y + :3:0283:0453[638d8026x_00271040x] mad.f32 r9.z, c16.x, r6.w, r9.w + :3:0284:0454[638d801bx_10251024x] mad.f32 r6.w, c9.x, r6.w, c9.y + :3:0285:0455[63918023x_00269041x] (nop2) mad.f32 r8.w, c16.y, r8.w, r9.z + :2:0286:0458[41380826x_0000001bx] (nop3) floor.f r9.z, r6.w + :2:0287:0462[4018081bx_4026001bx] (nop3) add.f r6.w, r6.w, (neg)r9.z + :3:0288:0466[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:0289:0470[00000200x_00000000x] (rpt2)nop + :4:0290:0473[80b00026x_0000001bx] cos r9.z, r6.w + :4:0291:0474[8090101bx_0000001bx] (ss)sin r6.w, r6.w + :3:0292:0475[638d081ax_00290026x] (nop1) mad.f32 r6.z, r9.z, r6.z, r10.y + :3:0293:0477[638d901ax_001a0028x] (ss)mad.f32 r6.z, r10.x, r6.w, r6.z + :2:0294:0478[4070081bx_000f103ex] (nop1) mul.f r6.w, c15.z, r3.w + :3:0295:0480[63920026x_001b103ax] mad.f32 r9.z, c14.z, r9.x, r6.w + :3:0296:0481[63928027x_001b103ax] mad.f32 r9.w, c14.z, r9.y, r6.w + :3:0297:0482[63918828x_001b103ax] (nop1) mad.f32 r10.x, c14.z, r8.w, r6.w + :3:0298:0484[63930026x_10251024x] mad.f32 r9.z, c9.x, r9.z, c9.y + :3:0299:0485[63938027x_10251024x] mad.f32 r9.w, c9.x, r9.w, c9.y + :3:0300:0486[63940828x_10251024x] (nop1) mad.f32 r10.x, c9.x, r10.x, c9.y + :2:0301:0488[41300029x_00000026x] floor.f r10.y, r9.z + :2:0302:0489[4138002ax_00000027x] (nop2) floor.f r10.z, r9.w + :2:0303:0492[40100026x_40290026x] add.f r9.z, r9.z, (neg)r10.y + :2:0304:0493[40180027x_402a0027x] (nop2) add.f r9.w, r9.w, (neg)r10.z + :3:0305:0496[63930026x_10261023x] mad.f32 r9.z, c8.w, r9.z, c9.z + :3:0306:0497[63938827x_10269023x] (nop3) mad.f32 r9.w, c8.w, r9.w, c9.z + :0:0307:0501[00000100x_00000000x] (rpt1)nop + :4:0308:0503[80900026x_00000026x] sin r9.z, r9.z + :3:0309:0504[63841025x_00250026x] (ss)mad.f32 r9.y, r9.z, r2.x, r9.y + :4:0310:0505[80900027x_00000027x] sin r9.w, r9.w + :3:0311:0506[63841023x_00238027x] (ss)(nop2) mad.f32 r8.w, r9.w, r2.x, r8.w + :2:0312:0509[40700026x_10420025x] mul.f r9.z, r9.y, c16.z + :2:0313:0510[40700029x_103f0025x] mul.f r10.y, r9.y, c15.w + :2:0314:0511[40700027x_103b0025x] mul.f r9.w, r9.y, c14.w + :3:0315:0512[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :3:0316:0513[6391802ax_10259024x] (nop2) mad.f32 r10.z, c9.x, r8.w, c9.y + :2:0317:0516[4130002bx_00000025x] floor.f r10.w, r9.y + :2:0318:0517[4138002cx_0000002ax] (nop2) floor.f r11.x, r10.z + :2:0319:0520[40100025x_402b0025x] add.f r9.y, r9.y, (neg)r10.w + :2:0320:0521[4018002ax_402c002ax] (nop2) add.f r10.z, r10.z, (neg)r11.x + :3:0321:0524[63928025x_10261023x] mad.f32 r9.y, c8.w, r9.y, c9.z + :3:0322:0525[6395082ax_10269023x] (nop3) mad.f32 r10.z, c8.w, r10.z, c9.z + :0:0323:0529[00000100x_00000000x] (rpt1)nop + :4:0324:0531[80b0002bx_00000025x] cos r10.w, r9.y + :4:0325:0532[80901025x_00000025x] (ss)sin r9.y, r9.y + :0:0326:0533[00000000x_00000000x] nop + :4:0327:0534[8090002cx_0000002ax] sin r11.x, r10.z + :4:0328:0535[80b0102ax_0000002ax] (ss)cos r10.z, r10.z + :2:0329:0536[4070002bx_002c002bx] mul.f r10.w, r10.w, r11.x + :2:0330:0537[4138082cx_00000028x] (nop3) floor.f r11.x, r10.x + :2:0331:0541[40180828x_402c0028x] (nop3) add.f r10.x, r10.x, (neg)r11.x + :3:0332:0545[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0333:0549[00000200x_00000000x] (rpt2)nop + :4:0334:0552[80900028x_00000028x] sin r10.x, r10.x + :3:0335:0553[63841824x_00248028x] (ss)(nop3) mad.f32 r9.x, r10.x, r2.x, r9.x + :3:0336:0557[63920026x_00261043x] mad.f32 r9.z, c16.w, r9.x, r9.z + :3:0337:0558[63920027x_0027103cx] mad.f32 r9.w, c15.x, r9.x, r9.w + :3:0338:0559[63920028x_00291040x] mad.f32 r10.x, c16.x, r9.x, r10.y + :3:0339:0560[63920024x_10251024x] mad.f32 r9.x, c9.x, r9.x, c9.y + :3:0340:0561[63918026x_00261044x] mad.f32 r9.z, c17.x, r8.w, r9.z + :3:0341:0562[63918027x_0027103dx] mad.f32 r9.w, c15.y, r8.w, r9.w + :3:0342:0563[63918023x_00281041x] mad.f32 r8.w, c16.y, r8.w, r10.x + :2:0343:0564[41380828x_00000024x] (nop3) floor.f r10.x, r9.x + :2:0344:0568[40180824x_40280024x] (nop3) add.f r9.x, r9.x, (neg)r10.x + :3:0345:0572[63920824x_10269023x] (nop3) mad.f32 r9.x, c8.w, r9.x, c9.z + :0:0346:0576[00000200x_00000000x] (rpt2)nop + :4:0347:0579[80b00028x_00000024x] cos r10.x, r9.x + :4:0348:0580[80901024x_00000024x] (ss)sin r9.x, r9.x + :3:0349:0581[63928825x_002b0028x] (nop1) mad.f32 r9.y, r10.x, r9.y, r10.w + :3:0350:0583[63921824x_0025802ax] (ss)(nop3) mad.f32 r9.x, r10.z, r9.x, r9.y + :2:0351:0587[40780824x_10450024x] (nop3) mul.f r9.x, r9.x, c17.y + :2:0352:0591[4010001ax_c024c01ax] add.f r6.z, (absneg)r6.z, (absneg)r9.x + :2:0353:0592[40700824x_000f1047x] (nop1) mul.f r9.x, c17.w, r3.w + :3:0354:0594[63930025x_00241046x] mad.f32 r9.y, c17.z, r9.z, r9.x + :3:0355:0595[63938028x_00241046x] mad.f32 r10.x, c17.z, r9.w, r9.x + :3:0356:0596[63918829x_00241046x] (nop1) mad.f32 r10.y, c17.z, r8.w, r9.x + :3:0357:0598[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :3:0358:0599[63940028x_10251024x] mad.f32 r10.x, c9.x, r10.x, c9.y + :3:0359:0600[63948829x_10251024x] (nop1) mad.f32 r10.y, c9.x, r10.y, c9.y + :2:0360:0602[4130002ax_00000025x] floor.f r10.z, r9.y + :2:0361:0603[4138002bx_00000028x] (nop2) floor.f r10.w, r10.x + :2:0362:0606[40100025x_402a0025x] add.f r9.y, r9.y, (neg)r10.z + :2:0363:0607[40180028x_402b0028x] (nop2) add.f r10.x, r10.x, (neg)r10.w + :3:0364:0610[63928025x_10261023x] mad.f32 r9.y, c8.w, r9.y, c9.z + :3:0365:0611[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0366:0615[00000100x_00000000x] (rpt1)nop + :4:0367:0617[80900025x_00000025x] sin r9.y, r9.y + :3:0368:0618[63841025x_00270025x] (ss)mad.f32 r9.y, r9.y, r2.x, r9.w + :4:0369:0619[80900028x_00000028x] sin r10.x, r10.x + :3:0370:0620[63841023x_00238028x] (ss)(nop2) mad.f32 r8.w, r10.x, r2.x, r8.w + :2:0371:0623[40700027x_10420025x] mul.f r9.w, r9.y, c16.z + :2:0372:0624[4070002ax_103f0025x] mul.f r10.z, r9.y, c15.w + :2:0373:0625[40700028x_103b0025x] mul.f r10.x, r9.y, c14.w + :3:0374:0626[63928025x_10251024x] mad.f32 r9.y, c9.x, r9.y, c9.y + :3:0375:0627[6391802bx_10259024x] (nop2) mad.f32 r10.w, c9.x, r8.w, c9.y + :2:0376:0630[4130002cx_00000025x] floor.f r11.x, r9.y + :2:0377:0631[4138002dx_0000002bx] (nop2) floor.f r11.y, r10.w + :2:0378:0634[40100025x_402c0025x] add.f r9.y, r9.y, (neg)r11.x + :2:0379:0635[4018002bx_402d002bx] (nop2) add.f r10.w, r10.w, (neg)r11.y + :3:0380:0638[63928025x_10261023x] mad.f32 r9.y, c8.w, r9.y, c9.z + :3:0381:0639[6395882bx_10269023x] (nop3) mad.f32 r10.w, c8.w, r10.w, c9.z + :0:0382:0643[00000100x_00000000x] (rpt1)nop + :4:0383:0645[80b0002cx_00000025x] cos r11.x, r9.y + :4:0384:0646[80901025x_00000025x] (ss)sin r9.y, r9.y + :0:0385:0647[00000000x_00000000x] nop + :4:0386:0648[8090002dx_0000002bx] sin r11.y, r10.w + :4:0387:0649[80b0102bx_0000002bx] (ss)cos r10.w, r10.w + :2:0388:0650[4070002cx_002d002cx] mul.f r11.x, r11.x, r11.y + :2:0389:0651[4138082dx_00000029x] (nop3) floor.f r11.y, r10.y + :2:0390:0655[40180829x_402d0029x] (nop3) add.f r10.y, r10.y, (neg)r11.y + :3:0391:0659[63948829x_10269023x] (nop3) mad.f32 r10.y, c8.w, r10.y, c9.z + :0:0392:0663[00000200x_00000000x] (rpt2)nop + :4:0393:0666[80900029x_00000029x] sin r10.y, r10.y + :3:0394:0667[63841826x_00268029x] (ss)(nop3) mad.f32 r9.z, r10.y, r2.x, r9.z + :3:0395:0671[63930027x_00271043x] mad.f32 r9.w, c16.w, r9.z, r9.w + :3:0396:0672[63930028x_0028103cx] mad.f32 r10.x, c15.x, r9.z, r10.x + :3:0397:0673[63930029x_002a1040x] mad.f32 r10.y, c16.x, r9.z, r10.z + :3:0398:0674[63918027x_00271044x] mad.f32 r9.w, c17.x, r8.w, r9.w + :3:0399:0675[63918028x_0028103dx] mad.f32 r10.x, c15.y, r8.w, r10.x + :3:0400:0676[63918023x_00291041x] mad.f32 r8.w, c16.y, r8.w, r10.y + :3:0401:0677[63930026x_10251024x] mad.f32 r9.z, c9.x, r9.z, c9.y + :3:0402:0678[63938029x_00221049x] mad.f32 r10.y, c18.y, r9.w, r8.z + :3:0403:0679[6394002ax_00221049x] mad.f32 r10.z, c18.y, r10.x, r8.z + :3:0404:0680[6391882dx_00221049x] (nop1) mad.f32 r11.y, c18.y, r8.w, r8.z + :3:0405:0682[63948029x_10251024x] mad.f32 r10.y, c9.x, r10.y, c9.y + :3:0406:0683[6395002ax_10251024x] mad.f32 r10.z, c9.x, r10.z, c9.y + :3:0407:0684[6396882dx_10251024x] (nop1) mad.f32 r11.y, c9.x, r11.y, c9.y + :2:0408:0686[4130002ex_00000029x] floor.f r11.z, r10.y + :2:0409:0687[4138002fx_0000002ax] (nop2) floor.f r11.w, r10.z + :2:0410:0690[40100029x_402e0029x] add.f r10.y, r10.y, (neg)r11.z + :2:0411:0691[4018002ax_402f002ax] (nop2) add.f r10.z, r10.z, (neg)r11.w + :3:0412:0694[63948029x_10261023x] mad.f32 r10.y, c8.w, r10.y, c9.z + :3:0413:0695[6395082ax_10269023x] (nop3) mad.f32 r10.z, c8.w, r10.z, c9.z + :0:0414:0699[00000100x_00000000x] (rpt1)nop + :4:0415:0701[80900029x_00000029x] sin r10.y, r10.y + :3:0416:0702[63841028x_00280029x] (ss)mad.f32 r10.x, r10.y, r2.x, r10.x + :4:0417:0703[8090002ax_0000002ax] sin r10.z, r10.z + :3:0418:0704[63841023x_0023802ax] (ss)(nop2) mad.f32 r8.w, r10.z, r2.x, r8.w + :2:0419:0707[40700029x_10420028x] mul.f r10.y, r10.x, c16.z + :2:0420:0708[4070002ex_103f0028x] mul.f r11.z, r10.x, c15.w + :3:0421:0709[6391802fx_10251024x] mad.f32 r11.w, c9.x, r8.w, c9.y + :2:0422:0710[4070002ax_103b0028x] mul.f r10.z, r10.x, c14.w + :3:0423:0711[63940828x_10251024x] (nop1) mad.f32 r10.x, c9.x, r10.x, c9.y + :2:0424:0713[41300831x_0000002fx] (nop1) floor.f r12.y, r11.w + :2:0425:0715[41300830x_00000028x] (nop1) floor.f r12.x, r10.x + :2:0426:0717[4010082fx_4031002fx] (nop1) add.f r11.w, r11.w, (neg)r12.y + :2:0427:0719[40100828x_40300028x] (nop1) add.f r10.x, r10.x, (neg)r12.x + :3:0428:0721[6397882fx_10261023x] (nop1) mad.f32 r11.w, c8.w, r11.w, c9.z + :3:0429:0723[63940828x_10269023x] (nop3) mad.f32 r10.x, c8.w, r10.x, c9.z + :0:0430:0727[00000000x_00000000x] nop + :4:0431:0728[80900031x_0000002fx] sin r12.y, r11.w + :4:0432:0729[80b0102fx_0000002fx] (ss)cos r11.w, r11.w + :0:0433:0730[00000100x_00000000x] (rpt1)nop + :4:0434:0732[80b00030x_00000028x] cos r12.x, r10.x + :4:0435:0733[80901028x_00000028x] (ss)sin r10.x, r10.x + :2:0436:0734[40700030x_00310030x] mul.f r12.x, r12.x, r12.y + :2:0437:0735[41380831x_0000002dx] (nop3) floor.f r12.y, r11.y + :2:0438:0739[4018082dx_4031002dx] (nop3) add.f r11.y, r11.y, (neg)r12.y + :3:0439:0743[6396882dx_10269023x] (nop3) mad.f32 r11.y, c8.w, r11.y, c9.z + :0:0440:0747[00000200x_00000000x] (rpt2)nop + :4:0441:0750[8090002dx_0000002dx] sin r11.y, r11.y + :3:0442:0751[63841827x_0027802dx] (ss)(nop3) mad.f32 r9.w, r11.y, r2.x, r9.w + :3:0443:0755[63938029x_00291043x] mad.f32 r10.y, c16.w, r9.w, r10.y + :3:0444:0756[6393802ax_002a103cx] mad.f32 r10.z, c15.x, r9.w, r10.z + :3:0445:0757[6393802dx_002e1040x] mad.f32 r11.y, c16.x, r9.w, r11.z + :3:0446:0758[63918029x_00291044x] mad.f32 r10.y, c17.x, r8.w, r10.y + :3:0447:0759[6391802ax_002a103dx] mad.f32 r10.z, c15.y, r8.w, r10.z + :3:0448:0760[63918023x_002d1041x] mad.f32 r8.w, c16.y, r8.w, r11.y + :3:0449:0761[63938027x_10251024x] mad.f32 r9.w, c9.x, r9.w, c9.y + :3:0450:0762[6394802dx_0020104cx] mad.f32 r11.y, c19.x, r10.y, r8.x + :3:0451:0763[6395002ex_0020104cx] mad.f32 r11.z, c19.x, r10.z, r8.x + :3:0452:0764[63918831x_0020104cx] (nop1) mad.f32 r12.y, c19.x, r8.w, r8.x + :3:0453:0766[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :3:0454:0767[6397002ex_10251024x] mad.f32 r11.z, c9.x, r11.z, c9.y + :3:0455:0768[63988831x_10251024x] (nop1) mad.f32 r12.y, c9.x, r12.y, c9.y + :2:0456:0770[41300032x_0000002dx] floor.f r12.z, r11.y + :2:0457:0771[41380033x_0000002ex] (nop2) floor.f r12.w, r11.z + :2:0458:0774[4010002dx_4032002dx] add.f r11.y, r11.y, (neg)r12.z + :2:0459:0775[4018002ex_4033002ex] (nop2) add.f r11.z, r11.z, (neg)r12.w + :3:0460:0778[6396802dx_10261023x] mad.f32 r11.y, c8.w, r11.y, c9.z + :3:0461:0779[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:0462:0783[00000100x_00000000x] (rpt1)nop + :4:0463:0785[8090002dx_0000002dx] sin r11.y, r11.y + :3:0464:0786[6384102ax_002a002dx] (ss)mad.f32 r10.z, r11.y, r2.x, r10.z + :4:0465:0787[8090002ex_0000002ex] sin r11.z, r11.z + :3:0466:0788[63841023x_0023802ex] (ss)(nop2) mad.f32 r8.w, r11.z, r2.x, r8.w + :3:0467:0791[6395002ax_10251024x] mad.f32 r10.z, c9.x, r10.z, c9.y + :3:0468:0792[63918023x_10259024x] (nop2) mad.f32 r8.w, c9.x, r8.w, c9.y + :2:0469:0795[4130002dx_0000002ax] floor.f r11.y, r10.z + :2:0470:0796[4138002ex_00000023x] (nop2) floor.f r11.z, r8.w + :2:0471:0799[4010002ax_402d002ax] add.f r10.z, r10.z, (neg)r11.y + :2:0472:0800[40180023x_402e0023x] (nop2) add.f r8.w, r8.w, (neg)r11.z + :3:0473:0803[6395002ax_10261023x] mad.f32 r10.z, c8.w, r10.z, c9.z + :3:0474:0804[63918823x_10269023x] (nop3) mad.f32 r8.w, c8.w, r8.w, c9.z + :0:0475:0808[00000100x_00000000x] (rpt1)nop + :4:0476:0810[80b0002dx_0000002ax] cos r11.y, r10.z + :4:0477:0811[8090102ax_0000002ax] (ss)sin r10.z, r10.z + :0:0478:0812[00000000x_00000000x] nop + :4:0479:0813[8090002ex_00000023x] sin r11.z, r8.w + :4:0480:0814[80b01023x_00000023x] (ss)cos r8.w, r8.w + :2:0481:0815[4070002dx_002e002dx] mul.f r11.y, r11.y, r11.z + :2:0482:0816[4138082ex_00000031x] (nop3) floor.f r11.z, r12.y + :2:0483:0820[4018082ex_402e0031x] (nop3) add.f r11.z, r12.y, (neg)r11.z + :3:0484:0824[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:0485:0828[00000200x_00000000x] (rpt2)nop + :4:0486:0831[8090002ex_0000002ex] sin r11.z, r11.z + :3:0487:0832[63841829x_0029802ex] (ss)(nop3) mad.f32 r10.y, r11.z, r2.x, r10.y + :3:0488:0836[63948829x_10259024x] (nop3) mad.f32 r10.y, c9.x, r10.y, c9.y + :2:0489:0840[4138082ex_00000029x] (nop3) floor.f r11.z, r10.y + :2:0490:0844[40180829x_402e0029x] (nop3) add.f r10.y, r10.y, (neg)r11.z + :3:0491:0848[63948829x_10269023x] (nop3) mad.f32 r10.y, c8.w, r10.y, c9.z + :0:0492:0852[00000200x_00000000x] (rpt2)nop + :4:0493:0855[80b0002ex_00000029x] cos r11.z, r10.y + :4:0494:0856[80901029x_00000029x] (ss)sin r10.y, r10.y + :3:0495:0857[6395082ax_002d002ex] (nop1) mad.f32 r10.z, r11.z, r10.z, r11.y + :3:0496:0859[63949023x_002a0023x] (ss)mad.f32 r8.w, r8.w, r10.y, r10.z + :2:0497:0860[41380829x_00000027x] (nop3) floor.f r10.y, r9.w + :2:0498:0864[40100027x_40290027x] add.f r9.w, r9.w, (neg)r10.y + :2:0499:0865[40780023x_104e0023x] (nop2) mul.f r8.w, r8.w, c19.z + :3:0500:0868[63938827x_10269023x] (nop3) mad.f32 r9.w, c8.w, r9.w, c9.z + :0:0501:0872[00000200x_00000000x] (rpt2)nop + :4:0502:0875[80b00029x_00000027x] cos r10.y, r9.w + :4:0503:0876[80901027x_00000027x] (ss)sin r9.w, r9.w + :3:0504:0877[63940828x_00300029x] (nop1) mad.f32 r10.x, r10.y, r10.x, r12.x + :3:0505:0879[63939027x_0028002fx] (ss)mad.f32 r9.w, r11.w, r9.w, r10.x + :2:0506:0880[41380828x_00000026x] (nop3) floor.f r10.x, r9.z + :2:0507:0884[40100026x_40280026x] add.f r9.z, r9.z, (neg)r10.x + :2:0508:0885[40780027x_104b0027x] (nop2) mul.f r9.w, r9.w, c18.w + :3:0509:0888[63930826x_10269023x] (nop3) mad.f32 r9.z, c8.w, r9.z, c9.z + :0:0510:0892[00000200x_00000000x] (rpt2)nop + :4:0511:0895[80b00028x_00000026x] cos r10.x, r9.z + :4:0512:0896[80901026x_00000026x] (ss)sin r9.z, r9.z + :3:0513:0897[63928825x_002c0028x] (nop1) mad.f32 r9.y, r10.x, r9.y, r11.x + :3:0514:0899[63931825x_0025802bx] (ss)(nop3) mad.f32 r9.y, r10.w, r9.z, r9.y + :2:0515:0903[40780825x_10480025x] (nop3) mul.f r9.y, r9.y, c18.x + :2:0516:0907[4018081ax_c025001ax] (nop3) add.f r6.z, r6.z, (absneg)r9.y + :2:0517:0911[4018081ax_c027001ax] (nop3) add.f r6.z, r6.z, (absneg)r9.w + :2:0518:0915[4010081ax_c023001ax] (nop1) add.f r6.z, r6.z, (absneg)r8.w + :3:0519:0917[6387081ax_001a9029x] (nop3) mad.f32 r6.z, c10.y, r3.z, r6.z + :2:0520:0921[4010081ax_104f801ax] (nop1) add.f r6.z, (abs)r6.z, c19.w + :3:0521:0923[6387081ax_001a1050x] (nop1) mad.f32 r6.z, c20.x, r3.z, r6.z + :3:0522:0925[6390881ax_001a001fx] (nop1) mad.f32 r6.z, r7.w, r8.y, r6.z + :3:0523:0927[638e081ax_001a902dx] (nop3) mad.f32 r6.z, c11.y, r7.x, r6.z + :2:0524:0931[40100025x_1056001ax] add.f r9.y, r6.z, c21.z + :2:0525:0932[40180023x_001a106fx] (nop2) add.f r8.w, c27.w, r6.z + :2:0526:0935[40b000f8x_0025106cx] cmps.f.lt p0.x, c27.x, r9.y + :2:0527:0936[40100425x_001a1030x] (sat)add.f r9.y, c12.x, r6.z + :2:0528:0937[40580023x_10700023x] (nop2) max.f r8.w, r8.w, c28.x + :2:0529:0940[40700026x_103e0025x] mul.f r9.z, r9.y, c15.z + :2:0530:0941[40300023x_10290023x] min.f r8.w, r8.w, c10.y + :0:0531:0942[00900000x_000002cdx] br !p0.x, #717 + :2:0532:0943[48100028x_10550019x] (jp)add.f r10.x, r6.y, c21.y + :2:0533:0944[40700029x_10270019x] mul.f r10.y, r6.y, c9.w + :2:0534:0945[40100019x_10590019x] add.f r6.y, r6.y, c22.y + :2:0535:0946[40700027x_00260026x] mul.f r9.w, r9.z, r9.z + :2:0536:0947[4010002ax_10590018x] add.f r10.z, r6.x, c22.y + :3:0537:0948[63948029x_10251024x] mad.f32 r10.y, c9.x, r10.y, c9.y + :2:0538:0949[4010002cx_10030019x] add.f r11.x, r6.y, c0.w + :2:0539:0950[4010002bx_10030028x] add.f r10.w, r10.x, c0.w + :2:0540:0951[40700027x_00260027x] mul.f r9.w, r9.w, r9.z + :2:0541:0952[4130002ex_00000029x] floor.f r11.z, r10.y + :3:0542:0953[6396002cx_10251024x] mad.f32 r11.x, c9.x, r11.x, c9.y + :2:0543:0954[40100018x_10550018x] add.f r6.x, r6.x, c21.y + :3:0544:0955[6395802bx_10251024x] mad.f32 r10.w, c9.x, r10.w, c9.y + :2:0545:0956[40100029x_402e0029x] add.f r10.y, r10.y, (neg)r11.z + :2:0546:0957[4130002ex_0000002cx] floor.f r11.z, r11.x + :2:0547:0958[40700007x_0027102fx] mul.f r1.w, c11.w, r9.w + :2:0548:0959[4130002fx_0000002bx] floor.f r11.w, r10.w + :3:0549:0960[63948029x_10261023x] mad.f32 r10.y, c8.w, r10.y, c9.z + :2:0550:0961[4010002cx_402e002cx] add.f r11.x, r11.x, (neg)r11.z + :2:0551:0962[4010001ax_001a1051x] add.f r6.z, c20.y, r6.z + :2:0552:0963[4010002bx_402f002bx] add.f r10.w, r10.w, (neg)r11.w + :2:0553:0964[4070002dx_10380019x] mul.f r11.y, r6.y, c14.x + :3:0554:0965[6396002cx_10261023x] mad.f32 r11.x, c8.w, r11.x, c9.z + :2:0555:0966[4070041ax_1052001ax] (sat)mul.f r6.z, r6.z, c20.z + :4:0556:0967[80900029x_00000029x] sin r10.y, r10.y + :3:0557:0968[6395802bx_10261023x] mad.f32 r10.w, c8.w, r10.w, c9.z + :3:0558:0969[6396802dx_001e1039x] mad.f32 r11.y, c14.y, r11.y, r7.z + :3:0559:0970[6394902ex_10211025x] (ss)mad.f32 r11.z, c9.y, r10.y, c8.y + :2:0560:0971[4070001ax_1053001ax] mul.f r6.z, r6.z, c20.w + :3:0561:0972[63948031x_105b1025x] mad.f32 r12.y, c9.y, r10.y, c22.w + :4:0562:0973[8090002cx_0000002cx] sin r11.x, r11.x + :3:0563:0974[638e002ex_002e1037x] mad.f32 r11.z, c13.w, r7.x, r11.z + :3:0564:0975[638e0031x_00311037x] mad.f32 r12.y, c13.w, r7.x, r12.y + :4:0565:0976[8090002bx_0000002bx] sin r10.w, r10.w + :3:0566:0977[63948029x_105e1025x] mad.f32 r10.y, c9.y, r10.y, c23.z + :3:0567:0978[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :3:0568:0979[638e001cx_00291037x] mad.f32 r7.x, c13.w, r7.x, r10.y + :3:0569:0980[63988029x_10251024x] mad.f32 r10.y, c9.x, r12.y, c9.y + :3:0570:0981[6388102bx_001d002bx] (ss)mad.f32 r10.w, r10.w, r4.x, r7.y + :3:0571:0982[63880010x_001d002cx] mad.f32 r4.x, r11.x, r4.x, r7.y + :3:0572:0983[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :2:0573:0984[41300031x_00000029x] floor.f r12.y, r10.y + :3:0574:0985[6395802bx_10251024x] mad.f32 r10.w, c9.x, r10.w, c9.y + :3:0575:0986[6397001dx_10251024x] mad.f32 r7.y, c9.x, r11.z, c9.y + :2:0576:0987[41300032x_0000001cx] floor.f r12.z, r7.x + :2:0577:0988[40100029x_40310029x] add.f r10.y, r10.y, (neg)r12.y + :2:0578:0989[40100031x_10550012x] add.f r12.y, r4.z, c21.y + :2:0579:0990[4130002cx_0000001dx] floor.f r11.x, r7.y + :2:0580:0991[4010001cx_4032001cx] add.f r7.x, r7.x, (neg)r12.z + :3:0581:0992[63948029x_10261023x] mad.f32 r10.y, c8.w, r10.y, c9.z + :3:0582:0993[63880010x_10251024x] mad.f32 r4.x, c9.x, r4.x, c9.y + :2:0583:0994[4010001dx_402c001dx] add.f r7.y, r7.y, (neg)r11.x + :3:0584:0995[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :2:0585:0996[4130002cx_0000002bx] floor.f r11.x, r10.w + :2:0586:0997[40100012x_10590012x] add.f r4.z, r4.z, c22.y + :3:0587:0998[638e801dx_10261023x] mad.f32 r7.y, c8.w, r7.y, c9.z + :4:0588:0999[80900029x_00000029x] sin r10.y, r10.y + :2:0589:1000[4130002ex_00000010x] floor.f r11.z, r4.x + :2:0590:1001[4010002bx_402c002bx] add.f r10.w, r10.w, (neg)r11.x + :3:0591:1002[63949029x_10251025x] (ss)mad.f32 r10.y, c9.y, r10.y, c9.y + :4:0592:1003[8090001cx_0000001cx] sin r7.x, r7.x + :3:0593:1004[638e101cx_10251025x] (ss)mad.f32 r7.x, c9.y, r7.x, c9.y + :2:0594:1005[40100010x_402e0010x] add.f r4.x, r4.x, (neg)r11.z + :3:0595:1006[6395802bx_10261023x] mad.f32 r10.w, c8.w, r10.w, c9.z + :4:0596:1007[8090001dx_0000001dx] sin r7.y, r7.y + :2:0597:1008[40700029x_00270029x] mul.f r10.y, r10.y, r9.w + :2:0598:1009[4070001cx_0027001cx] mul.f r7.x, r7.x, r9.w + :3:0599:1010[63880010x_10261023x] mad.f32 r4.x, c8.w, r4.x, c9.z + :3:0600:1011[638e901dx_10251025x] (ss)mad.f32 r7.y, c9.y, r7.y, c9.y + :2:0601:1012[40700829x_001a0029x] (nop1) mul.f r10.y, r10.y, r6.z + :4:0602:1014[8090002cx_0000002bx] sin r11.x, r10.w + :4:0603:1015[80b0102bx_0000002bx] (ss)cos r10.w, r10.w + :0:0604:1016[00000000x_00000000x] nop + :2:0605:1017[4070001dx_0027001dx] mul.f r7.y, r7.y, r9.w + :2:0606:1018[40700027x_002c0018x] mul.f r9.w, r6.x, r11.x + :4:0607:1019[8090002ex_00000010x] sin r11.z, r4.x + :4:0608:1020[80b01010x_00000010x] (ss)cos r4.x, r4.x + :0:0609:1021[00000000x_00000000x] nop + :3:0610:1022[63958027x_00270031x] mad.f32 r9.w, r12.y, r10.w, r9.w + :2:0611:1023[4070001dx_001a001dx] mul.f r7.y, r7.y, r6.z + :2:0612:1024[4070001ax_001a001cx] mul.f r6.z, r7.x, r6.z + :2:0613:1025[4130001cx_0000002dx] floor.f r7.x, r11.y + :2:0614:1026[4070002fx_002e002ax] mul.f r11.w, r10.z, r11.z + :2:0615:1027[40701030x_0010002ax] (ss)mul.f r12.x, r10.z, r4.x + :3:0616:1028[63880010x_002f0012x] mad.f32 r4.x, r4.z, r4.x, r11.w + :2:0617:1029[4010001cx_401c002dx] add.f r7.x, r11.y, (neg)r7.x + :2:0618:1030[4070002dx_002b0018x] mul.f r11.y, r6.x, r10.w + :3:0619:1031[6397002ex_40300012x] mad.f32 r11.z, r4.z, (neg)r11.z, r12.x + :3:0620:1032[6396002bx_402d0031x] mad.f32 r10.w, r12.y, (neg)r11.x, r11.y + :2:0621:1033[4070002cx_10380027x] mul.f r11.x, r9.w, c14.x + :3:0622:1034[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :2:0623:1035[40700030x_1038002ex] mul.f r12.x, r11.z, c14.x + :2:0624:1036[4070002dx_1038002bx] mul.f r11.y, r10.w, c14.x + :3:0625:1037[6396002cx_001e9039x] (nop2) mad.f32 r11.x, c14.y, r11.x, r7.z + :3:0626:1040[6396802dx_001e1039x] mad.f32 r11.y, c14.y, r11.y, r7.z + :4:0627:1041[8090001cx_0000001cx] sin r7.x, r7.x + :3:0628:1042[6396002cx_10251024x] mad.f32 r11.x, c9.x, r11.x, c9.y + :2:0629:1043[4070181cx_0008001cx] (ss)(nop1) mul.f r7.x, r7.x, r2.x + :3:0630:1045[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :2:0631:1046[41300032x_0000002cx] floor.f r12.z, r11.x + :3:0632:1047[6388001cx_001c1038x] mad.f32 r7.x, c14.x, r4.x, r7.x + :2:0633:1048[40700010x_10380010x] mul.f r4.x, r4.x, c14.x + :2:0634:1049[41300033x_0000002dx] floor.f r12.w, r11.y + :2:0635:1050[4018002cx_4032002cx] (nop2) add.f r11.x, r11.x, (neg)r12.z + :2:0636:1053[4010002dx_4033002dx] add.f r11.y, r11.y, (neg)r12.w + :3:0637:1054[6396002cx_10261023x] mad.f32 r11.x, c8.w, r11.x, c9.z + :3:0638:1055[63880810x_001e1039x] (nop1) mad.f32 r4.x, c14.y, r4.x, r7.z + :3:0639:1057[6396882dx_10269023x] (nop3) mad.f32 r11.y, c8.w, r11.y, c9.z + :4:0640:1061[8090002cx_0000002cx] sin r11.x, r11.x + :3:0641:1062[63880010x_10251024x] mad.f32 r4.x, c9.x, r4.x, c9.y + :2:0642:1063[4070182cx_0008002cx] (ss)(nop1) mul.f r11.x, r11.x, r2.x + :4:0643:1065[8090002dx_0000002dx] sin r11.y, r11.y + :3:0644:1066[6395802bx_002c1038x] mad.f32 r10.w, c14.x, r10.w, r11.x + :2:0645:1067[41300037x_00000010x] floor.f r13.w, r4.x + :2:0646:1068[4070182cx_0008002dx] (ss)(nop1) mul.f r11.x, r11.y, r2.x + :3:0647:1070[6394002cx_002c1038x] mad.f32 r11.x, c14.x, r10.x, r11.x + :2:0648:1071[40700032x_103b002bx] mul.f r12.z, r10.w, c14.w + :2:0649:1072[40700033x_103f002bx] mul.f r12.w, r10.w, c15.w + :2:0650:1073[4070002dx_1042002bx] mul.f r11.y, r10.w, c16.z + :3:0651:1074[63960034x_10251024x] mad.f32 r13.x, c9.x, r11.x, c9.y + :3:0652:1075[6395802bx_10251024x] mad.f32 r10.w, c9.x, r10.w, c9.y + :2:0653:1076[40100810x_40370010x] (nop1) add.f r4.x, r4.x, (neg)r13.w + :2:0654:1078[41300036x_00000034x] floor.f r13.z, r13.x + :2:0655:1079[41300035x_0000002bx] floor.f r13.y, r10.w + :3:0656:1080[63880810x_10261023x] (nop1) mad.f32 r4.x, c8.w, r4.x, c9.z + :2:0657:1082[40100034x_40360034x] add.f r13.x, r13.x, (neg)r13.z + :2:0658:1083[4018002bx_4035002bx] (nop2) add.f r10.w, r10.w, (neg)r13.y + :3:0659:1086[639a0034x_10261023x] mad.f32 r13.x, c8.w, r13.x, c9.z + :4:0660:1087[80900010x_00000010x] sin r4.x, r4.x + :3:0661:1088[6395802bx_10261023x] mad.f32 r10.w, c8.w, r10.w, c9.z + :2:0662:1089[40781810x_00080010x] (ss)(nop3) mul.f r4.x, r4.x, r2.x + :0:0663:1093[00000000x_00000000x] nop + :4:0664:1094[80900036x_00000034x] sin r13.z, r13.x + :4:0665:1095[80b01034x_00000034x] (ss)cos r13.x, r13.x + :0:0666:1096[00000000x_00000000x] nop + :4:0667:1097[80b00035x_0000002bx] cos r13.y, r10.w + :4:0668:1098[8090102bx_0000002bx] (ss)sin r10.w, r10.w + :3:0669:1099[63970010x_00101038x] mad.f32 r4.x, c14.x, r11.z, r4.x + :2:0670:1100[40700035x_00360035x] mul.f r13.y, r13.y, r13.z + :2:0671:1101[40780836x_10380028x] (nop3) mul.f r13.z, r10.x, c14.x + :3:0672:1105[639b0036x_001e1039x] mad.f32 r13.z, c14.y, r13.z, r7.z + :3:0673:1106[6398001ex_001e1039x] mad.f32 r7.z, c14.y, r12.x, r7.z + :2:0674:1107[40700037x_103b0010x] mul.f r13.w, r4.x, c14.w + :2:0675:1108[4070002ex_10420010x] mul.f r11.z, r4.x, c16.z + :3:0676:1109[638e0037x_0037103cx] mad.f32 r13.w, c15.x, r7.x, r13.w + :3:0677:1110[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :2:0678:1111[40700038x_103f0010x] mul.f r14.x, r4.x, c15.w + :3:0679:1112[638e0030x_10251024x] mad.f32 r12.x, c9.x, r7.x, c9.y + :3:0680:1113[638e002ex_002e1043x] mad.f32 r11.z, c16.w, r7.x, r11.z + :2:0681:1114[41300039x_0000001ex] floor.f r14.y, r7.z + :3:0682:1115[638e001cx_00381040x] mad.f32 r7.x, c16.x, r7.x, r14.x + :3:0683:1116[639b002fx_10251024x] mad.f32 r11.w, c9.x, r13.z, c9.y + :2:0684:1117[41300036x_00000030x] floor.f r13.z, r12.x + :2:0685:1118[4010001ex_4039001ex] add.f r7.z, r7.z, (neg)r14.y + :3:0686:1119[63880010x_10259024x] (nop2) mad.f32 r4.x, c9.x, r4.x, c9.y + :3:0687:1122[638f001ex_10261023x] mad.f32 r7.z, c8.w, r7.z, c9.z + :2:0688:1123[40100030x_40360030x] add.f r12.x, r12.x, (neg)r13.z + :2:0689:1124[41380838x_00000010x] (nop3) floor.f r14.x, r4.x + :0:0690:1128[00000000x_00000000x] nop + :4:0691:1129[8090001ex_0000001ex] sin r7.z, r7.z + :3:0692:1130[63980030x_10261023x] mad.f32 r12.x, c8.w, r12.x, c9.z + :2:0693:1131[40100010x_40380010x] add.f r4.x, r4.x, (neg)r14.x + :2:0694:1132[4070181ex_0008001ex] (ss)(nop1) mul.f r7.z, r7.z, r2.x + :3:0695:1134[638c801ex_001e1038x] mad.f32 r7.z, c14.x, r6.y, r7.z + :3:0696:1135[63880010x_10269023x] (nop2) mad.f32 r4.x, c8.w, r4.x, c9.z + :3:0697:1138[638f0037x_0037103dx] mad.f32 r13.w, c15.y, r7.z, r13.w + :4:0698:1139[80b00036x_00000030x] cos r13.z, r12.x + :4:0699:1140[80901030x_00000030x] (ss)sin r12.x, r12.x + :3:0700:1141[638f002ex_002e1044x] mad.f32 r11.z, c17.x, r7.z, r11.z + :3:0701:1142[638f081cx_001c1041x] (nop1) mad.f32 r7.x, c16.y, r7.z, r7.x + :4:0702:1144[80b00038x_00000010x] cos r14.x, r4.x + :4:0703:1145[80901010x_00000010x] (ss)sin r4.x, r4.x + :3:0704:1146[639b803ax_001b103ax] mad.f32 r14.z, c14.z, r13.w, r6.w + :3:0705:1147[63970039x_001b103ax] mad.f32 r14.y, c14.z, r11.z, r6.w + :3:0706:1148[638e003bx_001b103ax] mad.f32 r14.w, c14.z, r7.x, r6.w + :3:0707:1149[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :3:0708:1150[639d003ax_10251024x] mad.f32 r14.z, c9.x, r14.z, c9.y + :3:0709:1151[639c8039x_10251024x] mad.f32 r14.y, c9.x, r14.y, c9.y + :3:0710:1152[639d883bx_10251024x] (nop1) mad.f32 r14.w, c9.x, r14.w, c9.y + :2:0711:1154[4130003dx_0000003ax] floor.f r15.y, r14.z + :2:0712:1155[4138003cx_00000039x] (nop2) floor.f r15.x, r14.y + :2:0713:1158[4010003ax_403d003ax] add.f r14.z, r14.z, (neg)r15.y + :2:0714:1159[40180039x_403c0039x] (nop2) add.f r14.y, r14.y, (neg)r15.x + :3:0715:1162[639d003ax_10261023x] mad.f32 r14.z, c8.w, r14.z, c9.z + :3:0716:1163[639c8839x_10269023x] (nop3) mad.f32 r14.y, c8.w, r14.y, c9.z + :0:0717:1167[00000100x_00000000x] (rpt1)nop + :4:0718:1169[8090003ax_0000003ax] sin r14.z, r14.z + :3:0719:1170[6384101cx_001c003ax] (ss)mad.f32 r7.x, r14.z, r2.x, r7.x + :4:0720:1171[80900039x_00000039x] sin r14.y, r14.y + :3:0721:1172[63841037x_00378039x] (ss)(nop2) mad.f32 r13.w, r14.y, r2.x, r13.w + :3:0722:1175[638e003dx_10251024x] mad.f32 r15.y, c9.x, r7.x, c9.y + :2:0723:1176[40700039x_10420037x] mul.f r14.y, r13.w, c16.z + :2:0724:1177[4070003ax_103b0037x] mul.f r14.z, r13.w, c14.w + :2:0725:1178[4070003cx_103f0037x] mul.f r15.x, r13.w, c15.w + :2:0726:1179[4130003fx_0000003dx] floor.f r15.w, r15.y + :3:0727:1180[639b8037x_10259024x] (nop2) mad.f32 r13.w, c9.x, r13.w, c9.y + :2:0728:1183[4010003dx_403f003dx] add.f r15.y, r15.y, (neg)r15.w + :2:0729:1184[4138003ex_00000037x] (nop2) floor.f r15.z, r13.w + :3:0730:1187[639e803dx_10261023x] mad.f32 r15.y, c8.w, r15.y, c9.z + :2:0731:1188[40180837x_403e0037x] (nop3) add.f r13.w, r13.w, (neg)r15.z + :0:0732:1192[00000100x_00000000x] (rpt1)nop + :4:0733:1194[8090003fx_0000003dx] sin r15.w, r15.y + :4:0734:1195[80b0103dx_0000003dx] (ss)cos r15.y, r15.y + :3:0735:1196[639b8837x_10269023x] (nop3) mad.f32 r13.w, c8.w, r13.w, c9.z + :0:0736:1200[00000200x_00000000x] (rpt2)nop + :4:0737:1203[80b0003ex_00000037x] cos r15.z, r13.w + :4:0738:1204[80901037x_00000037x] (ss)sin r13.w, r13.w + :2:0739:1205[4070003ex_003f003ex] mul.f r15.z, r15.z, r15.w + :2:0740:1206[4138083fx_0000003bx] (nop3) floor.f r15.w, r14.w + :2:0741:1210[4018083bx_403f003bx] (nop3) add.f r14.w, r14.w, (neg)r15.w + :3:0742:1214[639d883bx_10269023x] (nop3) mad.f32 r14.w, c8.w, r14.w, c9.z + :0:0743:1218[00000200x_00000000x] (rpt2)nop + :4:0744:1221[8090003bx_0000003bx] sin r14.w, r14.w + :3:0745:1222[6384182ex_002e803bx] (ss)(nop3) mad.f32 r11.z, r14.w, r2.x, r11.z + :3:0746:1226[63970039x_00391043x] mad.f32 r14.y, c16.w, r11.z, r14.y + :3:0747:1227[6397003ax_003a103cx] mad.f32 r14.z, c15.x, r11.z, r14.z + :3:0748:1228[6397003bx_003c1040x] mad.f32 r14.w, c16.x, r11.z, r15.x + :3:0749:1229[638e0039x_00391044x] mad.f32 r14.y, c17.x, r7.x, r14.y + :3:0750:1230[638e003ax_003a103dx] mad.f32 r14.z, c15.y, r7.x, r14.z + :3:0751:1231[638e001cx_003b1041x] mad.f32 r7.x, c16.y, r7.x, r14.w + :3:0752:1232[6397002ex_10251024x] mad.f32 r11.z, c9.x, r11.z, c9.y + :3:0753:1233[639c803bx_00241046x] mad.f32 r14.w, c17.z, r14.y, r9.x + :3:0754:1234[639d003cx_00241046x] mad.f32 r15.x, c17.z, r14.z, r9.x + :3:0755:1235[638e083fx_00241046x] (nop1) mad.f32 r15.w, c17.z, r7.x, r9.x + :3:0756:1237[639d803bx_10251024x] mad.f32 r14.w, c9.x, r14.w, c9.y + :3:0757:1238[639e003cx_10251024x] mad.f32 r15.x, c9.x, r15.x, c9.y + :3:0758:1239[639f883fx_10251024x] (nop1) mad.f32 r15.w, c9.x, r15.w, c9.y + :2:0759:1241[41300040x_0000003bx] floor.f r16.x, r14.w + :2:0760:1242[41380041x_0000003cx] (nop2) floor.f r16.y, r15.x + :2:0761:1245[4010003bx_4040003bx] add.f r14.w, r14.w, (neg)r16.x + :2:0762:1246[4018003cx_4041003cx] (nop2) add.f r15.x, r15.x, (neg)r16.y + :3:0763:1249[639d803bx_10261023x] mad.f32 r14.w, c8.w, r14.w, c9.z + :3:0764:1250[639e083cx_10269023x] (nop3) mad.f32 r15.x, c8.w, r15.x, c9.z + :0:0765:1254[00000100x_00000000x] (rpt1)nop + :4:0766:1256[8090003bx_0000003bx] sin r14.w, r14.w + :3:0767:1257[6384103ax_003a003bx] (ss)mad.f32 r14.z, r14.w, r2.x, r14.z + :4:0768:1258[8090003cx_0000003cx] sin r15.x, r15.x + :3:0769:1259[6384101cx_001c803cx] (ss)(nop2) mad.f32 r7.x, r15.x, r2.x, r7.x + :2:0770:1262[4070003bx_1042003ax] mul.f r14.w, r14.z, c16.z + :2:0771:1263[40700040x_103f003ax] mul.f r16.x, r14.z, c15.w + :2:0772:1264[4070003cx_103b003ax] mul.f r15.x, r14.z, c14.w + :3:0773:1265[639d003ax_10251024x] mad.f32 r14.z, c9.x, r14.z, c9.y + :3:0774:1266[638e0041x_10259024x] (nop2) mad.f32 r16.y, c9.x, r7.x, c9.y + :2:0775:1269[41300042x_0000003ax] floor.f r16.z, r14.z + :2:0776:1270[41380043x_00000041x] (nop2) floor.f r16.w, r16.y + :2:0777:1273[4010003ax_4042003ax] add.f r14.z, r14.z, (neg)r16.z + :2:0778:1274[40180041x_40430041x] (nop2) add.f r16.y, r16.y, (neg)r16.w + :3:0779:1277[639d003ax_10261023x] mad.f32 r14.z, c8.w, r14.z, c9.z + :3:0780:1278[63a08841x_10269023x] (nop3) mad.f32 r16.y, c8.w, r16.y, c9.z + :0:0781:1282[00000100x_00000000x] (rpt1)nop + :4:0782:1284[80b00042x_0000003ax] cos r16.z, r14.z + :4:0783:1285[8090103ax_0000003ax] (ss)sin r14.z, r14.z + :0:0784:1286[00000000x_00000000x] nop + :4:0785:1287[80900043x_00000041x] sin r16.w, r16.y + :4:0786:1288[80b01041x_00000041x] (ss)cos r16.y, r16.y + :2:0787:1289[40700042x_00430042x] mul.f r16.z, r16.z, r16.w + :2:0788:1290[41380843x_0000003fx] (nop3) floor.f r16.w, r15.w + :2:0789:1294[4018083fx_4043003fx] (nop3) add.f r15.w, r15.w, (neg)r16.w + :3:0790:1298[639f883fx_10269023x] (nop3) mad.f32 r15.w, c8.w, r15.w, c9.z + :0:0791:1302[00000200x_00000000x] (rpt2)nop + :4:0792:1305[8090003fx_0000003fx] sin r15.w, r15.w + :3:0793:1306[63841839x_0039803fx] (ss)(nop3) mad.f32 r14.y, r15.w, r2.x, r14.y + :3:0794:1310[639c803bx_003b1043x] mad.f32 r14.w, c16.w, r14.y, r14.w + :3:0795:1311[639c803cx_003c103cx] mad.f32 r15.x, c15.x, r14.y, r15.x + :3:0796:1312[639c803fx_00401040x] mad.f32 r15.w, c16.x, r14.y, r16.x + :3:0797:1313[638e003bx_003b1044x] mad.f32 r14.w, c17.x, r7.x, r14.w + :3:0798:1314[638e003cx_003c103dx] mad.f32 r15.x, c15.y, r7.x, r15.x + :3:0799:1315[638e001cx_003f1041x] mad.f32 r7.x, c16.y, r7.x, r15.w + :3:0800:1316[639c8039x_10251024x] mad.f32 r14.y, c9.x, r14.y, c9.y + :3:0801:1317[639d803fx_00221049x] mad.f32 r15.w, c18.y, r14.w, r8.z + :3:0802:1318[639e0040x_00221049x] mad.f32 r16.x, c18.y, r15.x, r8.z + :3:0803:1319[638e0843x_00221049x] (nop1) mad.f32 r16.w, c18.y, r7.x, r8.z + :3:0804:1321[639f803fx_10251024x] mad.f32 r15.w, c9.x, r15.w, c9.y + :3:0805:1322[63a00040x_10251024x] mad.f32 r16.x, c9.x, r16.x, c9.y + :3:0806:1323[63a18843x_10251024x] (nop1) mad.f32 r16.w, c9.x, r16.w, c9.y + :2:0807:1325[41300044x_0000003fx] floor.f r17.x, r15.w + :2:0808:1326[41380045x_00000040x] (nop2) floor.f r17.y, r16.x + :2:0809:1329[4010003fx_4044003fx] add.f r15.w, r15.w, (neg)r17.x + :2:0810:1330[40180040x_40450040x] (nop2) add.f r16.x, r16.x, (neg)r17.y + :3:0811:1333[639f803fx_10261023x] mad.f32 r15.w, c8.w, r15.w, c9.z + :3:0812:1334[63a00840x_10269023x] (nop3) mad.f32 r16.x, c8.w, r16.x, c9.z + :0:0813:1338[00000100x_00000000x] (rpt1)nop + :4:0814:1340[8090003fx_0000003fx] sin r15.w, r15.w + :3:0815:1341[6384103cx_003c003fx] (ss)mad.f32 r15.x, r15.w, r2.x, r15.x + :4:0816:1342[80900040x_00000040x] sin r16.x, r16.x + :3:0817:1343[6384101cx_001c8040x] (ss)(nop2) mad.f32 r7.x, r16.x, r2.x, r7.x + :2:0818:1346[4070003fx_1042003cx] mul.f r15.w, r15.x, c16.z + :2:0819:1347[40700044x_103f003cx] mul.f r17.x, r15.x, c15.w + :2:0820:1348[40700040x_103b003cx] mul.f r16.x, r15.x, c14.w + :3:0821:1349[639e003cx_10251024x] mad.f32 r15.x, c9.x, r15.x, c9.y + :3:0822:1350[638e0045x_10259024x] (nop2) mad.f32 r17.y, c9.x, r7.x, c9.y + :2:0823:1353[41300046x_0000003cx] floor.f r17.z, r15.x + :2:0824:1354[41380047x_00000045x] (nop2) floor.f r17.w, r17.y + :2:0825:1357[4010003cx_4046003cx] add.f r15.x, r15.x, (neg)r17.z + :2:0826:1358[40180045x_40470045x] (nop2) add.f r17.y, r17.y, (neg)r17.w + :3:0827:1361[639e003cx_10261023x] mad.f32 r15.x, c8.w, r15.x, c9.z + :3:0828:1362[63a28845x_10269023x] (nop3) mad.f32 r17.y, c8.w, r17.y, c9.z + :0:0829:1366[00000100x_00000000x] (rpt1)nop + :4:0830:1368[80b00046x_0000003cx] cos r17.z, r15.x + :4:0831:1369[8090103cx_0000003cx] (ss)sin r15.x, r15.x + :0:0832:1370[00000000x_00000000x] nop + :4:0833:1371[80900047x_00000045x] sin r17.w, r17.y + :4:0834:1372[80b01045x_00000045x] (ss)cos r17.y, r17.y + :2:0835:1373[40700046x_00470046x] mul.f r17.z, r17.z, r17.w + :2:0836:1374[41380847x_00000043x] (nop3) floor.f r17.w, r16.w + :2:0837:1378[40180843x_40470043x] (nop3) add.f r16.w, r16.w, (neg)r17.w + :3:0838:1382[63a18843x_10269023x] (nop3) mad.f32 r16.w, c8.w, r16.w, c9.z + :0:0839:1386[00000200x_00000000x] (rpt2)nop + :4:0840:1389[80900043x_00000043x] sin r16.w, r16.w + :3:0841:1390[6384183bx_003b8043x] (ss)(nop3) mad.f32 r14.w, r16.w, r2.x, r14.w + :3:0842:1394[639d803fx_003f1043x] mad.f32 r15.w, c16.w, r14.w, r15.w + :3:0843:1395[639d8040x_0040103cx] mad.f32 r16.x, c15.x, r14.w, r16.x + :3:0844:1396[639d8043x_00441040x] mad.f32 r16.w, c16.x, r14.w, r17.x + :3:0845:1397[639d803bx_10251024x] mad.f32 r14.w, c9.x, r14.w, c9.y + :3:0846:1398[638e003fx_003f1044x] mad.f32 r15.w, c17.x, r7.x, r15.w + :3:0847:1399[638e0040x_0040103dx] mad.f32 r16.x, c15.y, r7.x, r16.x + :3:0848:1400[638e001cx_00439041x] (nop2) mad.f32 r7.x, c16.y, r7.x, r16.w + :3:0849:1403[63a00044x_0020104cx] mad.f32 r17.x, c19.x, r16.x, r8.x + :3:0850:1404[638e0047x_0020104cx] mad.f32 r17.w, c19.x, r7.x, r8.x + :3:0851:1405[639f8843x_0020104cx] (nop1) mad.f32 r16.w, c19.x, r15.w, r8.x + :3:0852:1407[63a20044x_10251024x] mad.f32 r17.x, c9.x, r17.x, c9.y + :3:0853:1408[63a38047x_10251024x] mad.f32 r17.w, c9.x, r17.w, c9.y + :3:0854:1409[63a18843x_10251024x] (nop1) mad.f32 r16.w, c9.x, r16.w, c9.y + :2:0855:1411[41300849x_00000044x] (nop1) floor.f r18.y, r17.x + :2:0856:1413[41300848x_00000043x] (nop1) floor.f r18.x, r16.w + :2:0857:1415[40100844x_40490044x] (nop1) add.f r17.x, r17.x, (neg)r18.y + :2:0858:1417[40100843x_40480043x] (nop1) add.f r16.w, r16.w, (neg)r18.x + :3:0859:1419[63a20844x_10261023x] (nop1) mad.f32 r17.x, c8.w, r17.x, c9.z + :3:0860:1421[63a18843x_10269023x] (nop3) mad.f32 r16.w, c8.w, r16.w, c9.z + :0:0861:1425[00000000x_00000000x] nop + :4:0862:1426[80900044x_00000044x] sin r17.x, r17.x + :3:0863:1427[6384181cx_001c0044x] (ss)(nop1) mad.f32 r7.x, r17.x, r2.x, r7.x + :4:0864:1429[80900043x_00000043x] sin r16.w, r16.w + :3:0865:1430[63841840x_00400043x] (ss)(nop1) mad.f32 r16.x, r16.w, r2.x, r16.x + :3:0866:1432[638e081cx_10251024x] (nop1) mad.f32 r7.x, c9.x, r7.x, c9.y + :3:0867:1434[63a00840x_10251024x] (nop1) mad.f32 r16.x, c9.x, r16.x, c9.y + :2:0868:1436[41300844x_0000001cx] (nop1) floor.f r17.x, r7.x + :2:0869:1438[41300843x_00000040x] (nop1) floor.f r16.w, r16.x + :2:0870:1440[4010081cx_4044001cx] (nop1) add.f r7.x, r7.x, (neg)r17.x + :2:0871:1442[40100840x_40430040x] (nop1) add.f r16.x, r16.x, (neg)r16.w + :3:0872:1444[638e081cx_10261023x] (nop1) mad.f32 r7.x, c8.w, r7.x, c9.z + :3:0873:1446[63a00840x_10269023x] (nop3) mad.f32 r16.x, c8.w, r16.x, c9.z + :0:0874:1450[00000000x_00000000x] nop + :4:0875:1451[80900044x_0000001cx] sin r17.x, r7.x + :4:0876:1452[80b0101cx_0000001cx] (ss)cos r7.x, r7.x + :0:0877:1453[00000100x_00000000x] (rpt1)nop + :4:0878:1455[80b00043x_00000040x] cos r16.w, r16.x + :4:0879:1456[80901040x_00000040x] (ss)sin r16.x, r16.x + :2:0880:1457[40700043x_00440043x] mul.f r16.w, r16.w, r17.x + :2:0881:1458[41380844x_00000047x] (nop3) floor.f r17.x, r17.w + :2:0882:1462[40180844x_40440047x] (nop3) add.f r17.x, r17.w, (neg)r17.x + :3:0883:1466[63a20844x_10269023x] (nop3) mad.f32 r17.x, c8.w, r17.x, c9.z + :0:0884:1470[00000200x_00000000x] (rpt2)nop + :4:0885:1473[80900044x_00000044x] sin r17.x, r17.x + :3:0886:1474[6384183fx_003f8044x] (ss)(nop3) mad.f32 r15.w, r17.x, r2.x, r15.w + :3:0887:1478[639f883fx_10259024x] (nop3) mad.f32 r15.w, c9.x, r15.w, c9.y + :2:0888:1482[41380844x_0000003fx] (nop3) floor.f r17.x, r15.w + :2:0889:1486[4018083fx_4044003fx] (nop3) add.f r15.w, r15.w, (neg)r17.x + :3:0890:1490[639f883fx_10269023x] (nop3) mad.f32 r15.w, c8.w, r15.w, c9.z + :0:0891:1494[00000200x_00000000x] (rpt2)nop + :4:0892:1497[80b00044x_0000003fx] cos r17.x, r15.w + :4:0893:1498[8090103fx_0000003fx] (ss)sin r15.w, r15.w + :3:0894:1499[63a00840x_00430044x] (nop1) mad.f32 r16.x, r17.x, r16.x, r16.w + :3:0895:1501[639f901cx_0040001cx] (ss)mad.f32 r7.x, r7.x, r15.w, r16.x + :2:0896:1502[4138083fx_0000003bx] (nop3) floor.f r15.w, r14.w + :2:0897:1506[4010003bx_403f003bx] add.f r14.w, r14.w, (neg)r15.w + :2:0898:1507[4078001cx_104e001cx] (nop2) mul.f r7.x, r7.x, c19.z + :3:0899:1510[639d883bx_10269023x] (nop3) mad.f32 r14.w, c8.w, r14.w, c9.z + :0:0900:1514[00000200x_00000000x] (rpt2)nop + :4:0901:1517[80b0003fx_0000003bx] cos r15.w, r14.w + :4:0902:1518[8090103bx_0000003bx] (ss)sin r14.w, r14.w + :3:0903:1519[639e083cx_0046003fx] (nop1) mad.f32 r15.x, r15.w, r15.x, r17.z + :3:0904:1521[639d903bx_003c0045x] (ss)mad.f32 r14.w, r17.y, r14.w, r15.x + :2:0905:1522[4138083cx_00000039x] (nop3) floor.f r15.x, r14.y + :2:0906:1526[40100039x_403c0039x] add.f r14.y, r14.y, (neg)r15.x + :2:0907:1527[4078003bx_104b003bx] (nop2) mul.f r14.w, r14.w, c18.w + :3:0908:1530[639c8839x_10269023x] (nop3) mad.f32 r14.y, c8.w, r14.y, c9.z + :0:0909:1534[00000200x_00000000x] (rpt2)nop + :4:0910:1537[80b0003cx_00000039x] cos r15.x, r14.y + :4:0911:1538[80901039x_00000039x] (ss)sin r14.y, r14.y + :3:0912:1539[639d083ax_0042003cx] (nop1) mad.f32 r14.z, r15.x, r14.z, r16.z + :3:0913:1541[639c9039x_003a0041x] (ss)mad.f32 r14.y, r16.y, r14.y, r14.z + :2:0914:1542[4138083ax_0000002ex] (nop3) floor.f r14.z, r11.z + :2:0915:1546[4010002ex_403a002ex] add.f r11.z, r11.z, (neg)r14.z + :2:0916:1547[40780039x_10480039x] (nop2) mul.f r14.y, r14.y, c18.x + :3:0917:1550[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:0918:1554[00000200x_00000000x] (rpt2)nop + :4:0919:1557[80b0003ax_0000002ex] cos r14.z, r11.z + :4:0920:1558[8090102ex_0000002ex] (ss)sin r11.z, r11.z + :3:0921:1559[639b8837x_003e003ax] (nop1) mad.f32 r13.w, r14.z, r13.w, r15.z + :3:0922:1561[6397102ex_0037003dx] (ss)mad.f32 r11.z, r15.y, r11.z, r13.w + :2:0923:1562[41380837x_0000001ex] (nop3) floor.f r13.w, r7.z + :2:0924:1566[4010001ex_4037001ex] add.f r7.z, r7.z, (neg)r13.w + :2:0925:1567[4078002ex_1045002ex] (nop2) mul.f r11.z, r11.z, c17.y + :3:0926:1570[638f081ex_10269023x] (nop3) mad.f32 r7.z, c8.w, r7.z, c9.z + :0:0927:1574[00000200x_00000000x] (rpt2)nop + :4:0928:1577[80900037x_0000001ex] sin r13.w, r7.z + :4:0929:1578[80b0101ex_0000001ex] (ss)cos r7.z, r7.z + :2:0930:1579[40700837x_00370038x] (nop1) mul.f r13.w, r14.x, r13.w + :3:0931:1581[63880810x_00370036x] (nop1) mad.f32 r4.x, r13.z, r4.x, r13.w + :3:0932:1583[63981810x_0010801ex] (ss)(nop3) mad.f32 r4.x, r7.z, r12.x, r4.x + :2:0933:1587[40180810x_c02ec010x] (nop3) add.f r4.x, (absneg)r4.x, (absneg)r11.z + :2:0934:1591[40180810x_c0390010x] (nop3) add.f r4.x, r4.x, (absneg)r14.y + :2:0935:1595[40180810x_c03b0010x] (nop3) add.f r4.x, r4.x, (absneg)r14.w + :2:0936:1599[40100010x_c01c0010x] add.f r4.x, r4.x, (absneg)r7.x + :2:0937:1600[4130001cx_0000002fx] floor.f r7.x, r11.w + :3:0938:1601[63870010x_00109029x] (nop2) mad.f32 r4.x, c10.y, r3.z, r4.x + :2:0939:1604[4010001cx_401c002fx] add.f r7.x, r11.w, (neg)r7.x + :2:0940:1605[40180010x_104f8010x] (nop2) add.f r4.x, (abs)r4.x, c19.w + :3:0941:1608[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :3:0942:1609[63870810x_00109050x] (nop3) mad.f32 r4.x, c20.x, r3.z, r4.x + :0:0943:1613[00000100x_00000000x] (rpt1)nop + :4:0944:1615[8090001cx_0000001cx] sin r7.x, r7.x + :3:0945:1616[63908010x_0010001fx] mad.f32 r4.x, r7.w, r8.y, r4.x + :2:0946:1617[4070181cx_0008001cx] (ss)(nop1) mul.f r7.x, r7.x, r2.x + :3:0947:1619[6393801cx_001c1038x] mad.f32 r7.x, c14.x, r9.w, r7.x + :2:0948:1620[40180010x_10560010x] (nop2) add.f r4.x, r4.x, c21.z + :3:0949:1623[638e0027x_0032103cx] mad.f32 r9.w, c15.x, r7.x, r12.z + :3:0950:1624[638e001ex_002d1043x] mad.f32 r7.z, c16.w, r7.x, r11.y + :3:0951:1625[63960027x_0027103dx] mad.f32 r9.w, c15.y, r11.x, r9.w + :3:0952:1626[638e002dx_00331040x] mad.f32 r11.y, c16.x, r7.x, r12.w + :3:0953:1627[6396001ex_001e1044x] mad.f32 r7.z, c17.x, r11.x, r7.z + :3:0954:1628[6396002cx_002d1041x] mad.f32 r11.x, c16.y, r11.x, r11.y + :3:0955:1629[6393802ex_001b103ax] mad.f32 r11.z, c14.z, r9.w, r6.w + :3:0956:1630[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :3:0957:1631[638f002dx_001b103ax] mad.f32 r11.y, c14.z, r7.z, r6.w + :3:0958:1632[6396001bx_001b103ax] mad.f32 r6.w, c14.z, r11.x, r6.w + :3:0959:1633[6397082ex_10259024x] (nop3) mad.f32 r11.z, c9.x, r11.z, c9.y + :2:0960:1637[41300030x_0000002ex] floor.f r12.x, r11.z + :3:0961:1638[6396802dx_10251024x] mad.f32 r11.y, c9.x, r11.y, c9.y + :3:0962:1639[638d881bx_10251024x] (nop1) mad.f32 r6.w, c9.x, r6.w, c9.y + :2:0963:1641[4010002ex_4030002ex] add.f r11.z, r11.z, (neg)r12.x + :2:0964:1642[4138002fx_0000002dx] (nop2) floor.f r11.w, r11.y + :3:0965:1645[6397002ex_10261023x] mad.f32 r11.z, c8.w, r11.z, c9.z + :2:0966:1646[4018082dx_402f002dx] (nop3) add.f r11.y, r11.y, (neg)r11.w + :0:0967:1650[00000100x_00000000x] (rpt1)nop + :4:0968:1652[8090002ex_0000002ex] sin r11.z, r11.z + :3:0969:1653[6396802dx_10261023x] mad.f32 r11.y, c8.w, r11.y, c9.z + :3:0970:1654[6384182cx_002c802ex] (ss)(nop3) mad.f32 r11.x, r11.z, r2.x, r11.x + :3:0971:1658[63960830x_10259024x] (nop3) mad.f32 r12.x, c9.x, r11.x, c9.y + :2:0972:1662[41300033x_00000030x] floor.f r12.w, r12.x + :4:0973:1663[8090002dx_0000002dx] sin r11.y, r11.y + :3:0974:1664[63841027x_0027802dx] (ss)(nop2) mad.f32 r9.w, r11.y, r2.x, r9.w + :2:0975:1667[40100030x_40330030x] add.f r12.x, r12.x, (neg)r12.w + :2:0976:1668[4070002dx_10420027x] mul.f r11.y, r9.w, c16.z + :2:0977:1669[4070002ex_103b0027x] mul.f r11.z, r9.w, c14.w + :2:0978:1670[4070002fx_103f0027x] mul.f r11.w, r9.w, c15.w + :3:0979:1671[63980030x_10261023x] mad.f32 r12.x, c8.w, r12.x, c9.z + :3:0980:1672[63938827x_10259024x] (nop3) mad.f32 r9.w, c9.x, r9.w, c9.y + :0:0981:1676[00000100x_00000000x] (rpt1)nop + :4:0982:1678[80900033x_00000030x] sin r12.w, r12.x + :4:0983:1679[80b01030x_00000030x] (ss)cos r12.x, r12.x + :2:0984:1680[41380832x_00000027x] (nop3) floor.f r12.z, r9.w + :2:0985:1684[40180827x_40320027x] (nop3) add.f r9.w, r9.w, (neg)r12.z + :3:0986:1688[63938827x_10269023x] (nop3) mad.f32 r9.w, c8.w, r9.w, c9.z + :0:0987:1692[00000200x_00000000x] (rpt2)nop + :4:0988:1695[80b00032x_00000027x] cos r12.z, r9.w + :4:0989:1696[80901027x_00000027x] (ss)sin r9.w, r9.w + :2:0990:1697[40700032x_00330032x] mul.f r12.z, r12.z, r12.w + :2:0991:1698[41380833x_0000001bx] (nop3) floor.f r12.w, r6.w + :2:0992:1702[4018081bx_4033001bx] (nop3) add.f r6.w, r6.w, (neg)r12.w + :3:0993:1706[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:0994:1710[00000200x_00000000x] (rpt2)nop + :4:0995:1713[8090001bx_0000001bx] sin r6.w, r6.w + :3:0996:1714[6384181bx_001e801bx] (ss)(nop3) mad.f32 r6.w, r6.w, r2.x, r7.z + :3:0997:1718[638d801ex_002d1043x] mad.f32 r7.z, c16.w, r6.w, r11.y + :3:0998:1719[638d802dx_002e103cx] mad.f32 r11.y, c15.x, r6.w, r11.z + :3:0999:1720[6396001ex_001e1044x] mad.f32 r7.z, c17.x, r11.x, r7.z + :3:1000:1721[6396002dx_002d103dx] mad.f32 r11.y, c15.y, r11.x, r11.y + :3:1001:1722[638d802ex_002f1040x] mad.f32 r11.z, c16.x, r6.w, r11.w + :3:1002:1723[638d801bx_10251024x] mad.f32 r6.w, c9.x, r6.w, c9.y + :3:1003:1724[6396002cx_002e1041x] mad.f32 r11.x, c16.y, r11.x, r11.z + :3:1004:1725[6396802fx_00241046x] mad.f32 r11.w, c17.z, r11.y, r9.x + :3:1005:1726[638f002ex_00249046x] (nop2) mad.f32 r11.z, c17.z, r7.z, r9.x + :3:1006:1729[6397802fx_10251024x] mad.f32 r11.w, c9.x, r11.w, c9.y + :3:1007:1730[63960024x_00241046x] mad.f32 r9.x, c17.z, r11.x, r9.x + :3:1008:1731[6397082ex_10251024x] (nop1) mad.f32 r11.z, c9.x, r11.z, c9.y + :2:1009:1733[41300036x_0000002fx] floor.f r13.z, r11.w + :3:1010:1734[63920024x_10251024x] mad.f32 r9.x, c9.x, r9.x, c9.y + :2:1011:1735[41300833x_0000002ex] (nop1) floor.f r12.w, r11.z + :2:1012:1737[4018082fx_4036002fx] (nop3) add.f r11.w, r11.w, (neg)r13.z + :3:1013:1741[6397802fx_10261023x] mad.f32 r11.w, c8.w, r11.w, c9.z + :2:1014:1742[4018082ex_4033002ex] (nop3) add.f r11.z, r11.z, (neg)r12.w + :0:1015:1746[00000100x_00000000x] (rpt1)nop + :4:1016:1748[8090002fx_0000002fx] sin r11.w, r11.w + :3:1017:1749[6397002ex_10261023x] mad.f32 r11.z, c8.w, r11.z, c9.z + :3:1018:1750[6384182cx_002c802fx] (ss)(nop3) mad.f32 r11.x, r11.w, r2.x, r11.x + :3:1019:1754[63960836x_10259024x] (nop3) mad.f32 r13.z, c9.x, r11.x, c9.y + :2:1020:1758[41300038x_00000036x] floor.f r14.x, r13.z + :4:1021:1759[8090002ex_0000002ex] sin r11.z, r11.z + :3:1022:1760[6384102dx_002d802ex] (ss)(nop2) mad.f32 r11.y, r11.z, r2.x, r11.y + :2:1023:1763[40100036x_40380036x] add.f r13.z, r13.z, (neg)r14.x + :2:1024:1764[4070002ex_1042002dx] mul.f r11.z, r11.y, c16.z + :2:1025:1765[4070002fx_103b002dx] mul.f r11.w, r11.y, c14.w + :2:1026:1766[40700033x_103f002dx] mul.f r12.w, r11.y, c15.w + :3:1027:1767[639b0036x_10261023x] mad.f32 r13.z, c8.w, r13.z, c9.z + :3:1028:1768[6396882dx_10259024x] (nop3) mad.f32 r11.y, c9.x, r11.y, c9.y + :0:1029:1772[00000100x_00000000x] (rpt1)nop + :4:1030:1774[80900038x_00000036x] sin r14.x, r13.z + :4:1031:1775[80b01036x_00000036x] (ss)cos r13.z, r13.z + :2:1032:1776[41380837x_0000002dx] (nop3) floor.f r13.w, r11.y + :2:1033:1780[4018082dx_4037002dx] (nop3) add.f r11.y, r11.y, (neg)r13.w + :3:1034:1784[6396882dx_10269023x] (nop3) mad.f32 r11.y, c8.w, r11.y, c9.z + :0:1035:1788[00000200x_00000000x] (rpt2)nop + :4:1036:1791[80b00037x_0000002dx] cos r13.w, r11.y + :4:1037:1792[8090102dx_0000002dx] (ss)sin r11.y, r11.y + :2:1038:1793[40700037x_00380037x] mul.f r13.w, r13.w, r14.x + :2:1039:1794[41380838x_00000024x] (nop3) floor.f r14.x, r9.x + :2:1040:1798[40180824x_40380024x] (nop3) add.f r9.x, r9.x, (neg)r14.x + :3:1041:1802[63920824x_10269023x] (nop3) mad.f32 r9.x, c8.w, r9.x, c9.z + :0:1042:1806[00000200x_00000000x] (rpt2)nop + :4:1043:1809[80900024x_00000024x] sin r9.x, r9.x + :3:1044:1810[6384181ex_001e8024x] (ss)(nop3) mad.f32 r7.z, r9.x, r2.x, r7.z + :3:1045:1814[638f0024x_002e1043x] mad.f32 r9.x, c16.w, r7.z, r11.z + :3:1046:1815[638f002ex_002f103cx] mad.f32 r11.z, c15.x, r7.z, r11.w + :3:1047:1816[638f002fx_00331040x] mad.f32 r11.w, c16.x, r7.z, r12.w + :3:1048:1817[6396002ex_002e103dx] mad.f32 r11.z, c15.y, r11.x, r11.z + :3:1049:1818[63960024x_00241044x] mad.f32 r9.x, c17.x, r11.x, r9.x + :3:1050:1819[6396002cx_002f1041x] mad.f32 r11.x, c16.y, r11.x, r11.w + :3:1051:1820[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :3:1052:1821[63970033x_00221049x] mad.f32 r12.w, c18.y, r11.z, r8.z + :3:1053:1822[6392002fx_00221049x] mad.f32 r11.w, c18.y, r9.x, r8.z + :3:1054:1823[63960822x_00221049x] (nop1) mad.f32 r8.z, c18.y, r11.x, r8.z + :3:1055:1825[63998033x_10251024x] mad.f32 r12.w, c9.x, r12.w, c9.y + :3:1056:1826[6397802fx_10251024x] mad.f32 r11.w, c9.x, r11.w, c9.y + :3:1057:1827[63910822x_10251024x] (nop1) mad.f32 r8.z, c9.x, r8.z, c9.y + :2:1058:1829[41300039x_00000033x] floor.f r14.y, r12.w + :2:1059:1830[41380038x_0000002fx] (nop2) floor.f r14.x, r11.w + :2:1060:1833[40100033x_40390033x] add.f r12.w, r12.w, (neg)r14.y + :2:1061:1834[4018002fx_4038002fx] (nop2) add.f r11.w, r11.w, (neg)r14.x + :3:1062:1837[63998033x_10261023x] mad.f32 r12.w, c8.w, r12.w, c9.z + :3:1063:1838[6397882fx_10269023x] (nop3) mad.f32 r11.w, c8.w, r11.w, c9.z + :0:1064:1842[00000100x_00000000x] (rpt1)nop + :4:1065:1844[80900033x_00000033x] sin r12.w, r12.w + :3:1066:1845[6384102cx_002c0033x] (ss)mad.f32 r11.x, r12.w, r2.x, r11.x + :4:1067:1846[8090002fx_0000002fx] sin r11.w, r11.w + :3:1068:1847[6384102ex_002e802fx] (ss)(nop2) mad.f32 r11.z, r11.w, r2.x, r11.z + :3:1069:1850[63960039x_10251024x] mad.f32 r14.y, c9.x, r11.x, c9.y + :2:1070:1851[4070002fx_1042002ex] mul.f r11.w, r11.z, c16.z + :2:1071:1852[40700033x_103b002ex] mul.f r12.w, r11.z, c14.w + :2:1072:1853[40700038x_103f002ex] mul.f r14.x, r11.z, c15.w + :2:1073:1854[4130003bx_00000039x] floor.f r14.w, r14.y + :3:1074:1855[6397002ex_10259024x] (nop2) mad.f32 r11.z, c9.x, r11.z, c9.y + :2:1075:1858[40100039x_403b0039x] add.f r14.y, r14.y, (neg)r14.w + :2:1076:1859[4138003ax_0000002ex] (nop2) floor.f r14.z, r11.z + :3:1077:1862[639c8039x_10261023x] mad.f32 r14.y, c8.w, r14.y, c9.z + :2:1078:1863[4018082ex_403a002ex] (nop3) add.f r11.z, r11.z, (neg)r14.z + :0:1079:1867[00000100x_00000000x] (rpt1)nop + :4:1080:1869[8090003bx_00000039x] sin r14.w, r14.y + :4:1081:1870[80b01039x_00000039x] (ss)cos r14.y, r14.y + :3:1082:1871[6397082ex_10269023x] (nop3) mad.f32 r11.z, c8.w, r11.z, c9.z + :0:1083:1875[00000200x_00000000x] (rpt2)nop + :4:1084:1878[80b0003ax_0000002ex] cos r14.z, r11.z + :4:1085:1879[8090102ex_0000002ex] (ss)sin r11.z, r11.z + :2:1086:1880[4070003ax_003b003ax] mul.f r14.z, r14.z, r14.w + :2:1087:1881[4138083bx_00000022x] (nop3) floor.f r14.w, r8.z + :2:1088:1885[40180822x_403b0022x] (nop3) add.f r8.z, r8.z, (neg)r14.w + :3:1089:1889[63910822x_10269023x] (nop3) mad.f32 r8.z, c8.w, r8.z, c9.z + :0:1090:1893[00000200x_00000000x] (rpt2)nop + :4:1091:1896[80900022x_00000022x] sin r8.z, r8.z + :3:1092:1897[63841822x_00248022x] (ss)(nop3) mad.f32 r8.z, r8.z, r2.x, r9.x + :3:1093:1901[63910024x_002f1043x] mad.f32 r9.x, c16.w, r8.z, r11.w + :3:1094:1902[6391002fx_0033103cx] mad.f32 r11.w, c15.x, r8.z, r12.w + :3:1095:1903[63960024x_00241044x] mad.f32 r9.x, c17.x, r11.x, r9.x + :3:1096:1904[63910033x_00381040x] mad.f32 r12.w, c16.x, r8.z, r14.x + :3:1097:1905[6396002fx_002f103dx] mad.f32 r11.w, c15.y, r11.x, r11.w + :3:1098:1906[6396002cx_00331041x] mad.f32 r11.x, c16.y, r11.x, r12.w + :3:1099:1907[63920033x_0020104cx] mad.f32 r12.w, c19.x, r9.x, r8.x + :3:1100:1908[63910022x_10251024x] mad.f32 r8.z, c9.x, r8.z, c9.y + :3:1101:1909[63978038x_0020104cx] mad.f32 r14.x, c19.x, r11.w, r8.x + :3:1102:1910[63960020x_0020104cx] mad.f32 r8.x, c19.x, r11.x, r8.x + :3:1103:1911[63998833x_10251024x] (nop1) mad.f32 r12.w, c9.x, r12.w, c9.y + :3:1104:1913[639c0038x_10251024x] mad.f32 r14.x, c9.x, r14.x, c9.y + :3:1105:1914[63900020x_10251024x] mad.f32 r8.x, c9.x, r8.x, c9.y + :2:1106:1915[4130083bx_00000033x] (nop1) floor.f r14.w, r12.w + :2:1107:1917[4130083cx_00000038x] (nop1) floor.f r15.x, r14.x + :2:1108:1919[40100833x_403b0033x] (nop1) add.f r12.w, r12.w, (neg)r14.w + :2:1109:1921[40100838x_403c0038x] (nop1) add.f r14.x, r14.x, (neg)r15.x + :3:1110:1923[63998833x_10261023x] (nop1) mad.f32 r12.w, c8.w, r12.w, c9.z + :3:1111:1925[639c0838x_10269023x] (nop3) mad.f32 r14.x, c8.w, r14.x, c9.z + :0:1112:1929[00000000x_00000000x] nop + :4:1113:1930[80900033x_00000033x] sin r12.w, r12.w + :3:1114:1931[6384182fx_002f0033x] (ss)(nop1) mad.f32 r11.w, r12.w, r2.x, r11.w + :4:1115:1933[80900038x_00000038x] sin r14.x, r14.x + :3:1116:1934[6384182cx_002c0038x] (ss)(nop1) mad.f32 r11.x, r14.x, r2.x, r11.x + :3:1117:1936[6397882fx_10251024x] (nop1) mad.f32 r11.w, c9.x, r11.w, c9.y + :3:1118:1938[6396082cx_10251024x] (nop1) mad.f32 r11.x, c9.x, r11.x, c9.y + :2:1119:1940[41300833x_0000002fx] (nop1) floor.f r12.w, r11.w + :2:1120:1942[41300838x_0000002cx] (nop1) floor.f r14.x, r11.x + :2:1121:1944[4010082fx_4033002fx] (nop1) add.f r11.w, r11.w, (neg)r12.w + :2:1122:1946[4010082cx_4038002cx] (nop1) add.f r11.x, r11.x, (neg)r14.x + :3:1123:1948[6397882fx_10261023x] (nop1) mad.f32 r11.w, c8.w, r11.w, c9.z + :3:1124:1950[6396082cx_10269023x] (nop3) mad.f32 r11.x, c8.w, r11.x, c9.z + :0:1125:1954[00000000x_00000000x] nop + :4:1126:1955[80b00033x_0000002fx] cos r12.w, r11.w + :4:1127:1956[8090102fx_0000002fx] (ss)sin r11.w, r11.w + :0:1128:1957[00000100x_00000000x] (rpt1)nop + :4:1129:1959[80900038x_0000002cx] sin r14.x, r11.x + :4:1130:1960[80b0102cx_0000002cx] (ss)cos r11.x, r11.x + :2:1131:1961[40700033x_00380033x] mul.f r12.w, r12.w, r14.x + :2:1132:1962[41380838x_00000020x] (nop3) floor.f r14.x, r8.x + :2:1133:1966[40180820x_40380020x] (nop3) add.f r8.x, r8.x, (neg)r14.x + :3:1134:1970[63900820x_10269023x] (nop3) mad.f32 r8.x, c8.w, r8.x, c9.z + :0:1135:1974[00000200x_00000000x] (rpt2)nop + :4:1136:1977[80900020x_00000020x] sin r8.x, r8.x + :3:1137:1978[63841808x_00248020x] (ss)(nop3) mad.f32 r2.x, r8.x, r2.x, r9.x + :3:1138:1982[63840808x_10259024x] (nop3) mad.f32 r2.x, c9.x, r2.x, c9.y + :2:1139:1986[41380820x_00000008x] (nop3) floor.f r8.x, r2.x + :2:1140:1990[40180808x_40200008x] (nop3) add.f r2.x, r2.x, (neg)r8.x + :3:1141:1994[63840808x_10269023x] (nop3) mad.f32 r2.x, c8.w, r2.x, c9.z + :0:1142:1998[00000200x_00000000x] (rpt2)nop + :4:1143:2001[80b00020x_00000008x] cos r8.x, r2.x + :4:1144:2002[80901008x_00000008x] (ss)sin r2.x, r2.x + :3:1145:2003[63978820x_00330020x] (nop1) mad.f32 r8.x, r8.x, r11.w, r12.w + :3:1146:2005[63841008x_0020002cx] (ss)mad.f32 r2.x, r11.x, r2.x, r8.x + :2:1147:2006[41380820x_00000022x] (nop3) floor.f r8.x, r8.z + :2:1148:2010[40100020x_40200022x] add.f r8.x, r8.z, (neg)r8.x + :2:1149:2011[40780008x_104e0008x] (nop2) mul.f r2.x, r2.x, c19.z + :3:1150:2014[63900820x_10269023x] (nop3) mad.f32 r8.x, c8.w, r8.x, c9.z + :0:1151:2018[00000200x_00000000x] (rpt2)nop + :4:1152:2021[80b00022x_00000020x] cos r8.z, r8.x + :4:1153:2022[80901020x_00000020x] (ss)sin r8.x, r8.x + :3:1154:2023[63970822x_003a0022x] (nop1) mad.f32 r8.z, r8.z, r11.z, r14.z + :3:1155:2025[63901020x_00220039x] (ss)mad.f32 r8.x, r14.y, r8.x, r8.z + :2:1156:2026[41380822x_0000001ex] (nop3) floor.f r8.z, r7.z + :2:1157:2030[4010001ex_4022001ex] add.f r7.z, r7.z, (neg)r8.z + :2:1158:2031[40780020x_104b0020x] (nop2) mul.f r8.x, r8.x, c18.w + :3:1159:2034[638f081ex_10269023x] (nop3) mad.f32 r7.z, c8.w, r7.z, c9.z + :0:1160:2038[00000200x_00000000x] (rpt2)nop + :4:1161:2041[80b00022x_0000001ex] cos r8.z, r7.z + :4:1162:2042[8090101ex_0000001ex] (ss)sin r7.z, r7.z + :3:1163:2043[63968822x_00370022x] (nop1) mad.f32 r8.z, r8.z, r11.y, r13.w + :3:1164:2045[638f101ex_00220036x] (ss)mad.f32 r7.z, r13.z, r7.z, r8.z + :2:1165:2046[41380822x_0000001bx] (nop3) floor.f r8.z, r6.w + :2:1166:2050[4010001bx_4022001bx] add.f r6.w, r6.w, (neg)r8.z + :2:1167:2051[4078001ex_1048001ex] (nop2) mul.f r7.z, r7.z, c18.x + :3:1168:2054[638d881bx_10269023x] (nop3) mad.f32 r6.w, c8.w, r6.w, c9.z + :0:1169:2058[00000200x_00000000x] (rpt2)nop + :4:1170:2061[80b00022x_0000001bx] cos r8.z, r6.w + :4:1171:2062[8090101bx_0000001bx] (ss)sin r6.w, r6.w + :3:1172:2063[63938822x_00320022x] (nop1) mad.f32 r8.z, r8.z, r9.w, r12.z + :3:1173:2065[638d901bx_00220030x] (ss)mad.f32 r6.w, r12.x, r6.w, r8.z + :2:1174:2066[41380822x_0000001cx] (nop3) floor.f r8.z, r7.x + :2:1175:2070[4010001cx_4022001cx] add.f r7.x, r7.x, (neg)r8.z + :2:1176:2071[4078001bx_1045001bx] (nop2) mul.f r6.w, r6.w, c17.y + :3:1177:2074[638e081cx_10269023x] (nop3) mad.f32 r7.x, c8.w, r7.x, c9.z + :0:1178:2078[00000200x_00000000x] (rpt2)nop + :4:1179:2081[80b00022x_0000001cx] cos r8.z, r7.x + :4:1180:2082[8090101cx_0000001cx] (ss)sin r7.x, r7.x + :3:1181:2083[63958822x_00350022x] (nop1) mad.f32 r8.z, r8.z, r10.w, r13.y + :3:1182:2085[638e181cx_00228034x] (ss)(nop3) mad.f32 r7.x, r13.x, r7.x, r8.z + :2:1183:2089[4010001bx_c01bc01cx] add.f r6.w, (absneg)r7.x, (absneg)r6.w + :2:1184:2090[4070001cx_10360019x] mul.f r7.x, r6.y, c13.z + :2:1185:2091[40700819x_10340019x] (nop1) mul.f r6.y, r6.y, c13.x + :2:1186:2093[4010001bx_c01e001bx] add.f r6.w, r6.w, (absneg)r7.z + :3:1187:2094[638e001cx_10251024x] mad.f32 r7.x, c9.x, r7.x, c9.y + :3:1188:2095[638c8019x_10251024x] mad.f32 r6.y, c9.x, r6.y, c9.y + :2:1189:2096[4070001ex_10340028x] mul.f r7.z, r10.x, c13.x + :2:1190:2097[4010001bx_c020001bx] add.f r6.w, r6.w, (absneg)r8.x + :2:1191:2098[41300022x_0000001cx] floor.f r8.z, r7.x + :2:1192:2099[41300024x_00000019x] floor.f r9.x, r6.y + :3:1193:2100[638f001ex_10251024x] mad.f32 r7.z, c9.x, r7.z, c9.y + :2:1194:2101[40100008x_c008001bx] add.f r2.x, r6.w, (absneg)r2.x + :2:1195:2102[4070001bx_10360028x] mul.f r6.w, r10.x, c13.z + :2:1196:2103[40100019x_40240019x] add.f r6.y, r6.y, (neg)r9.x + :2:1197:2104[4010001cx_4022001cx] add.f r7.x, r7.x, (neg)r8.z + :3:1198:2105[63870008x_00081029x] mad.f32 r2.x, c10.y, r3.z, r2.x + :3:1199:2106[638d801bx_10251024x] mad.f32 r6.w, c9.x, r6.w, c9.y + :3:1200:2107[638c8019x_10261023x] mad.f32 r6.y, c8.w, r6.y, c9.z + :3:1201:2108[638e001cx_10261023x] mad.f32 r7.x, c8.w, r7.x, c9.z + :2:1202:2109[40100008x_104f8008x] add.f r2.x, (abs)r2.x, c19.w + :2:1203:2110[41300020x_0000001bx] floor.f r8.x, r6.w + :3:1204:2111[63870008x_00089050x] (nop2) mad.f32 r2.x, c20.x, r3.z, r2.x + :2:1205:2114[4010001bx_4020001bx] add.f r6.w, r6.w, (neg)r8.x + :4:1206:2115[80900019x_00000019x] sin r6.y, r6.y + :4:1207:2116[80b0001cx_0000001cx] cos r7.x, r7.x + :3:1208:2117[63908008x_0008001fx] mad.f32 r2.x, r7.w, r8.y, r2.x + :2:1209:2118[40701819x_10210019x] (ss)(nop1) mul.f r6.y, r6.y, c8.y + :3:1210:2120[638d801bx_10261023x] mad.f32 r6.w, c8.w, r6.w, c9.z + :2:1211:2121[4070001cx_1021001cx] mul.f r7.x, r7.x, c8.y + :2:1212:2122[40100008x_10560008x] add.f r2.x, r2.x, c21.z + :2:1213:2123[40180812x_40190012x] (nop3) add.f r4.z, r4.z, (neg)r6.y + :4:1214:2127[80b0001bx_0000001bx] cos r6.w, r6.w + :2:1215:2128[4078181bx_1021001bx] (ss)(nop3) mul.f r6.w, r6.w, c8.y + :2:1216:2132[40100018x_401b0018x] add.f r6.x, r6.x, (neg)r6.w + :2:1217:2133[4018081bx_401c002ax] (nop3) add.f r6.w, r10.z, (neg)r7.x + :2:1218:2137[4070001bx_001b001bx] mul.f r6.w, r6.w, r6.w + :2:1219:2138[40700018x_00180018x] mul.f r6.x, r6.x, r6.x + :3:1220:2139[63890812x_001b8012x] (nop3) mad.f32 r4.z, r4.z, r4.z, r6.w + :3:1221:2143[63890010x_0010102dx] mad.f32 r4.x, c11.y, r4.z, r4.x + :2:1222:2144[41300012x_0000001ex] floor.f r4.z, r7.z + :3:1223:2145[63928010x_8010903ex] (nop2) mad.f32 r4.x, c15.z, r9.y, (neg)r4.x + :2:1224:2148[40100012x_4012001ex] add.f r4.z, r7.z, (neg)r4.z + :2:1225:2149[40780010x_10270010x] (nop2) mul.f r4.x, r4.x, c9.w + :3:1226:2152[63890012x_10261023x] mad.f32 r4.z, c8.w, r4.z, c9.z + :2:1227:2153[40580c10x_10580010x] (sat)(nop3) max.f r4.x, r4.x, c22.x + :0:1228:2157[00000100x_00000000x] (rpt1)nop + :4:1229:2159[80900012x_00000012x] sin r4.z, r4.z + :2:1230:2160[40781812x_10210012x] (ss)(nop3) mul.f r4.z, r4.z, c8.y + :2:1231:2164[40180812x_40120031x] (nop3) add.f r4.z, r12.y, (neg)r4.z + :3:1232:2168[63890812x_00188012x] (nop3) mad.f32 r4.z, r4.z, r4.z, r6.x + :3:1233:2172[63890808x_0008102dx] (nop1) mad.f32 r2.x, c11.y, r4.z, r2.x + :3:1234:2174[63928808x_8008903ex] (nop3) mad.f32 r2.x, c15.z, r9.y, (neg)r2.x + :2:1235:2178[40780808x_10570008x] (nop3) mul.f r2.x, r2.x, c21.w + :2:1236:2182[40580c08x_10580008x] (sat)(nop3) max.f r2.x, r2.x, c22.x + :2:1237:2186[40180808x_00100008x] (nop3) add.f r2.x, r2.x, r4.x + :3:1238:2190[63840010x_1060105fx] mad.f32 r4.x, c23.w, r2.x, c24.x + :3:1239:2191[63840012x_105a1054x] mad.f32 r4.z, c21.x, r2.x, c22.z + :3:1240:2192[63840808x_105d105cx] (nop1) mad.f32 r2.x, c23.x, r2.x, c23.y + :2:1241:2194[40700010x_00100026x] mul.f r4.x, r9.z, r4.x + :2:1242:2195[40700012x_00120026x] mul.f r4.z, r9.z, r4.z + :2:1243:2196[40700818x_00080026x] (nop1) mul.f r6.x, r9.z, r2.x + :2:1244:2198[40700808x_0010001ax] (nop1) mul.f r2.x, r6.z, r4.x + :2:1245:2200[40700009x_00180029x] mul.f r2.y, r10.y, r6.x + :2:1246:2201[4070000ax_0012001dx] mul.f r2.z, r7.y, r4.z + :0:1247:2202[01000000x_0000000ex] jump #14 + :1:1248:2203[284cc007x_00000000x] (jp)mov.u32u32 r1.w, 0x00000000 + :0:1249:2204[00000200x_00000000x] (rpt2)nop + :1:1250:2207[200cc010x_00000007x] mov.u32u32 r4.x, r1.w + :0:1251:2208[00000200x_00000000x] (rpt2)nop + :1:1252:2211[200cc00ax_00000010x] mov.u32u32 r2.z, r4.x + :0:1253:2212[00000200x_00000000x] (rpt2)nop + :1:1254:2215[200cc010x_0000000ax] mov.u32u32 r4.x, r2.z + :0:1255:2216[00000200x_00000000x] (rpt2)nop + :1:1256:2219[200cc009x_00000010x] mov.u32u32 r2.y, r4.x + :0:1257:2220[00000200x_00000000x] (rpt2)nop + :1:1258:2223[200cc010x_00000009x] mov.u32u32 r4.x, r2.y + :0:1259:2224[00000200x_00000000x] (rpt2)nop + :1:1260:2227[200cc008x_00000010x] mov.u32u32 r2.x, r4.x + :1:1261:2228[280cc012x_00000004x] (jp)mov.u32u32 r4.z, r1.x + :1:1262:2229[200cc019x_00000009x] mov.u32u32 r6.y, r2.y + :1:1263:2230[200cc01ax_0000000ax] mov.u32u32 r6.z, r2.z + :1:1264:2231[200cc01bx_00000007x] mov.u32u32 r6.w, r1.w + :3:1265:2232[63890012x_102c102dx] mad.f32 r4.z, c11.y, r4.z, c11.x + :1:1266:2233[200cc01cx_00000003x] mov.u32u32 r7.x, r0.w + :1:1267:2234[200cc01dx_00000000x] mov.u32u32 r7.y, r0.x + :1:1268:2235[200cc01ex_00000001x] mov.u32u32 r7.z, r0.y + :2:1269:2236[40700012x_102e0012x] mul.f r4.z, r4.z, c11.z + :2:1270:2237[4010001cx_401c1022x] add.f r7.x, c8.z, (neg)r7.x + :1:1271:2238[200cc020x_00000002x] mov.u32u32 r8.x, r0.z + :2:1272:2239[40780810x_102a0023x] (nop3) mul.f r4.x, r8.w, c10.z + :4:1273:2243[8070000bx_00000012x] exp2 r2.w, r4.z + :2:1274:2244[40700010x_00230010x] mul.f r4.x, r4.x, r8.w + :1:1275:2245[200cd012x_0000000bx] (ss)mov.u32u32 r4.z, r2.w + :1:1276:2246[200cc018x_00000005x] mov.u32u32 r6.x, r1.y + :0:1277:2247[00000200x_00000000x] (rpt2)nop + :2:1278:2250[40100412x_40180012x] (sat)add.f r4.z, r4.z, (neg)r6.x + :2:1279:2251[40100010x_40101025x] add.f r4.x, c9.y, (neg)r4.x + :1:1280:2252[200cc018x_00000003x] mov.u32u32 r6.x, r0.w + :1:1281:2253[200cc022x_00000004x] mov.u32u32 r8.z, r1.x + :3:1282:2254[63890008x_0008102bx] mad.f32 r2.x, c10.w, r4.z, r2.x + :3:1283:2255[63890019x_00191061x] mad.f32 r6.y, c24.y, r4.z, r6.y + :3:1284:2256[6389001bx_001b1037x] mad.f32 r6.w, c13.w, r4.z, r6.w + :2:1285:2257[40500010x_10710010x] max.f r4.x, r4.x, c28.y + :3:1286:2258[638e0000x_001d0008x] mad.f32 r0.x, r2.x, r7.x, r7.y + :3:1287:2259[63890008x_001a1061x] mad.f32 r2.x, c24.y, r4.z, r6.z + :3:1288:2260[638e0001x_001e0019x] mad.f32 r0.y, r6.y, r7.x, r7.z + :2:1289:2261[40300010x_10500010x] min.f r4.x, r4.x, c20.x + :1:1290:2262[200cc023x_00000006x] mov.u32u32 r8.w, r1.z + :3:1291:2263[638e0002x_00200008x] mad.f32 r0.z, r2.x, r7.x, r8.x + :3:1292:2264[638e0003x_0018001bx] mad.f32 r0.w, r6.w, r7.x, r6.x + :2:1293:2265[40100004x_00100022x] add.f r1.x, r8.z, r4.x + :1:1294:2266[200cc024x_0000000bx] mov.u32u32 r9.x, r2.w + :2:1295:2267[42180006x_20010023x] (nop2) add.u r1.z, r8.w, 1 + :1:1296:2270[200cc005x_00000024x] mov.u32u32 r1.y, r9.x + :0:1297:2271[01000000x_fffffb99x] jump #-1127 + :2:1298:2272[48500401x_00010001x] (jp)(sat)max.f r0.y, r0.y, r0.y + :2:1299:2273[40500402x_00020002x] (sat)max.f r0.z, r0.z, r0.z + :2:1300:2274[40100003x_400e1022x] add.f r0.w, c8.z, (neg)r3.z + :2:1301:2275[40500400x_00000000x] (sat)max.f r0.x, r0.x, r0.x + :2:1302:2276[4070000fx_00010001x] mul.f r3.w, r0.y, r0.y + :2:1303:2277[40500006x_00010002x] max.f r1.z, r0.z, r0.y + :2:1304:2278[40500403x_102a0003x] (sat)max.f r0.w, r0.w, c10.z + :2:1305:2279[40500004x_00010000x] max.f r1.x, r0.x, r0.y + :2:1306:2280[40100005x_40020000x] add.f r1.y, r0.x, (neg)r0.z + :2:1307:2281[40300007x_00010000x] min.f r1.w, r0.x, r0.y + :2:1308:2282[4010000ex_40000002x] add.f r3.z, r0.z, (neg)r0.x + :2:1309:2283[40500004x_00020004x] max.f r1.x, r1.x, r0.z + :3:1310:2284[63828005x_00020003x] mad.f32 r1.y, r0.w, r1.y, r0.z + :2:1311:2285[40300007x_00020007x] min.f r1.w, r1.w, r0.z + :2:1312:2286[40500006x_00000006x] max.f r1.z, r1.z, r0.x + :3:1313:2287[6387000ex_00000003x] mad.f32 r3.z, r0.w, r3.z, r0.x + :2:1314:2288[40100008x_10630004x] add.f r2.x, r1.x, c24.w + :2:1315:2289[40100005x_10620005x] add.f r1.y, r1.y, c24.z + :2:1316:2290[40300002x_00010002x] min.f r0.z, r0.z, r0.y + :2:1317:2291[40100004x_40070004x] add.f r1.x, r1.x, (neg)r1.w + :3:1318:2292[6380800ax_80051021x] mad.f32 r2.z, c8.y, r0.y, (neg)r1.y + :3:1319:2293[6382800fx_000f0005x] mad.f32 r3.w, r1.y, r1.y, r3.w + :2:1320:2294[40300000x_00000002x] min.f r0.x, r0.z, r0.x + :4:1321:2295[80100008x_00000008x] rcp r2.x, r2.x + :2:1322:2296[40500007x_00010005x] max.f r1.w, r1.y, r0.y + :2:1323:2297[40100002x_400e000ax] add.f r0.z, r2.z, (neg)r3.z + :2:1324:2298[4030000cx_00010005x] min.f r3.x, r1.y, r0.y + :3:1325:2299[6387000ax_000f000ex] mad.f32 r2.z, r3.z, r3.z, r3.w + :2:1326:2300[40500007x_000e0007x] max.f r1.w, r1.w, r3.z + :2:1327:2301[40100009x_10630006x] add.f r2.y, r1.z, c24.w + :2:1328:2302[4030000cx_000e000cx] min.f r3.x, r3.x, r3.z + :2:1329:2303[40100000x_40000006x] add.f r0.x, r1.z, (neg)r0.x + :2:1330:2304[4010000fx_10630007x] add.f r3.w, r1.w, c24.w + :3:1331:2305[6382800dx_80011021x] mad.f32 r3.y, c8.y, r1.y, (neg)r0.y + :4:1332:2306[8030000ax_0000000ax] rsq r2.z, r2.z + :2:1333:2307[40100007x_400c0007x] add.f r1.w, r1.w, (neg)r3.x + :2:1334:2308[40700006x_00020002x] mul.f r1.z, r0.z, r0.z + :4:1335:2309[80100009x_00000009x] rcp r2.y, r2.y + :2:1336:2310[4010000bx_00010005x] add.f r2.w, r1.y, r0.y + :2:1337:2311[4010000dx_400e000dx] add.f r3.y, r3.y, (neg)r3.z + :2:1338:2312[40701010x_000a0001x] (ss)mul.f r4.x, r0.y, r2.z + :4:1339:2313[8010000cx_0000000fx] rcp r3.x, r3.w + :2:1340:2314[4070100fx_00090000x] (ss)mul.f r3.w, r0.x, r2.y + :2:1341:2315[4010000bx_000b000ex] add.f r2.w, r3.z, r2.w + :3:1342:2316[63840004x_800f0004x] mad.f32 r1.x, r1.x, r2.x, (neg)r3.w + :3:1343:2317[63868006x_0006000dx] mad.f32 r1.z, r3.y, r3.y, r1.z + :2:1344:2318[40700008x_000a0005x] mul.f r2.x, r1.y, r2.z + :2:1345:2319[4070000ax_000a000ex] mul.f r2.z, r3.z, r2.z + :2:1346:2320[40700803x_00040003x] (nop1) mul.f r0.w, r0.w, r1.x + :3:1347:2322[63848000x_00030000x] mad.f32 r0.x, r0.x, r2.y, r0.w + :3:1348:2323[63870003x_80011021x] mad.f32 r0.w, c8.y, r3.z, (neg)r0.y + :3:1349:2324[63860000x_80008007x] (nop2) mad.f32 r0.x, r1.w, r3.x, (neg)r0.x + :2:1350:2327[40180803x_40050003x] (nop3) add.f r0.w, r0.w, (neg)r1.y + :3:1351:2331[63818804x_00068003x] (nop3) mad.f32 r1.x, r0.w, r0.w, r1.z + :0:1352:2335[00000200x_00000000x] (rpt2)nop + :4:1353:2338[80300004x_00000004x] rsq r1.x, r1.x + :2:1354:2339[40701003x_00040003x] (ss)mul.f r0.w, r0.w, r1.x + :2:1355:2340[40700002x_00040002x] mul.f r0.z, r0.z, r1.x + :2:1356:2341[40780004x_0004000dx] (nop2) mul.f r1.x, r3.y, r1.x + :2:1357:2344[40700007x_00100002x] mul.f r1.w, r0.z, r4.x + :2:1358:2345[40700006x_00031020x] mul.f r1.z, c8.x, r0.w + :3:1359:2346[63840007x_00070004x] mad.f32 r1.w, r1.x, r2.x, r1.w + :2:1360:2347[40700002x_00021020x] mul.f r0.z, c8.x, r0.z + :2:1361:2348[40700004x_00041020x] mul.f r1.x, c8.x, r1.x + :2:1362:2349[40700006x_80000006x] mul.f r1.z, r1.z, (abs)r0.x + :3:1363:2350[63850003x_00070003x] mad.f32 r0.w, r0.w, r2.z, r1.w + :2:1364:2351[40700002x_80000002x] mul.f r0.z, r0.z, (abs)r0.x + :2:1365:2352[40700000x_80000004x] mul.f r0.x, r1.x, (abs)r0.x + :1:1366:2353[204cc007x_3f800000x] mov.u32u32 r1.w, 0x3f800000 + :2:1367:2354[40700004x_00030006x] mul.f r1.x, r1.z, r0.w + :2:1368:2355[40700002x_00030002x] mul.f r0.z, r0.z, r0.w + :2:1369:2356[40780000x_00030000x] (nop2) mul.f r0.x, r0.x, r0.w + :3:1370:2359[63858401x_00010002x] (sat)mad.f32 r0.y, r0.z, r2.w, r0.y + :3:1371:2360[63858403x_000e0004x] (sat)mad.f32 r0.w, r1.x, r2.w, r3.z + :3:1372:2361[63858400x_00050000x] (sat)mad.f32 r0.x, r0.x, r2.w, r1.y + :2:1373:2362[40100004x_40171022x] add.f r1.x, c8.z, (neg)r5.w + :2:1374:2363[40180805x_40131022x] (nop3) add.f r1.y, c8.z, (neg)r4.w + :4:1375:2367[80500002x_00000003x] log2 r0.z, r0.w + :4:1376:2368[80500001x_00000001x] log2 r0.y, r0.y + :0:1377:2369[00000000x_00000000x] nop + :4:1378:2370[80500000x_00000000x] log2 r0.x, r0.x + :2:1379:2371[40701003x_00131065x] (ss)mul.f r0.w, c25.y, r4.w + :2:1380:2372[40700002x_106c0002x] mul.f r0.z, r0.z, c27.x + :2:1381:2373[40700001x_106a0001x] mul.f r0.y, r0.y, c26.z + :2:1382:2374[40700000x_10640000x] mul.f r0.x, r0.x, c25.x + :2:1383:2375[40780803x_00170003x] (nop3) mul.f r0.w, r0.w, r5.w + :2:1384:2379[40700003x_00050003x] mul.f r0.w, r0.w, r1.y + :4:1385:2380[80700002x_00000002x] exp2 r0.z, r0.z + :4:1386:2381[80700001x_00000001x] exp2 r0.y, r0.y + :0:1387:2382[00000000x_00000000x] nop + :4:1388:2383[80700000x_00000000x] exp2 r0.x, r0.x + :2:1389:2384[40701802x_106d0002x] (ss)(nop1) mul.f r0.z, r0.z, c27.y + :2:1390:2386[40700003x_00040003x] mul.f r0.w, r0.w, r1.x + :2:1391:2387[40780801x_106b0001x] (nop3) mul.f r0.y, r0.y, c26.w + :0:1392:2391[00000100x_00000000x] (rpt1)nop + :4:1393:2393[80500003x_00000003x] log2 r0.w, r0.w + :2:1394:2394[40781803x_10680003x] (ss)(nop3) mul.f r0.w, r0.w, c26.x + :0:1395:2398[00000200x_00000000x] (rpt2)nop + :4:1396:2401[80700003x_00000003x] exp2 r0.w, r0.w + :3:1397:2402[63819803x_10509069x] (ss)(nop3) mad.f32 r0.w, c26.y, r0.w, c20.x + :2:1398:2406[40700006x_00030002x] mul.f r1.z, r0.z, r0.w + :2:1399:2407[40700005x_00030001x] mul.f r1.y, r0.y, r0.w + :2:1400:2408[40700004x_00030000x] mul.f r1.x, r0.x, r0.w + :0:1401:2409[03000000x_00000000x] end + :0:1402:2410[00000000x_00000000x] nop + :0:1403:2411[00000000x_00000000x] nop + :0:1404:2412[00000000x_00000000x] nop + :0:1405:2413[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-73 (cnt=74, max=73) + - used (merged): 0-147 (cnt=148, max=147) + - input (half): (cnt=0, max=0) + - input (full): 19-20 (cnt=2, max=20) + - const (half): (cnt=0, max=0) + - const (full): 0-1 3-5 8-9 32-113 (cnt=89, max=113) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 4-7 (cnt=4, max=7) (estimated) + - shaderdb: 2414 instructions, 1355 nops, 1059 non-nops, (1406 instlen), 0 half, 19 full + - shaderdb: 140 (ss), 0 (sy) +!+ 00000100 SP_BLEND_CNTL: { UNK8 } + + fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x } +!+ 00000001 SP_FS_OUTPUT_CNTL1: { MRT = 1 } +!+ 00000004 SP_FS_OUTPUT[0].REG: { REGID = r1.x } +!+ 00000004 SP_FS_OUTPUT[0x1].REG: { REGID = r1.x } +!+ 00000004 SP_FS_OUTPUT[0x2].REG: { REGID = r1.x } +!+ 00000004 SP_FS_OUTPUT[0x3].REG: { REGID = r1.x } +!+ 00000004 SP_FS_OUTPUT[0x4].REG: { REGID = r1.x } +!+ 00000004 SP_FS_OUTPUT[0x5].REG: { REGID = r1.x } +!+ 00000004 SP_FS_OUTPUT[0x6].REG: { REGID = r1.x } +!+ 00000004 SP_FS_OUTPUT[0x7].REG: { REGID = r1.x } + + 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } + + 00000000 SP_UNKNOWN_A9A8: 0 + + 00000005 SP_UNKNOWN_AB00: 0x5 + + 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } +!+ 00000058 SP_FS_INSTRLEN: 88 +!+ 011160a0 SP_IBO_LO: 0x11160a0 base=1116000, offset=160, size=388 + + 00000000 SP_IBO_HI: 0 base=1116000, offset=160, size=388 + + 00000000 SP_IBO_COUNT: 0 + + 00000100 HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED } + + 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 } + + 00000000 HLSQ_DS_CNTL: { CONSTLEN = 0 } + + 00000000 HLSQ_GS_CNTL: { CONSTLEN = 0 } + + 00000001 HLSQ_UNKNOWN_B980: 0x1 + + 00000007 HLSQ_CONTROL_1_REG: 0x7 + + fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } + + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } +!+ 1513fcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r4.w | ZWCOORDREGID = r5.y } + + 000000fc HLSQ_CONTROL_5_REG: 0xfc + + 000000ff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 } + + 00000108 HLSQ_FS_CNTL: { CONSTLEN = 32 | ENABLED } +0000000001d8f130: 0000: 70388003 00000186 00000001 00000004 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d8f140: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 3 + :0,1,17,3 +0000000001d8f144: 0000: 48088a01 00000003 +0000000001d91ac0: 0000: 70bf8003 01d8f000 00000000 00000053 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91ad0: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 18 + :0,1,18,3 +0000000001d91ad4: 0000: 48088901 00000012 +t7 opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0x883 | BIT = 0 | WAIT_FOR_ME } +0000000001d91adc: 0000: 70b90001 02000883 +t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) + { REG0 = 0 | MODE = PRED_TEST } + { DWORDS = 2 } +0000000001d91ae4: 0000: 70c70002 10000000 00000002 +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = 0x15 | MARKER = RM6_ENDVIS } +0000000001d91af0: 0000: 70e50001 00000015 +t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords) + { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } + { ADDR_LO = 0 } + { ADDR_HI = 0 } +0000000001d91af8: 0000: 70438003 00040000 00000000 00000000 +t7 opcode: CP_SKIP_IB2_ENABLE_LOCAL (23) (2 dwords) +0000000001d91b08: 0000: 70230001 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91b10: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 19 + :0,1,18,19 +0000000001d91b14: 0000: 48088a01 00000013 +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = 0x16 | MARKER = RM6_RESOLVE } +0000000001d91b1c: 0000: 70e50001 00000016 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91b24: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 20 + :0,1,18,20 +0000000001d91b28: 0000: 48088a01 00000014 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91b30: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 21 + :0,1,21,20 +0000000001d91b34: 0000: 48088901 00000015 +t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + ibaddr:0000000001116130 + ibsize:00000015 +t4 write RB_BLIT_SCISSOR_TL (88d1) + RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } + RB_BLIT_SCISSOR_BR: { X = 2175 | Y = 1439 } +0000000001116130: 0000: 4888d102 00000000 059f087f +t4 write RB_BLIT_INFO (88e3) + RB_BLIT_INFO: { CLEAR_MASK = 0 } +000000000111613c: 0000: 4088e301 00000000 +t4 write RB_BLIT_DST_INFO (88d7) + RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM } + RB_BLIT_DST: 0x1125000 + RB_BLIT_DST+0x1: 0 + RB_BLIT_DST_PITCH: 8704 + RB_BLIT_DST_ARRAY_PITCH: 12533760 +0000000001116144: 0000: 4888d785 000018a0 01125000 00000000 00000088 0002fd00 +t4 write RB_BLIT_BASE_GMEM (88d6) + RB_BLIT_BASE_GMEM: 0 +000000000111615c: 0000: 4088d601 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001116164: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 7 + :0,1,21,7 +0000000001116168: 0000: 48088a01 00000007 +t7 opcode: CP_EVENT_WRITE (46) (2 dwords) + { EVENT = BLIT } + event BLIT + mode: RM6_RESOLVE + skip_ib2: g=1, l=0 + draw[3] register values +!+ 00000015 CP_SCRATCH[0x6].REG: 21 + :0,1,21,7 +!+ 00000007 CP_SCRATCH[0x7].REG: 7 + :0,1,21,7 + + 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } + + 059f087f RB_BLIT_SCISSOR_BR: { X = 2175 | Y = 1439 } + + 00000000 RB_BLIT_BASE_GMEM: 0 +!+ 000018a0 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM } +!+ 01125000 RB_BLIT_DST: 0x1125000 + + 00000000 RB_BLIT_DST+0x1: 0 +!+ 00000088 RB_BLIT_DST_PITCH: 8704 +!+ 0002fd00 RB_BLIT_DST_ARRAY_PITCH: 12533760 +!+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 } +0000000001116170: 0000: 70460001 0000001e +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001116178: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 8 + :0,1,21,8 +000000000111617c: 0000: 48088a01 00000008 +0000000001d91b3c: 0000: 70bf8003 01116130 00000000 00000015 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91b4c: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 22 + :0,1,22,8 +0000000001d91b50: 0000: 48088901 00000016 +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = RM6_YIELD | MARKER = RM6_YIELD } +0000000001d91b58: 0000: 70e50001 00000007 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91b60: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 23 + :0,1,22,23 +0000000001d91b64: 0000: 48088a01 00000017 +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = 0x14 | MARKER = RM6_GMEM } +0000000001d91b6c: 0000: 70e50001 00000014 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91b74: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 24 + :0,1,22,24 +0000000001d91b78: 0000: 48088a01 00000018 +t4 write GRAS_SC_WINDOW_SCISSOR_TL (80f0) + GRAS_SC_WINDOW_SCISSOR_TL: { X = 544 | Y = 0 } + GRAS_SC_WINDOW_SCISSOR_BR: { X = 1087 | Y = 479 } +0000000001d91b80: 0000: 4080f002 00000220 01df043f +t4 write GRAS_2D_RESOLVE_CNTL_1 (840a) + GRAS_2D_RESOLVE_CNTL_1: { X = 544 | Y = 0 } + GRAS_2D_RESOLVE_CNTL_2: { X = 1087 | Y = 479 } +0000000001d91b8c: 0000: 48840a02 00000220 01df043f +t7 opcode: CP_WAIT_FOR_ME (13) (1 dwords) +0000000001d91b98: 0000: 70138000 +t7 opcode: CP_SET_MODE (63) (2 dwords) +0000000001d91b9c: 0000: 70e30001 00000000 +t7 opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0x883 | BIT = 0 | WAIT_FOR_ME } +0000000001d91ba4: 0000: 70b90001 02000883 +t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) + { REG0 = 0 | MODE = PRED_TEST } + { DWORDS = 11 } +0000000001d91bac: 0000: 70c70002 10000000 0000000b +t7 opcode: CP_SET_BIN_DATA5 (2f) (8 dwords) + { VSC_SIZE = 1 | VSC_N = 0 } + { BIN_DATA_ADDR_LO = 0x1d5d440 } + { BIN_DATA_ADDR_HI = 0 } + { BIN_SIZE_ADDRESS_LO = 0x1d65804 } + { BIN_SIZE_ADDRESS_HI = 0 } + { BIN_PRIM_STRM_LO = 0x1d68040 } + { BIN_PRIM_STRM_HI = 0 } +0000000001d91bb8: 0000: 702f0007 00010000 01d5d440 00000000 01d65804 00000000 01d68040 00000000 +t7 opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords) +0000000001d91bd8: 0000: 70640001 00000000 +t7 opcode: CP_NOP (10) (3 dwords) +0000000001d91be0: 0000: 70100002 70640001 00000001 +t4 write RB_WINDOW_OFFSET (8890) + RB_WINDOW_OFFSET: { X = 544 | Y = 0 } +0000000001d91bec: 0000: 48889001 00000220 +t4 write RB_WINDOW_OFFSET2 (88d4) + RB_WINDOW_OFFSET2: { X = 544 | Y = 0 } +0000000001d91bf4: 0000: 4888d401 00000220 +t4 write SP_WINDOW_OFFSET (b4d1) + SP_WINDOW_OFFSET: { X = 544 | Y = 0 } +0000000001d91bfc: 0000: 48b4d101 00000220 +t4 write SP_TP_WINDOW_OFFSET (b307) + SP_TP_WINDOW_OFFSET: { X = 544 | Y = 0 } +0000000001d91c04: 0000: 48b30701 00000220 +t4 write GRAS_BIN_CONTROL (80a1) + GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 } +0000000001d91c0c: 0000: 4880a101 06001e11 +t4 write RB_BIN_CONTROL (8800) + RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 } +0000000001d91c14: 0000: 48880001 06001e11 +t4 write RB_BIN_CONTROL2 (88d3) + RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 } +0000000001d91c1c: 0000: 4088d301 00001e11 +t7 opcode: CP_SET_MODE (63) (2 dwords) +0000000001d91c24: 0000: 70e30001 00000000 +t4 write RB_SAMPLE_CONFIG (8804) + RB_SAMPLE_CONFIG: { 0 } +0000000001d91c2c: 0000: 40880401 00000000 +t4 write SP_TP_SAMPLE_CONFIG (b304) + SP_TP_SAMPLE_CONFIG: { 0 } +0000000001d91c34: 0000: 48b30401 00000000 +t4 write GRAS_SAMPLE_CONFIG (80a4) + GRAS_SAMPLE_CONFIG: { 0 } +0000000001d91c3c: 0000: 4880a401 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91c44: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 25 + :0,1,25,24 +0000000001d91c48: 0000: 48088901 00000019 +t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + ibaddr:00000000011160d0 + ibsize:00000018 +0000000001d91c50: 0000: 70bf8003 011160d0 00000000 00000018 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91c60: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 26 + :0,1,26,24 +0000000001d91c64: 0000: 48088901 0000001a +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91c6c: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 27 + :0,1,27,24 +0000000001d91c70: 0000: 48088901 0000001b +t7 opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0xc39 | BIT = 0 | WAIT_FOR_ME } +0000000001d91c78: 0000: 70b90001 02000c39 +t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) + { REG0 = 0 | MODE = PRED_TEST } + { DWORDS = 4 } +0000000001d91c80: 0000: 70c70002 10000000 00000004 +t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + ibaddr:0000000001d8f000 + ibsize:00000053 +0000000001d91c8c: 0000: 70bf8003 01d8f000 00000000 00000053 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91c9c: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 28 + :0,1,28,24 +0000000001d91ca0: 0000: 48088901 0000001c +t7 opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0x883 | BIT = 0 | WAIT_FOR_ME } +0000000001d91ca8: 0000: 70b90001 02000883 +t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) + { REG0 = 0 | MODE = PRED_TEST } + { DWORDS = 2 } +0000000001d91cb0: 0000: 70c70002 10000000 00000002 +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = 0x15 | MARKER = RM6_ENDVIS } +0000000001d91cbc: 0000: 70e50001 00000015 +t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords) + { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } + { ADDR_LO = 0 } + { ADDR_HI = 0 } +0000000001d91cc4: 0000: 70438003 00040000 00000000 00000000 +t7 opcode: CP_SKIP_IB2_ENABLE_LOCAL (23) (2 dwords) +0000000001d91cd4: 0000: 70230001 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91cdc: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 29 + :0,1,28,29 +0000000001d91ce0: 0000: 48088a01 0000001d +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = 0x16 | MARKER = RM6_RESOLVE } +0000000001d91ce8: 0000: 70e50001 00000016 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91cf0: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 30 + :0,1,28,30 +0000000001d91cf4: 0000: 48088a01 0000001e +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91cfc: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 31 + :0,1,31,30 +0000000001d91d00: 0000: 48088901 0000001f +t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + ibaddr:0000000001116130 + ibsize:00000015 +0000000001d91d08: 0000: 70bf8003 01116130 00000000 00000015 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91d18: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 32 + :0,1,32,30 +0000000001d91d1c: 0000: 48088901 00000020 +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = RM6_YIELD | MARKER = RM6_YIELD } +0000000001d91d24: 0000: 70e50001 00000007 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91d2c: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 33 + :0,1,32,33 +0000000001d91d30: 0000: 48088a01 00000021 +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = 0x14 | MARKER = RM6_GMEM } +0000000001d91d38: 0000: 70e50001 00000014 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91d40: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 34 + :0,1,32,34 +0000000001d91d44: 0000: 48088a01 00000022 +t4 write GRAS_SC_WINDOW_SCISSOR_TL (80f0) + GRAS_SC_WINDOW_SCISSOR_TL: { X = 1088 | Y = 0 } + GRAS_SC_WINDOW_SCISSOR_BR: { X = 1631 | Y = 479 } +0000000001d91d4c: 0000: 4080f002 00000440 01df065f +t4 write GRAS_2D_RESOLVE_CNTL_1 (840a) + GRAS_2D_RESOLVE_CNTL_1: { X = 1088 | Y = 0 } + GRAS_2D_RESOLVE_CNTL_2: { X = 1631 | Y = 479 } +0000000001d91d58: 0000: 48840a02 00000440 01df065f +t7 opcode: CP_WAIT_FOR_ME (13) (1 dwords) +0000000001d91d64: 0000: 70138000 +t7 opcode: CP_SET_MODE (63) (2 dwords) +0000000001d91d68: 0000: 70e30001 00000000 +t7 opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0x883 | BIT = 0 | WAIT_FOR_ME } +0000000001d91d70: 0000: 70b90001 02000883 +t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) + { REG0 = 0 | MODE = PRED_TEST } + { DWORDS = 11 } +0000000001d91d78: 0000: 70c70002 10000000 0000000b +t7 opcode: CP_SET_BIN_DATA5 (2f) (8 dwords) + { VSC_SIZE = 1 | VSC_N = 0 } + { BIN_DATA_ADDR_LO = 0x1d5d880 } + { BIN_DATA_ADDR_HI = 0 } + { BIN_SIZE_ADDRESS_LO = 0x1d65808 } + { BIN_SIZE_ADDRESS_HI = 0 } + { BIN_PRIM_STRM_LO = 0x1d69080 } + { BIN_PRIM_STRM_HI = 0 } +0000000001d91d84: 0000: 702f0007 00010000 01d5d880 00000000 01d65808 00000000 01d69080 00000000 +t7 opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords) +0000000001d91da4: 0000: 70640001 00000000 +t7 opcode: CP_NOP (10) (3 dwords) +0000000001d91dac: 0000: 70100002 70640001 00000001 +t4 write RB_WINDOW_OFFSET (8890) + RB_WINDOW_OFFSET: { X = 1088 | Y = 0 } +0000000001d91db8: 0000: 48889001 00000440 +t4 write RB_WINDOW_OFFSET2 (88d4) + RB_WINDOW_OFFSET2: { X = 1088 | Y = 0 } +0000000001d91dc0: 0000: 4888d401 00000440 +t4 write SP_WINDOW_OFFSET (b4d1) + SP_WINDOW_OFFSET: { X = 1088 | Y = 0 } +0000000001d91dc8: 0000: 48b4d101 00000440 +t4 write SP_TP_WINDOW_OFFSET (b307) + SP_TP_WINDOW_OFFSET: { X = 1088 | Y = 0 } +0000000001d91dd0: 0000: 48b30701 00000440 +t4 write GRAS_BIN_CONTROL (80a1) + GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 } +0000000001d91dd8: 0000: 4880a101 06001e11 +t4 write RB_BIN_CONTROL (8800) + RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 } +0000000001d91de0: 0000: 48880001 06001e11 +t4 write RB_BIN_CONTROL2 (88d3) + RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 } +0000000001d91de8: 0000: 4088d301 00001e11 +t7 opcode: CP_SET_MODE (63) (2 dwords) +0000000001d91df0: 0000: 70e30001 00000000 +t4 write RB_SAMPLE_CONFIG (8804) + RB_SAMPLE_CONFIG: { 0 } +0000000001d91df8: 0000: 40880401 00000000 +t4 write SP_TP_SAMPLE_CONFIG (b304) + SP_TP_SAMPLE_CONFIG: { 0 } +0000000001d91e00: 0000: 48b30401 00000000 +t4 write GRAS_SAMPLE_CONFIG (80a4) + GRAS_SAMPLE_CONFIG: { 0 } +0000000001d91e08: 0000: 4880a401 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91e10: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 35 + :0,1,35,34 +0000000001d91e14: 0000: 48088901 00000023 +t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + ibaddr:00000000011160d0 + ibsize:00000018 +0000000001d91e1c: 0000: 70bf8003 011160d0 00000000 00000018 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91e2c: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 36 + :0,1,36,34 +0000000001d91e30: 0000: 48088901 00000024 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91e38: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 37 + :0,1,37,34 +0000000001d91e3c: 0000: 48088901 00000025 +t7 opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0xc3a | BIT = 0 | WAIT_FOR_ME } +0000000001d91e44: 0000: 70b90001 02000c3a +t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) + { REG0 = 0 | MODE = PRED_TEST } + { DWORDS = 4 } +0000000001d91e4c: 0000: 70c70002 10000000 00000004 +t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + ibaddr:0000000001d8f000 + ibsize:00000053 +0000000001d91e58: 0000: 70bf8003 01d8f000 00000000 00000053 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91e68: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 38 + :0,1,38,34 +0000000001d91e6c: 0000: 48088901 00000026 +t7 opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0x883 | BIT = 0 | WAIT_FOR_ME } +0000000001d91e74: 0000: 70b90001 02000883 +t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) + { REG0 = 0 | MODE = PRED_TEST } + { DWORDS = 2 } +0000000001d91e7c: 0000: 70c70002 10000000 00000002 +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = 0x15 | MARKER = RM6_ENDVIS } +0000000001d91e88: 0000: 70e50001 00000015 +t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords) + { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } + { ADDR_LO = 0 } + { ADDR_HI = 0 } +0000000001d91e90: 0000: 70438003 00040000 00000000 00000000 +t7 opcode: CP_SKIP_IB2_ENABLE_LOCAL (23) (2 dwords) +0000000001d91ea0: 0000: 70230001 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91ea8: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 39 + :0,1,38,39 +0000000001d91eac: 0000: 48088a01 00000027 +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = 0x16 | MARKER = RM6_RESOLVE } +0000000001d91eb4: 0000: 70e50001 00000016 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91ebc: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 40 + :0,1,38,40 +0000000001d91ec0: 0000: 48088a01 00000028 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91ec8: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 41 + :0,1,41,40 +0000000001d91ecc: 0000: 48088901 00000029 +t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + ibaddr:0000000001116130 + ibsize:00000015 +0000000001d91ed4: 0000: 70bf8003 01116130 00000000 00000015 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91ee4: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 42 + :0,1,42,40 +0000000001d91ee8: 0000: 48088901 0000002a +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = RM6_YIELD | MARKER = RM6_YIELD } +0000000001d91ef0: 0000: 70e50001 00000007 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91ef8: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 43 + :0,1,42,43 +0000000001d91efc: 0000: 48088a01 0000002b +t7 opcode: CP_SET_MARKER (65) (2 dwords) + { MODE = 0x14 | MARKER = RM6_GMEM } +0000000001d91f04: 0000: 70e50001 00000014 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91f0c: 0000: 70268000 +t4 write CP_SCRATCH[0x7].REG (088a) + CP_SCRATCH[0x7].REG: 44 + :0,1,42,44 +0000000001d91f10: 0000: 48088a01 0000002c +t4 write GRAS_SC_WINDOW_SCISSOR_TL (80f0) + GRAS_SC_WINDOW_SCISSOR_TL: { X = 1632 | Y = 0 } + GRAS_SC_WINDOW_SCISSOR_BR: { X = 2159 | Y = 479 } +0000000001d91f18: 0000: 4080f002 00000660 01df086f +t4 write GRAS_2D_RESOLVE_CNTL_1 (840a) + GRAS_2D_RESOLVE_CNTL_1: { X = 1632 | Y = 0 } + GRAS_2D_RESOLVE_CNTL_2: { X = 2159 | Y = 479 } +0000000001d91f24: 0000: 48840a02 00000660 01df086f +t7 opcode: CP_WAIT_FOR_ME (13) (1 dwords) +0000000001d91f30: 0000: 70138000 +t7 opcode: CP_SET_MODE (63) (2 dwords) +0000000001d91f34: 0000: 70e30001 00000000 +t7 opcode: CP_REG_TEST (39) (2 dwords) + { REG = 0x883 | BIT = 0 | WAIT_FOR_ME } +0000000001d91f3c: 0000: 70b90001 02000883 +t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) + { REG0 = 0 | MODE = PRED_TEST } + { DWORDS = 11 } +0000000001d91f44: 0000: 70c70002 10000000 0000000b +t7 opcode: CP_SET_BIN_DATA5 (2f) (8 dwords) + { VSC_SIZE = 1 | VSC_N = 0 } + { BIN_DATA_ADDR_LO = 0x1d5dcc0 } + { BIN_DATA_ADDR_HI = 0 } + { BIN_SIZE_ADDRESS_LO = 0x1d6580c } + { BIN_SIZE_ADDRESS_HI = 0 } + { BIN_PRIM_STRM_LO = 0x1d6a0c0 } + { BIN_PRIM_STRM_HI = 0 } +0000000001d91f50: 0000: 702f0007 00010000 01d5dcc0 00000000 01d6580c 00000000 01d6a0c0 00000000 +t7 opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords) +0000000001d91f70: 0000: 70640001 00000000 +t7 opcode: CP_NOP (10) (3 dwords) +0000000001d91f78: 0000: 70100002 70640001 00000001 +t4 write RB_WINDOW_OFFSET (8890) + RB_WINDOW_OFFSET: { X = 1632 | Y = 0 } +0000000001d91f84: 0000: 48889001 00000660 +t4 write RB_WINDOW_OFFSET2 (88d4) + RB_WINDOW_OFFSET2: { X = 1632 | Y = 0 } +0000000001d91f8c: 0000: 4888d401 00000660 +t4 write SP_WINDOW_OFFSET (b4d1) + SP_WINDOW_OFFSET: { X = 1632 | Y = 0 } +0000000001d91f94: 0000: 48b4d101 00000660 +t4 write SP_TP_WINDOW_OFFSET (b307) + SP_TP_WINDOW_OFFSET: { X = 1632 | Y = 0 } +0000000001d91f9c: 0000: 48b30701 00000660 +t4 write GRAS_BIN_CONTROL (80a1) + GRAS_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 } +0000000001d91fa4: 0000: 4880a101 06001e11 +t4 write RB_BIN_CONTROL (8800) + RB_BIN_CONTROL: { BINW = 544 | BINH = 480 | UNK22 = 0x18 } +0000000001d91fac: 0000: 48880001 06001e11 +t4 write RB_BIN_CONTROL2 (88d3) + RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 } +0000000001d91fb4: 0000: 4088d301 00001e11 +t7 opcode: CP_SET_MODE (63) (2 dwords) +0000000001d91fbc: 0000: 70e30001 00000000 +t4 write RB_SAMPLE_CONFIG (8804) + RB_SAMPLE_CONFIG: { 0 } +0000000001d91fc4: 0000: 40880401 00000000 +t4 write SP_TP_SAMPLE_CONFIG (b304) + SP_TP_SAMPLE_CONFIG: { 0 } +0000000001d91fcc: 0000: 48b30401 00000000 +t4 write GRAS_SAMPLE_CONFIG (80a4) + GRAS_SAMPLE_CONFIG: { 0 } +0000000001d91fd4: 0000: 4880a401 00000000 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91fdc: 0000: 70268000 +t4 write CP_SCRATCH[0x6].REG (0889) + CP_SCRATCH[0x6].REG: 45 + :0,1,45,44 +0000000001d91fe0: 0000: 48088901 0000002d +t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) + ibaddr:00000000011160d0 + ibsize:00000018 +0000000001d91fe8: 0000: 70bf8003 011160d0 00000000 00000018 +t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) +0000000001d91ff8: 0000: 70268000 +############################################################ +vertices: 0 +cmd: null_platform_t/2995: fence=1856 +cmd: null_platform_t/2995: fence=1857 diff --git a/src/freedreno/.gitlab-ci/reference/glxgears-a420.log b/src/freedreno/.gitlab-ci/reference/glxgears-a420.log new file mode 100644 index 00000000000..78930e4cacc --- /dev/null +++ b/src/freedreno/.gitlab-ci/reference/glxgears-a420.log @@ -0,0 +1,5664 @@ +Reading src/freedreno/.gitlab-ci/traces/glxgears-a420.rd.gz... +gpu_id: 420 +cmd: X/23360: fence=1029603 +cmd: glxgears/23375: fence=1029604 +############################################################ +cmdstream: 414 dwords +t0 write RBBM_PERFCTR_CTL (0170) + RBBM_PERFCTR_CTL: 0x1 +108ce000: 0000: 00000170 00000001 +t0 write GRAS_DEBUG_ECO_CONTROL (0c81) + GRAS_DEBUG_ECO_CONTROL: 0 +108ce008: 0000: 00000c81 00000000 +t0 write SP_MODE_CONTROL (0ec3) + SP_MODE_CONTROL: 0x6 +108ce010: 0000: 00000ec3 00000006 +t0 write TPL1_TP_MODE_CONTROL (0f03) + TPL1_TP_MODE_CONTROL: 0x3a +108ce018: 0000: 00000f03 0000003a +t0 write UNKNOWN_0D01 (0d01) + UNKNOWN_0D01: 0x1 +108ce020: 0000: 00000d01 00000001 +t0 write UNKNOWN_0E42 (0e42) + UNKNOWN_0E42: 0 +108ce028: 0000: 00000e42 00000000 +t0 write UCHE_CACHE_WAYS_VFD (0e8c) + UCHE_CACHE_WAYS_VFD: 0x7 +108ce030: 0000: 00000e8c 00000007 +t0 write UCHE_CACHE_MODE_CONTROL (0e80) + UCHE_CACHE_MODE_CONTROL: 0 +108ce038: 0000: 00000e80 00000000 +t0 write UCHE_INVALIDATE0 (0e8a) + UCHE_INVALIDATE0: 0 + UCHE_INVALIDATE1: 0x12 +108ce040: 0000: 00010e8a 00000000 00000012 +t0 write HLSQ_MODE_CONTROL (0e05) + HLSQ_MODE_CONTROL: 0 +108ce04c: 0000: 00000e05 00000000 +t0 write UNKNOWN_0CC5 (0cc5) + UNKNOWN_0CC5: 0x6 +108ce054: 0000: 00000cc5 00000006 +t0 write UNKNOWN_0CC6 (0cc6) + UNKNOWN_0CC6: 0 +108ce05c: 0000: 00000cc6 00000000 +t0 write UNKNOWN_0EC2 (0ec2) + UNKNOWN_0EC2: 0x40000 +108ce064: 0000: 00000ec2 00040000 +t0 write UNKNOWN_2001 (2001) + UNKNOWN_2001: 0 +108ce06c: 0000: 00002001 00000000 +t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords) +108ce074: 0000: c0003b00 00001000 +t0 write UNKNOWN_20EF (20ef) + UNKNOWN_20EF: 0 +108ce07c: 0000: 000020ef 00000000 +t0 write RB_BLEND_RED (20f0) + RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + RB_BLEND_RED_F32: 0.000000 + RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + RB_BLEND_GREEN_F32: 0.007813 +108ce084: 0000: 000320f0 00000000 00000000 00000000 3c0000ff +t0 write UNKNOWN_2152 (2152) + UNKNOWN_2152: 0 +108ce098: 0000: 00002152 00000000 +t0 write UNKNOWN_2153 (2153) + UNKNOWN_2153: 0 +108ce0a0: 0000: 00002153 00000000 +t0 write UNKNOWN_2154 (2154) + UNKNOWN_2154: 0 +108ce0a8: 0000: 00002154 00000000 +t0 write UNKNOWN_2155 (2155) + UNKNOWN_2155: 0 +108ce0b0: 0000: 00002155 00000000 +t0 write UNKNOWN_2156 (2156) + UNKNOWN_2156: 0 +108ce0b8: 0000: 00002156 00000000 +t0 write UNKNOWN_2157 (2157) + UNKNOWN_2157: 0 +108ce0c0: 0000: 00002157 00000000 +t0 write UNKNOWN_21C3 (21c3) + UNKNOWN_21C3: 0x1d +108ce0c8: 0000: 000021c3 0000001d +t0 write PC_GS_PARAM (21e5) + PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } +108ce0d0: 0000: 000021e5 00000000 +t0 write UNKNOWN_21E6 (21e6) + UNKNOWN_21E6: 0x1 +108ce0d8: 0000: 000021e6 00000001 +t0 write PC_HS_PARAM (21e7) + PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } +108ce0e0: 0000: 000021e7 00000000 +t0 write UNKNOWN_22D7 (22d7) + UNKNOWN_22D7: 0 +108ce0e8: 0000: 000022d7 00000000 +t0 write TPL1_TP_TEX_OFFSET (2380) + TPL1_TP_TEX_OFFSET: 0 +108ce0f0: 0000: 00002380 00000000 +t0 write TPL1_TP_TEX_COUNT (2381) + TPL1_TP_TEX_COUNT: { VS = 16 | HS = 0 | DS = 0 | GS = 0 } +108ce0f8: 0000: 00002381 00000010 +t0 write TPL1_TP_FS_TEX_COUNT (23a0) + TPL1_TP_FS_TEX_COUNT: 0x10 +108ce100: 0000: 000023a0 00000010 +t3 opcode: CP_SET_DRAW_STATE (43) (3 dwords) + { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } + { ADDR_LO = 0 } +108ce108: 0000: c0014300 00040000 00000000 +t0 write SP_VS_PVT_MEM_PARAM (22e2) + SP_VS_PVT_MEM_PARAM: 0x8000001 + SP_VS_PVT_MEM_ADDR: 0x10cd7000 +108ce114: 0000: 000122e2 08000001 10cd7000 +t0 write SP_FS_PVT_MEM_PARAM (22ec) + SP_FS_PVT_MEM_PARAM: 0x8000001 + SP_FS_PVT_MEM_ADDR: 0x10cd9000 +108ce120: 0000: 000122ec 08000001 10cd9000 +t0 write GRAS_SC_CONTROL (207b) + GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } +108ce12c: 0000: 0000207b 00000800 +t0 write RB_MSAA_CONTROL (20a2) + RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } +108ce134: 0000: 000020a2 00001000 +t0 write GRAS_CL_GB_CLIP_ADJ (2004) + GRAS_CL_GB_CLIP_ADJ: { HORZ = 0 | VERT = 0 } +108ce13c: 0000: 00002004 00000000 +t0 write RB_ALPHA_CONTROL (20f8) + RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_ALWAYS } +108ce144: 0000: 000020f8 00000e00 +t0 write RB_FS_OUTPUT (20f9) + RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } +108ce14c: 0000: 000020f9 ffff0000 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0 } +108ce154: 0000: 00002073 00000000 +t0 write VSC_BIN_SIZE (0c00) + VSC_BIN_SIZE: { WIDTH = 320 | HEIGHT = 320 } +108ce15c: 0000: 00000c00 0000014a +t0 write VSC_SIZE_ADDRESS (0c01) + VSC_SIZE_ADDRESS: 0x10cdb000 +108ce164: 0000: 00000c01 10cdb000 +t0 write VSC_PIPE_CONFIG[0].REG (0c08) + VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 } + VSC_PIPE_CONFIG[0x1].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x2].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x3].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x4].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x5].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x6].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + VSC_PIPE_CONFIG[0x7].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } +108ce16c: 0000: 00070c08 01100000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VSC_PIPE_DATA_ADDRESS[0].REG (0c10) + VSC_PIPE_DATA_ADDRESS[0].REG: 0x10cdc000 + VSC_PIPE_DATA_ADDRESS[0x1].REG: 0x10d1c000 + VSC_PIPE_DATA_ADDRESS[0x2].REG: 0x10d5c000 + VSC_PIPE_DATA_ADDRESS[0x3].REG: 0x10d9c000 + VSC_PIPE_DATA_ADDRESS[0x4].REG: 0x10ddc000 + VSC_PIPE_DATA_ADDRESS[0x5].REG: 0x10e1c000 + VSC_PIPE_DATA_ADDRESS[0x6].REG: 0x10e5c000 + VSC_PIPE_DATA_ADDRESS[0x7].REG: 0x10e9c000 +108ce190: 0000: 00070c10 10cdc000 10d1c000 10d5c000 10d9c000 10ddc000 10e1c000 10e5c000 +108ce1b0: 0020: 10e9c000 +t0 write VSC_PIPE_DATA_LENGTH[0].REG (0c18) + VSC_PIPE_DATA_LENGTH[0].REG: 0x3ffe0 + VSC_PIPE_DATA_LENGTH[0x1].REG: 0x3ffe0 + VSC_PIPE_DATA_LENGTH[0x2].REG: 0x3ffe0 + VSC_PIPE_DATA_LENGTH[0x3].REG: 0x3ffe0 + VSC_PIPE_DATA_LENGTH[0x4].REG: 0x3ffe0 + VSC_PIPE_DATA_LENGTH[0x5].REG: 0x3ffe0 + VSC_PIPE_DATA_LENGTH[0x6].REG: 0x3ffe0 + VSC_PIPE_DATA_LENGTH[0x7].REG: 0x3ffe0 +108ce1b4: 0000: 00070c18 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0 0003ffe0 +108ce1d4: 0020: 0003ffe0 +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +108ce1d8: 0000: c0002600 00000000 +t0 write RB_FRAME_BUFFER_DIMENSION (0ce0) + RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 } +108ce1e0: 0000: 00000ce0 012c012c +t0 write RB_MODE_CONTROL (20a0) + RB_MODE_CONTROL: { WIDTH = 320 | HEIGHT = 320 | ENABLE_GMEM } +108ce1e8: 0000: 000020a0 00010a0a +t0 write RB_DEPTH_INFO (2103) + RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_24_8 | DEPTH_BASE = 0x64000 } + RB_DEPTH_PITCH: 1280 + RB_DEPTH_PITCH2: 1280 +108ce1f0: 0000: 00022103 00064002 00000028 00000028 +t0 write RB_STENCIL_INFO (2108) + RB_STENCIL_INFO: { STENCIL_BASE = 0 } + RB_STENCIL_PITCH: 0 +108ce200: 0000: 00012108 00000000 00000000 +t0 write GRAS_DEPTH_CONTROL (2077) + GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_24_8 } +108ce20c: 0000: 00002077 00000002 +t0 write PC_VSTREAM_CONTROL (21c2) + PC_VSTREAM_CONTROL: { SIZE = 0 | N = 0 } +108ce214: 0000: 000021c2 00000000 +t3 opcode: (null) (4c) (4 dwords) +108ce21c: 0000: c0024c00 00000000 00000000 012b012b +t0 write RB_MRT[0].BUF_INFO (20a5) + RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 1280 } + RB_MRT[0].BASE: 0 + RB_MRT[0].CONTROL3: { STRIDE = 1280 } +108ce22c: 0000: 000220a5 0014089a 00000000 00002800 +t0 write RB_MRT[0x1].BUF_INFO (20aa) + RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x1].BASE: 0 + RB_MRT[0x1].CONTROL3: { STRIDE = 0 } +108ce23c: 0000: 000220aa 00000080 00000000 00000000 +t0 write RB_MRT[0x2].BUF_INFO (20af) + RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x2].BASE: 0 + RB_MRT[0x2].CONTROL3: { STRIDE = 0 } +108ce24c: 0000: 000220af 00000080 00000000 00000000 +t0 write RB_MRT[0x3].BUF_INFO (20b4) + RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x3].BASE: 0 + RB_MRT[0x3].CONTROL3: { STRIDE = 0 } +108ce25c: 0000: 000220b4 00000080 00000000 00000000 +t0 write RB_MRT[0x4].BUF_INFO (20b9) + RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x4].BASE: 0 + RB_MRT[0x4].CONTROL3: { STRIDE = 0 } +108ce26c: 0000: 000220b9 00000080 00000000 00000000 +t0 write RB_MRT[0x5].BUF_INFO (20be) + RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x5].BASE: 0 + RB_MRT[0x5].CONTROL3: { STRIDE = 0 } +108ce27c: 0000: 000220be 00000080 00000000 00000000 +t0 write RB_MRT[0x6].BUF_INFO (20c3) + RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x6].BASE: 0 + RB_MRT[0x6].CONTROL3: { STRIDE = 0 } +108ce28c: 0000: 000220c3 00000080 00000000 00000000 +t0 write RB_MRT[0x7].BUF_INFO (20c8) + RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + RB_MRT[0x7].BASE: 0 + RB_MRT[0x7].CONTROL3: { STRIDE = 0 } +108ce29c: 0000: 000220c8 00000080 00000000 00000000 +t0 write RB_BIN_OFFSET (210d) + RB_BIN_OFFSET: { X = 0 | Y = 0 } +108ce2ac: 0000: 0000210d 00000000 +t0 write GRAS_SC_SCREEN_SCISSOR_TL (207c) + GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } + GRAS_SC_SCREEN_SCISSOR_BR: { X = 299 | Y = 299 } +108ce2b4: 0000: 0001207c 00000000 012b012b +t0 write RB_RENDER_CONTROL (20a1) + RB_RENDER_CONTROL: { 0x8 } +108ce2c0: 0000: 000020a1 00000008 +t0 write CP_SCRATCH[0x6].REG (057e) + CP_SCRATCH[0x6].REG: 0x73 + :0,0,115,0 +108ce2c8: 0000: 0000057e 00000073 +t3 opcode: CP_INDIRECT_BUFFER (3f) (3 dwords) + ibaddr:109ce000 + ibsize:00000f2e +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x1 + :0,1,115,0 +109ce000: 0000: 0000057d 00000001 +t0 write RB_RENDER_COMPONENTS (20fb) + RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } +109ce008: 0000: 000020fb 0000000f +t0 write RB_ALPHA_CONTROL (20f8) + RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } +109ce010: 0000: 000020f8 00000000 +t0 write RB_STENCIL_CONTROL (2106) + RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + RB_STENCIL_CONTROL2: { 0 } +109ce018: 0000: 00012106 00000000 00000000 +t0 write RB_STENCILREFMASK (210b) + RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } +109ce024: 0000: 0001210b 00000000 00000000 +t0 write RB_DEPTH_CONTROL (2101) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS | Z_TEST_ENABLE } +109ce030: 0000: 00002101 80000076 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0 } +109ce038: 0000: 00002073 00000000 +t0 write GRAS_SU_MODE_CONTROL (2078) + GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.000000 | RENDERING_PASS } +109ce040: 0000: 00002078 00100004 +t0 write GRAS_SU_POINT_MINMAX (2070) + GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } + GRAS_SU_POINT_SIZE: 0.000000 +109ce048: 0000: 00012070 00000000 00000000 +t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) + GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 +109ce054: 0000: 00022074 00000000 00000000 00000000 +t0 write GRAS_CL_CLIP_CNTL (2000) + GRAS_CL_CLIP_CNTL: { 0x80000 } +109ce064: 0000: 00002000 00080000 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109ce06c: 0000: 000121c4 02000000 00000012 +t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) + GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +109ce078: 0000: 0001209c 012b012b 00000000 +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109ce084: 0000: c0002600 00000000 +t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) + GRAS_CL_VPORT_XOFFSET_0: 150.000000 + GRAS_CL_VPORT_XSCALE_0: 150.000000 + GRAS_CL_VPORT_YOFFSET_0: 150.000000 + GRAS_CL_VPORT_YSCALE_0: -150.000000 + GRAS_CL_VPORT_ZOFFSET_0: 0.000000 + GRAS_CL_VPORT_ZSCALE_0: 1.000000 +109ce08c: 0000: 00052008 43160000 43160000 43160000 c3160000 00000000 3f800000 +t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) + RB_VPORT_Z_CLAMP[0].MIN: 0 + RB_VPORT_Z_CLAMP[0].MAX: 0xffffff +109ce0a8: 0000: 00012120 00000000 00ffffff +t0 write HLSQ_UPDATE_CONTROL (23db) + HLSQ_UPDATE_CONTROL: 0x3 +109ce0b4: 0000: 000023db 00000003 +t0 write HLSQ_CONTROL_0_REG (23c0) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +109ce0bc: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc +t0 write HLSQ_VS_CONTROL_REG (23c5) + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +109ce0d4: 0000: 000423c5 01000042 017e423e 007e4200 007e4200 007e4200 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { 0x140010 } +109ce0ec: 0000: 000022c0 00140010 +t0 write SP_INSTR_CACHE_CTRL (22c1) + SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +109ce0f4: 0000: 000022c1 000005ff +t0 write SP_VS_LENGTH_REG (22e5) + SP_VS_LENGTH_REG: 1 +109ce0fc: 0000: 000022e5 00000001 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } + SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } +109ce104: 0000: 000222c4 00200400 04000042 0000fc00 +t0 write SP_VS_OBJ_OFFSET_REG (22e0) + SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + SP_VS_OBJ_START: 0x1073c000 +109ce114: 0000: 000122e0 00000000 1073c000 +t0 write SP_FS_LENGTH_REG (22ef) + SP_FS_LENGTH_REG: 1 +109ce120: 0000: 000022ef 00000001 +t0 write SP_FS_CTRL_REG0 (22e8) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 } +109ce128: 0000: 000122e8 00340400 8000003e +t0 write SP_FS_OBJ_OFFSET_REG (22ea) + SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + SP_FS_OBJ_START: 0x1073b000 +109ce134: 0000: 000122ea 7e420000 1073b000 +t0 write SP_HS_OBJ_OFFSET_REG (230d) + SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109ce140: 0000: 0000230d 7e420000 +t0 write SP_DS_OBJ_OFFSET_REG (2334) + SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109ce148: 0000: 00002334 7e420000 +t0 write SP_GS_OBJ_OFFSET_REG (235b) + SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109ce150: 0000: 0000235b 7e420000 +t0 write GRAS_CNTL (2003) + GRAS_CNTL: { 0 } +109ce158: 0000: 00002003 00000000 +t0 write RB_RENDER_CONTROL2 (20a3) + RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } +109ce160: 0000: 000020a3 00000000 +t0 write RB_FS_OUTPUT_REG (2100) + RB_FS_OUTPUT_REG: { MRT = 1 } +109ce168: 0000: 00002100 00000001 +t0 write SP_FS_OUTPUT_REG (22f0) + SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +109ce170: 0000: 000022f0 0000fc01 +t0 write SP_FS_MRT[0].REG (22f1) + SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } +109ce178: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_ATTR (2140) + VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 } + VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } +109ce19c: 0000: 00012140 40001000 00000000 +t0 write VPC_VARYING_INTERP[0].MODE (2142) + VPC_VARYING_INTERP[0].MODE: 0 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +109ce1a8: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_VARYING_PS_REPL[0].MODE (214a) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +109ce1cc: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :0:0000:0000[03000000x_00000000x] end + :0:0001:0001[00000000x_00000000x] nop + :0:0002:0002[00000000x_00000000x] nop + :0:0003:0003[00000000x_00000000x] nop + :0:0004:0004[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): (cnt=0, max=0) + - used (merged): (cnt=0, max=0) + - input (half): (cnt=0, max=0) + - input (full): (cnt=0, max=0) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): (cnt=0, max=0) (estimated) + - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full + - shaderdb: 0 (ss), 0 (sy) +109ce1f0: 0000: c0213000 00600000 00000000 00000000 03000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :1:0000:0000[20244000x_00000000x] mov.f32f32 r0.x, c0.x + :1:0001:0001[20244001x_00000001x] mov.f32f32 r0.y, c0.y + :1:0002:0002[20244002x_00000002x] mov.f32f32 r0.z, c0.z + :1:0003:0003[20244003x_00000003x] mov.f32f32 r0.w, c0.w + :0:0004:0004[03000000x_00000000x] end + :0:0005:0005[00000000x_00000000x] nop + :0:0006:0006[00000000x_00000000x] nop + :0:0007:0007[00000000x_00000000x] nop + :0:0008:0008[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-3 (cnt=4, max=3) + - used (merged): 0-7 (cnt=8, max=7) + - input (half): (cnt=0, max=0) + - input (full): (cnt=0, max=0) + - const (half): (cnt=0, max=0) + - const (full): 0-3 (cnt=4, max=3) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 0-3 (cnt=4, max=3) (estimated) + - shaderdb: 9 instructions, 8 nops, 1 non-nops, (9 instlen), 0 half, 1 full + - shaderdb: 0 (ss), 0 (sy) +109ce27c: 0000: c0213000 00700000 00000000 00000000 20244000 00000001 20244001 00000002 +109ce29c: 0020: 20244002 00000003 20244003 00000000 03000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (19 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109ce314: 0.000000 0.000000 0.000000 0.000000 -nan -nan 0.000000 0.000000 +109ce334: 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 +109ce314: 0000: 00000000 00000000 00000000 00000000 ffffffff ffffffff 00000405 00000000 +109ce334: 0020: 00000000 00000000 02070000 00000000 00000000 00000000 00000000 00000000 +109ce308: 0000: c0113000 01300000 00000001 00000000 00000000 00000000 00000000 ffffffff +109ce328: 0020: ffffffff 00000405 00000000 00000000 00000000 02070000 00000000 00000000 +* +t0 write RB_MRT[0].CONTROL (20a4) + RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +109ce354: 0000: 000020a4 0f000c00 +t0 write RB_MRT[0].BLEND_CONTROL (20a8) + RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109ce35c: 0000: 000020a8 00000000 +t0 write RB_MRT[0x1].CONTROL (20a9) + RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +109ce364: 0000: 000020a9 00000c00 +t0 write RB_MRT[0x1].BLEND_CONTROL (20ad) + RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109ce36c: 0000: 000020ad 00000000 +t0 write RB_MRT[0x2].CONTROL (20ae) + RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +109ce374: 0000: 000020ae 00000c00 +t0 write RB_MRT[0x2].BLEND_CONTROL (20b2) + RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109ce37c: 0000: 000020b2 00000000 +t0 write RB_MRT[0x3].CONTROL (20b3) + RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +109ce384: 0000: 000020b3 00000c00 +t0 write RB_MRT[0x3].BLEND_CONTROL (20b7) + RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109ce38c: 0000: 000020b7 00000000 +t0 write RB_MRT[0x4].CONTROL (20b8) + RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +109ce394: 0000: 000020b8 00000c00 +t0 write RB_MRT[0x4].BLEND_CONTROL (20bc) + RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109ce39c: 0000: 000020bc 00000000 +t0 write RB_MRT[0x5].CONTROL (20bd) + RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +109ce3a4: 0000: 000020bd 00000c00 +t0 write RB_MRT[0x5].BLEND_CONTROL (20c1) + RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109ce3ac: 0000: 000020c1 00000000 +t0 write RB_MRT[0x6].CONTROL (20c2) + RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +109ce3b4: 0000: 000020c2 00000c00 +t0 write RB_MRT[0x6].BLEND_CONTROL (20c6) + RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109ce3bc: 0000: 000020c6 00000000 +t0 write RB_MRT[0x7].CONTROL (20c7) + RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +109ce3c4: 0000: 000020c7 00000c00 +t0 write RB_MRT[0x7].BLEND_CONTROL (20cb) + RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109ce3cc: 0000: 000020cb 00000000 +t0 write RB_FS_OUTPUT (20f9) + RB_FS_OUTPUT: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff } +109ce3d4: 0000: 000020f9 ffff0100 +t0 write RB_BLEND_RED (20f0) + RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + RB_BLEND_RED_F32: 0.000000 + RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + RB_BLEND_GREEN_F32: 0.000000 + RB_BLEND_BLUE: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + RB_BLEND_BLUE_F32: 0.000000 + RB_BLEND_ALPHA: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + RB_BLEND_ALPHA_F32: 0.000000 +109ce3dc: 0000: 000720f0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VFD_FETCH[0].INSTR_0 (220a) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } + VFD_FETCH[0].INSTR_1: 0x1074a000 + VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 } + VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +109ce400: 0000: 0003220a 0000060b 1074a000 00001000 00000001 +t0 write VFD_DECODE[0].INSTR (228a) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +109ce414: 0000: 0000228a 2c0000df +t0 write VFD_CONTROL_0 (2200) + VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } + VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + VFD_CONTROL_2: 0 + VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + VFD_CONTROL_4: 0 +109ce41c: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000 +t0 write UCHE_INVALIDATE0 (0e8a) + UCHE_INVALIDATE0: 0 + UCHE_INVALIDATE1: 0x12 +109ce434: 0000: 00010e8a 00000000 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109ce440: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109ce44c: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x2 + :0,1,115,2 +109ce454: 0000: 0000057f 00000002 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 2 } + draw[0] register values +!+ 00000001 RBBM_PERFCTR_CTL: 0x1 +!+ 00000001 CP_SCRATCH[0x5].REG: 0x1 + :0,1,115,2 +!+ 00000073 CP_SCRATCH[0x6].REG: 0x73 + :0,1,115,2 +!+ 00000002 CP_SCRATCH[0x7].REG: 0x2 + :0,1,115,2 +!+ 0000014a VSC_BIN_SIZE: { WIDTH = 320 | HEIGHT = 320 } +!+ 10cdb000 VSC_SIZE_ADDRESS: 0x10cdb000 +!+ 01100000 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 } + + 00000000 VSC_PIPE_CONFIG[0x1].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x2].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x3].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x4].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x5].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x6].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + + 00000000 VSC_PIPE_CONFIG[0x7].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } +!+ 10cdc000 VSC_PIPE_DATA_ADDRESS[0].REG: 0x10cdc000 +!+ 10d1c000 VSC_PIPE_DATA_ADDRESS[0x1].REG: 0x10d1c000 +!+ 10d5c000 VSC_PIPE_DATA_ADDRESS[0x2].REG: 0x10d5c000 +!+ 10d9c000 VSC_PIPE_DATA_ADDRESS[0x3].REG: 0x10d9c000 +!+ 10ddc000 VSC_PIPE_DATA_ADDRESS[0x4].REG: 0x10ddc000 +!+ 10e1c000 VSC_PIPE_DATA_ADDRESS[0x5].REG: 0x10e1c000 +!+ 10e5c000 VSC_PIPE_DATA_ADDRESS[0x6].REG: 0x10e5c000 +!+ 10e9c000 VSC_PIPE_DATA_ADDRESS[0x7].REG: 0x10e9c000 +!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0].REG: 0x3ffe0 +!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x1].REG: 0x3ffe0 +!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x2].REG: 0x3ffe0 +!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x3].REG: 0x3ffe0 +!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x4].REG: 0x3ffe0 +!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x5].REG: 0x3ffe0 +!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x6].REG: 0x3ffe0 +!+ 0003ffe0 VSC_PIPE_DATA_LENGTH[0x7].REG: 0x3ffe0 + + 00000000 GRAS_DEBUG_ECO_CONTROL: 0 +!+ 00000006 UNKNOWN_0CC5: 0x6 + + 00000000 UNKNOWN_0CC6: 0 +!+ 012c012c RB_FRAME_BUFFER_DIMENSION: { WIDTH = 300 | HEIGHT = 300 } +!+ 00000001 UNKNOWN_0D01: 0x1 + + 00000000 HLSQ_MODE_CONTROL: 0 + + 00000000 UNKNOWN_0E42: 0 + + 00000000 UCHE_CACHE_MODE_CONTROL: 0 + + 00000000 UCHE_INVALIDATE0: 0 +!+ 00000012 UCHE_INVALIDATE1: 0x12 +!+ 00000007 UCHE_CACHE_WAYS_VFD: 0x7 +!+ 00040000 UNKNOWN_0EC2: 0x40000 +!+ 00000006 SP_MODE_CONTROL: 0x6 +!+ 0000003a TPL1_TP_MODE_CONTROL: 0x3a +!+ 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + + 00000000 UNKNOWN_2001: 0 + + 00000000 GRAS_CNTL: { 0 } + + 00000000 GRAS_CL_GB_CLIP_ADJ: { HORZ = 0 | VERT = 0 } +!+ 43160000 GRAS_CL_VPORT_XOFFSET_0: 150.000000 +!+ 43160000 GRAS_CL_VPORT_XSCALE_0: 150.000000 +!+ 43160000 GRAS_CL_VPORT_YOFFSET_0: 150.000000 +!+ c3160000 GRAS_CL_VPORT_YSCALE_0: -150.000000 + + 00000000 GRAS_CL_VPORT_ZOFFSET_0: 0.000000 +!+ 3f800000 GRAS_CL_VPORT_ZSCALE_0: 1.000000 + + 00000000 GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 } + + 00000000 GRAS_SU_POINT_SIZE: 0.000000 + + 00000000 GRAS_ALPHA_CONTROL: { 0 } + + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 +!+ 00000002 GRAS_DEPTH_CONTROL: { FORMAT = DEPTH4_24_8 } +!+ 00100004 GRAS_SU_MODE_CONTROL: { FRONT_CW | LINEHALFWIDTH = 0.000000 | RENDERING_PASS } +!+ 00000800 GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } + + 00000000 GRAS_SC_SCREEN_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 012b012b GRAS_SC_SCREEN_SCISSOR_BR: { X = 299 | Y = 299 } +!+ 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 00010a0a RB_MODE_CONTROL: { WIDTH = 320 | HEIGHT = 320 | ENABLE_GMEM } +!+ 00000008 RB_RENDER_CONTROL: { 0x8 } +!+ 00001000 RB_MSAA_CONTROL: { DISABLE | SAMPLES = 0 } + + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } +!+ 0f000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +!+ 0014089a RB_MRT[0].BUF_INFO: { COLOR_FORMAT = RB4_R8G8B8A8_UNORM | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WXYZ | COLOR_BUF_PITCH = 1280 } + + 00000000 RB_MRT[0].BASE: 0 +!+ 00002800 RB_MRT[0].CONTROL3: { STRIDE = 1280 } + + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 00000c00 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +!+ 00000080 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x1].BASE: 0 + + 00000000 RB_MRT[0x1].CONTROL3: { STRIDE = 0 } + + 00000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 00000c00 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +!+ 00000080 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x2].BASE: 0 + + 00000000 RB_MRT[0x2].CONTROL3: { STRIDE = 0 } + + 00000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 00000c00 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +!+ 00000080 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x3].BASE: 0 + + 00000000 RB_MRT[0x3].CONTROL3: { STRIDE = 0 } + + 00000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 00000c00 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +!+ 00000080 RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x4].BASE: 0 + + 00000000 RB_MRT[0x4].CONTROL3: { STRIDE = 0 } + + 00000000 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 00000c00 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +!+ 00000080 RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x5].BASE: 0 + + 00000000 RB_MRT[0x5].CONTROL3: { STRIDE = 0 } + + 00000000 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 00000c00 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +!+ 00000080 RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x6].BASE: 0 + + 00000000 RB_MRT[0x6].CONTROL3: { STRIDE = 0 } + + 00000000 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 00000c00 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0 } +!+ 00000080 RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE4_2 | DITHER_MODE = DITHER_DISABLE | COLOR_SWAP = WZYX | COLOR_BUF_PITCH = 0 } + + 00000000 RB_MRT[0x7].BASE: 0 + + 00000000 RB_MRT[0x7].CONTROL3: { STRIDE = 0 } + + 00000000 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + + 00000000 UNKNOWN_20EF: 0 + + 00000000 RB_BLEND_RED: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + + 00000000 RB_BLEND_RED_F32: 0.000000 + + 00000000 RB_BLEND_GREEN: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + + 00000000 RB_BLEND_GREEN_F32: 0.000000 + + 00000000 RB_BLEND_BLUE: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + + 00000000 RB_BLEND_BLUE_F32: 0.000000 + + 00000000 RB_BLEND_ALPHA: { UINT = 0 | SINT = 0 | FLOAT = 0.000000 } + + 00000000 RB_BLEND_ALPHA_F32: 0.000000 + + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } +!+ ffff0100 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff } +!+ 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } +!+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } +!+ 80000076 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS | Z_TEST_ENABLE } +!+ 00064002 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_24_8 | DEPTH_BASE = 0x64000 } +!+ 00000028 RB_DEPTH_PITCH: 1280 +!+ 00000028 RB_DEPTH_PITCH2: 1280 + + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + + 00000000 RB_STENCIL_CONTROL2: { 0 } + + 00000000 RB_STENCIL_INFO: { STENCIL_BASE = 0 } + + 00000000 RB_STENCIL_PITCH: 0 + + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + + 00000000 RB_BIN_OFFSET: { X = 0 | Y = 0 } + + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 +!+ 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff +!+ 40001000 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 } + + 00000000 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } + + 00000000 VPC_VARYING_INTERP[0].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + + 00000000 UNKNOWN_2152: 0 + + 00000000 UNKNOWN_2153: 0 + + 00000000 UNKNOWN_2154: 0 + + 00000000 UNKNOWN_2155: 0 + + 00000000 UNKNOWN_2156: 0 + + 00000000 UNKNOWN_2157: 0 + + 00000000 PC_VSTREAM_CONTROL: { SIZE = 0 | N = 0 } +!+ 0000001d UNKNOWN_21C3: 0x1d +!+ 02000000 PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST } +!+ 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +!+ ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 PC_GS_PARAM: { MAX_VERTICES = 0 | INVOCATIONS = 0 | PRIMTYPE = PC_DRAW_POINTS } +!+ 00000001 UNKNOWN_21E6: 0x1 + + 00000000 PC_HS_PARAM: { VERTICES_OUT = 0 | SPACING = EQUAL_SPACING } +!+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } +!+ fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + + 00000000 VFD_CONTROL_2: 0 +!+ 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + + 00000000 VFD_CONTROL_4: 0 + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +!+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } +!+ 1074a000 VFD_FETCH[0].INSTR_1: 0x1074a000 +!+ 00001000 VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 } +!+ 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +!+ 2c0000df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +!+ 00140010 SP_SP_CTRL_REG: { 0x140010 } +!+ 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +!+ 00200400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } +!+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } +!+ 0000fc00 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } + + 00000000 UNKNOWN_22D7: 0 + + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } +!+ 1073c000 SP_VS_OBJ_START: 0x1073c000 +!+ 08000001 SP_VS_PVT_MEM_PARAM: 0x8000001 +!+ 10cd7000 SP_VS_PVT_MEM_ADDR: 0x10cd7000 +!+ 00000001 SP_VS_LENGTH_REG: 1 +!+ 00340400 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } +!+ 8000003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 } +!+ 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +!+ 1073b000 SP_FS_OBJ_START: 0x1073b000 +!+ 08000001 SP_FS_PVT_MEM_PARAM: 0x8000001 +!+ 10cd9000 SP_FS_PVT_MEM_ADDR: 0x10cd9000 +!+ 00000001 SP_FS_LENGTH_REG: 1 +!+ 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +!+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +!+ 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +!+ 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 00000000 TPL1_TP_TEX_OFFSET: 0 +!+ 00000010 TPL1_TP_TEX_COUNT: { VS = 16 | HS = 0 | DS = 0 | GS = 0 } +!+ 00000010 TPL1_TP_FS_TEX_COUNT: 0x10 +!+ 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } +!+ fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } +!+ fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } +!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } +!+ 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +!+ 01000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } +!+ 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } +!+ 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +!+ 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +!+ 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +!+ 00000003 HLSQ_UPDATE_CONTROL: 0x3 +109ce45c: 0000: c0023800 00000888 00000001 00000002 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x3 + :0,1,115,3 +109ce46c: 0000: 0000057f 00000003 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x7 + :0,7,115,3 +109ce474: 0000: 0000057d 00000007 +t0 write RB_ALPHA_CONTROL (20f8) + RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } +109ce47c: 0000: 000020f8 00000000 +t0 write RB_STENCIL_CONTROL (2106) + RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + RB_STENCIL_CONTROL2: { 0 } +109ce484: 0000: 00012106 00000000 00000000 +t0 write RB_STENCILREFMASK (210b) + RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } +109ce490: 0000: 0001210b 00000000 00000000 +t0 write RB_DEPTH_CONTROL (2101) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } +109ce49c: 0000: 00002101 80000016 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0 } +109ce4a4: 0000: 00002073 00000000 +t0 write GRAS_SU_MODE_CONTROL (2078) + GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } +109ce4ac: 0000: 00002078 00100012 +t0 write GRAS_SU_POINT_MINMAX (2070) + GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + GRAS_SU_POINT_SIZE: 1.000000 +109ce4b4: 0000: 00012070 00100010 00000010 +t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) + GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 +109ce4c0: 0000: 00022074 00000000 00000000 00000000 +t0 write GRAS_CL_CLIP_CNTL (2000) + GRAS_CL_CLIP_CNTL: { 0x80000 } +109ce4d0: 0000: 00002000 00080000 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109ce4d8: 0000: 000121c4 02000001 00000012 +t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) + GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +109ce4e4: 0000: 0001209c 012b012b 00000000 +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109ce4f0: 0000: c0002600 00000000 +t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) + GRAS_CL_VPORT_XOFFSET_0: 150.000000 + GRAS_CL_VPORT_XSCALE_0: 150.000000 + GRAS_CL_VPORT_YOFFSET_0: 150.000000 + GRAS_CL_VPORT_YSCALE_0: -150.000000 + GRAS_CL_VPORT_ZOFFSET_0: 0.500000 + GRAS_CL_VPORT_ZSCALE_0: 0.500000 +109ce4f8: 0000: 00052008 43160000 43160000 43160000 c3160000 3f000000 3f000000 +t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) + RB_VPORT_Z_CLAMP[0].MIN: 0 + RB_VPORT_Z_CLAMP[0].MAX: 0xffffff +109ce514: 0000: 00012120 00000000 00ffffff +t0 write HLSQ_UPDATE_CONTROL (23db) + HLSQ_UPDATE_CONTROL: 0x3 +109ce520: 0000: 000023db 00000003 +t0 write HLSQ_CONTROL_0_REG (23c0) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +109ce528: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc +t0 write HLSQ_VS_CONTROL_REG (23c5) + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +109ce540: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { 0x140010 } +109ce558: 0000: 000022c0 00140010 +t0 write SP_INSTR_CACHE_CTRL (22c1) + SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +109ce560: 0000: 000022c1 000005ff +t0 write SP_VS_LENGTH_REG (22e5) + SP_VS_LENGTH_REG: 4 +109ce568: 0000: 000022e5 00000004 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } + SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +109ce570: 0000: 000222c4 00201000 04000042 0010fc06 +t0 write SP_VS_OUT[0].REG (22c7) + SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +109ce580: 0000: 000022c7 00001e0a +t0 write SP_VS_VPC_DST[0].REG (22d8) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } +109ce588: 0000: 000022d8 08080808 +t0 write SP_VS_OBJ_OFFSET_REG (22e0) + SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + SP_VS_OBJ_START: 0x10cd0000 +109ce590: 0000: 000122e0 00000000 10cd0000 +t0 write SP_FS_LENGTH_REG (22ef) + SP_FS_LENGTH_REG: 1 +109ce59c: 0000: 000022ef 00000001 +t0 write SP_FS_CTRL_REG0 (22e8) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } +109ce5a4: 0000: 000122e8 00340402 8010003e +t0 write SP_FS_OBJ_OFFSET_REG (22ea) + SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + SP_FS_OBJ_START: 0x10cd2000 +109ce5b0: 0000: 000122ea 7e420000 10cd2000 +t0 write SP_HS_OBJ_OFFSET_REG (230d) + SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109ce5bc: 0000: 0000230d 7e420000 +t0 write SP_DS_OBJ_OFFSET_REG (2334) + SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109ce5c4: 0000: 00002334 7e420000 +t0 write SP_GS_OBJ_OFFSET_REG (235b) + SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109ce5cc: 0000: 0000235b 7e420000 +t0 write GRAS_CNTL (2003) + GRAS_CNTL: { 0 } +109ce5d4: 0000: 00002003 00000000 +t0 write RB_RENDER_CONTROL2 (20a3) + RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } +109ce5dc: 0000: 000020a3 00000000 +t0 write RB_FS_OUTPUT_REG (2100) + RB_FS_OUTPUT_REG: { MRT = 1 } +109ce5e4: 0000: 00002100 00000001 +t0 write SP_FS_OUTPUT_REG (22f0) + SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +109ce5ec: 0000: 000022f0 0000fc01 +t0 write SP_FS_MRT[0].REG (22f1) + SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } +109ce5f4: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_ATTR (2140) + VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +109ce618: 0000: 00012140 42001004 00040400 +t0 write VPC_VARYING_INTERP[0].MODE (2142) + VPC_VARYING_INTERP[0].MODE: 0x55 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +109ce624: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_VARYING_PS_REPL[0].MODE (214a) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +109ce648: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x + :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w + :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x + :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y + :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x + :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y + :3:0006:0006[63828006x_0000100cx] mad.f32 r1.z, c3.x, r1.y, r0.x + :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y + :3:0008:0008[63828009x_0001100fx] mad.f32 r2.y, c3.w, r1.y, r0.y + :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x + :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x + :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x + :0:0012:0012[00000000x_00000000x] nop + :3:0013:0013[63828007x_0000100dx] mad.f32 r1.w, c3.y, r1.y, r0.x + :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z + :1:0015:0015[20244002x_00000015x] mov.f32f32 r0.z, c5.y + :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x + :1:0017:0017[20244003x_00000016x] mov.f32f32 r0.w, c5.z + :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x + :1:0019:0019[20244004x_00000017x] mov.f32f32 r1.x, c5.w + :3:0020:0020[63828008x_0000100ex] mad.f32 r2.x, c3.z, r1.y, r0.x + :1:0021:0021[20244000x_00000011x] mov.f32f32 r0.x, c4.y + :2:0022:0022[40100002x_00021021x] add.f r0.z, c8.y, r0.z + :2:0023:0023[4050040dx_00041017x] (sat)max.f r3.y, c5.w, r1.x + :2:0024:0024[40100003x_00031022x] add.f r0.w, c8.z, r0.w + :2:0025:0025[40700000x_00001011x] mul.f r0.x, c4.y, r0.x + :0:0026:0026[00000000x_00000000x] nop + :3:0027:0027[63808000x_00001010x] mad.f32 r0.x, c4.x, r0.y, r0.x + :1:0028:0028[20244001x_00000012x] mov.f32f32 r0.y, c4.z + :0:0029:0029[00000200x_00000000x] (rpt2)nop + :3:0030:0032[63808000x_00001012x] mad.f32 r0.x, c4.z, r0.y, r0.x + :1:0031:0033[20244001x_00000014x] mov.f32f32 r0.y, c5.x + :0:0032:0034[00000200x_00000000x] (rpt2)nop + :2:0033:0037[40100001x_00011020x] add.f r0.y, c8.x, r0.y + :0:0034:0038[00000000x_00000000x] nop + :4:0035:0039[80300000x_00000000x] rsq r0.x, r0.x + :2:0036:0040[40701004x_00001011x] (ss)mul.f r1.x, c4.y, r0.x + :0:0037:0041[00000200x_00000000x] (rpt2)nop + :2:0038:0044[40700004x_10190004x] mul.f r1.x, r1.x, c6.y + :2:0039:0045[40700005x_00001010x] mul.f r1.y, c4.x, r0.x + :0:0040:0046[00000200x_00000000x] (rpt2)nop + :3:0041:0049[63828004x_00041018x] mad.f32 r1.x, c6.x, r1.y, r1.x + :2:0042:0050[40700000x_00001012x] mul.f r0.x, c4.z, r0.x + :0:0043:0051[00000200x_00000000x] (rpt2)nop + :3:0044:0054[63800000x_0004101ax] mad.f32 r0.x, c6.z, r0.x, r1.x + :0:0045:0055[00000200x_00000000x] (rpt2)nop + :2:0046:0058[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x + :2:0047:0059[40500000x_00001034x] max.f r0.x, c13.x, r0.x + :0:0048:0060[00000100x_00000000x] (rpt1)nop + :1:0049:0062[200c4004x_00000004x] cov.u32f32 r1.x, r1.x + :3:0050:0063[63800001x_00011024x] mad.f32 r0.y, c9.x, r0.x, r0.y + :3:0051:0064[63800002x_00021025x] mad.f32 r0.z, c9.y, r0.x, r0.z + :3:0052:0065[63800000x_00031026x] mad.f32 r0.x, c9.z, r0.x, r0.w + :3:0053:0066[6382040ax_00011028x] (sat)mad.f32 r2.z, c10.x, r1.x, r0.y + :3:0054:0067[6382040bx_00021029x] (sat)mad.f32 r2.w, c10.y, r1.x, r0.z + :3:0055:0068[6382040cx_0000102ax] (sat)mad.f32 r3.x, c10.z, r1.x, r0.x + :0:0056:0069[03000000x_00000000x] end + :0:0057:0070[00000000x_00000000x] nop + :0:0058:0071[00000000x_00000000x] nop + :0:0059:0072[00000000x_00000000x] nop + :0:0060:0073[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-13 (cnt=14, max=13) + - used (merged): 0-27 (cnt=28, max=27) + - input (half): (cnt=0, max=0) + - input (full): 2-5 (cnt=4, max=5) + - const (half): (cnt=0, max=0) + - const (full): 0-18 20-26 32-34 36-38 40-42 52 (cnt=36, max=52) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 6-13 (cnt=8, max=13) (estimated) + - shaderdb: 74 instructions, 38 nops, 36 non-nops, (61 instlen), 0 half, 4 full + - shaderdb: 1 (ss), 0 (sy) +109ce66c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 +109ce68c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c +109ce6ac: 0040: 63828006 10010002 40700000 0001100f 63828009 00001005 63818000 00000010 +109ce6cc: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 63828007 10020002 +109ce6ec: 0080: 40700000 00000015 20244002 00001006 63818000 00000016 20244003 0000100a +109ce70c: 00a0: 63820000 00000017 20244004 0000100e 63828008 00000011 20244000 00021021 +109ce72c: 00c0: 40100002 00041017 4050040d 00031022 40100003 00001011 40700000 00000000 +109ce74c: 00e0: 00000000 00001010 63808000 00000012 20244001 00000000 00000200 00001012 +109ce76c: 0100: 63808000 00000014 20244001 00000000 00000200 00011020 40100001 00000000 +109ce78c: 0120: 00000000 00000000 80300000 00001011 40701004 00000000 00000200 10190004 +109ce7ac: 0140: 40700004 00001010 40700005 00000000 00000200 00041018 63828004 00001012 +109ce7cc: 0160: 40700000 00000000 00000200 0004101a 63800000 00000000 00000200 00001034 +109ce7ec: 0180: 40b00004 00001034 40500000 00000000 00000100 00000004 200c4004 00011024 +109ce80c: 01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029 +109ce82c: 01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :0:0000:0000[00000000x_00000000x] nop + :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 + :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 + :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 + :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 + :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x + :0:0006:0006[03000000x_00000000x] end + :0:0007:0007[00000000x_00000000x] nop + :0:0008:0008[00000000x_00000000x] nop + :0:0009:0009[00000000x_00000000x] nop + :0:0010:0010[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-3 252 (cnt=5, max=3) + - used (merged): 0-7 504-505 (cnt=10, max=7) + - input (half): (cnt=0, max=0) + - input (full): 0-3 (cnt=4, max=3) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 252 (cnt=1, max=0) (estimated) + - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full + - shaderdb: 1 (ss), 0 (sy) +109ce878: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 +109ce898: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 +109ce8b8: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109ce910: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020 +109ce930: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502 +109ce950: 0.000000 0.000000 1.000000 1.000000 0.160000 0.020000 0.000000 1.000000 +109ce970: 0.039740 0.662886 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 +109ce990: 0.000000 0.000000 0.000000 1.000000 0.800000 0.100000 0.000000 1.000000 +109ce9b0: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 +109ce910: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43 +109ce930: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917 +109ce950: 0040: 00000000 00000000 3f800000 3f800000 3e23d70b 3ca3d70b 00000000 3f800000 +109ce970: 0060: 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 +109ce990: 0080: 00000000 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 +109ce9b0: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 +109ce904: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 +109ce924: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 +109ce944: 0040: c13f64ac 420e0660 421d1917 00000000 00000000 3f800000 3f800000 3e23d70b +109ce964: 0060: 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000 +109ce984: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3f4ccccd +109ce9a4: 00a0: 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 00000000 +109ce9c4: 00c0: 00000000 00000000 3f800000 +t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) + { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109ce9dc: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 +109ce9dc: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +109ce9d0: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +t0 write RB_MRT[0].CONTROL (20a4) + RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +109ce9ec: 0000: 000020a4 0f000c00 +t0 write RB_MRT[0].BLEND_CONTROL (20a8) + RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109ce9f4: 0000: 000020a8 00000000 +t0 write RB_MRT[0x1].CONTROL (20a9) + RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +109ce9fc: 0000: 000020a9 0f000c00 +t0 write RB_MRT[0x1].BLEND_CONTROL (20ad) + RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109cea04: 0000: 000020ad 00000000 +t0 write RB_MRT[0x2].CONTROL (20ae) + RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +109cea0c: 0000: 000020ae 0f000c00 +t0 write RB_MRT[0x2].BLEND_CONTROL (20b2) + RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109cea14: 0000: 000020b2 00000000 +t0 write RB_MRT[0x3].CONTROL (20b3) + RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +109cea1c: 0000: 000020b3 0f000c00 +t0 write RB_MRT[0x3].BLEND_CONTROL (20b7) + RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109cea24: 0000: 000020b7 00000000 +t0 write RB_MRT[0x4].CONTROL (20b8) + RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +109cea2c: 0000: 000020b8 0f000c00 +t0 write RB_MRT[0x4].BLEND_CONTROL (20bc) + RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109cea34: 0000: 000020bc 00000000 +t0 write RB_MRT[0x5].CONTROL (20bd) + RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +109cea3c: 0000: 000020bd 0f000c00 +t0 write RB_MRT[0x5].BLEND_CONTROL (20c1) + RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109cea44: 0000: 000020c1 00000000 +t0 write RB_MRT[0x6].CONTROL (20c2) + RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +109cea4c: 0000: 000020c2 0f000c00 +t0 write RB_MRT[0x6].BLEND_CONTROL (20c6) + RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109cea54: 0000: 000020c6 00000000 +t0 write RB_MRT[0x7].CONTROL (20c7) + RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } +109cea5c: 0000: 000020c7 0f000c00 +t0 write RB_MRT[0x7].BLEND_CONTROL (20cb) + RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +109cea64: 0000: 000020cb 00000000 +t0 write RB_FS_OUTPUT (20f9) + RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } +109cea6c: 0000: 000020f9 ffff0000 +t0 write VFD_FETCH[0].INSTR_0 (220a) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } + VFD_FETCH[0].INSTR_1: 0x107cb000 + VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +109cea74: 0000: 0003220a 0000060b 107cb000 00100000 00000001 +t0 write VFD_DECODE[0].INSTR (228a) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +109cea88: 0000: 0000228a 2c0020df +t0 write VFD_CONTROL_0 (2200) + VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } + VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + VFD_CONTROL_2: 0 + VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + VFD_CONTROL_4: 0 +109cea90: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000 +t0 write UCHE_INVALIDATE0 (0e8a) + UCHE_INVALIDATE0: 0 + UCHE_INVALIDATE1: 0x12 +109ceaa8: 0000: 00010e8a 00000000 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109ceab4: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109ceac0: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x8 + :0,7,115,8 +109ceac8: 0000: 0000057f 00000008 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 240 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd0000 } + { INDX_SIZE = 480 } + draw[1] register values +!+ 00000007 CP_SCRATCH[0x5].REG: 0x7 + :0,7,115,8 +!+ 00000008 CP_SCRATCH[0x7].REG: 0x8 + :0,7,115,8 + + 00000000 UCHE_INVALIDATE0: 0 + + 00000012 UCHE_INVALIDATE1: 0x12 + + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } + + 00000000 GRAS_CNTL: { 0 } + + 43160000 GRAS_CL_VPORT_XOFFSET_0: 150.000000 + + 43160000 GRAS_CL_VPORT_XSCALE_0: 150.000000 + + 43160000 GRAS_CL_VPORT_YOFFSET_0: 150.000000 + + c3160000 GRAS_CL_VPORT_YSCALE_0: -150.000000 +!+ 3f000000 GRAS_CL_VPORT_ZOFFSET_0: 0.500000 +!+ 3f000000 GRAS_CL_VPORT_ZSCALE_0: 0.500000 +!+ 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } +!+ 00000010 GRAS_SU_POINT_SIZE: 1.000000 + + 00000000 GRAS_ALPHA_CONTROL: { 0 } + + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 +!+ 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } + + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } + + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } + + 0f000c00 RB_MRT[0].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 0f000c00 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 0f000c00 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 0f000c00 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 0f000c00 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 0f000c00 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 0f000c00 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } +!+ 0f000c00 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_COPY | COMPONENT_ENABLE = 0xf } + + 00000000 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } + + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } +!+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff } + + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } +!+ 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } + + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + + 00000000 RB_STENCIL_CONTROL2: { 0 } + + 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + + 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 } + + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 + + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff +!+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } +!+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +!+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 +!+ 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } + + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + + 00000000 VFD_CONTROL_2: 0 + + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + + 00000000 VFD_CONTROL_4: 0 + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 + + 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } +!+ 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 +!+ 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +!+ 2c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } + + 00140010 SP_SP_CTRL_REG: { 0x140010 } + + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +!+ 00201000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + + 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } +!+ 0010fc06 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +!+ 00001e0a SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +!+ 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } + + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } +!+ 10cd0000 SP_VS_OBJ_START: 0x10cd0000 +!+ 00000004 SP_VS_LENGTH_REG: 4 +!+ 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } +!+ 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } + + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +!+ 10cd2000 SP_FS_OBJ_START: 0x10cd2000 + + 00000001 SP_FS_LENGTH_REG: 1 + + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } + + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +!+ 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 00000003 HLSQ_UPDATE_CONTROL: 0x3 +109cead0: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd0000 000001e0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x9 + :0,7,115,9 +109ceaec: 0000: 0000057f 00000009 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0xd + :0,13,115,9 +109ceaf4: 0000: 0000057d 0000000d +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109ceafc: 0000: 000121c4 02000001 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109ceb08: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109ceb14: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0xe + :0,13,115,14 +109ceb1c: 0000: 0000057f 0000000e +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 120 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd01e0 } + { INDX_SIZE = 240 } + draw[2] register values +!+ 0000000d CP_SCRATCH[0x5].REG: 0xd + :0,13,115,14 +!+ 0000000e CP_SCRATCH[0x7].REG: 0xe + :0,13,115,14 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +109ceb24: 0000: c0053800 00000404 00000001 00000078 00000000 10bd01e0 000000f0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0xf + :0,13,115,15 +109ceb40: 0000: 0000057f 0000000f +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x13 + :0,19,115,15 +109ceb48: 0000: 0000057d 00000013 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109ceb50: 0000: 000121c4 02000001 00000012 +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109ceb5c: 0000: c0002600 00000000 +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109ceb70: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020 +109ceb90: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502 +109cebb0: 0.000000 0.000000 -1.000000 1.000000 0.160000 0.020000 0.000000 1.000000 +109cebd0: 0.039740 0.662886 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 +109cebf0: 0.000000 0.000000 0.000000 1.000000 0.800000 0.100000 0.000000 1.000000 +109cec10: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 +109ceb70: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43 +109ceb90: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917 +109cebb0: 0040: 00000000 00000000 bf800000 3f800000 3e23d70b 3ca3d70b 00000000 3f800000 +109cebd0: 0060: 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 +109cebf0: 0080: 00000000 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 +109cec10: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 +109ceb64: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 +109ceb84: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 +109ceba4: 0040: c13f64ac 420e0660 421d1917 00000000 00000000 bf800000 3f800000 3e23d70b +109cebc4: 0060: 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000 3f800000 +109cebe4: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3f4ccccd +109cec04: 00a0: 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 00000000 +109cec24: 00c0: 00000000 00000000 3f800000 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109cec30: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109cec3c: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x14 + :0,19,115,20 +109cec44: 0000: 0000057f 00000014 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 240 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd02d0 } + { INDX_SIZE = 480 } + draw[3] register values +!+ 00000013 CP_SCRATCH[0x5].REG: 0x13 + :0,19,115,20 +!+ 00000014 CP_SCRATCH[0x7].REG: 0x14 + :0,19,115,20 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +109cec4c: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd02d0 000001e0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x15 + :0,19,115,21 +109cec68: 0000: 0000057f 00000015 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x19 + :0,25,115,21 +109cec70: 0000: 0000057d 00000019 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109cec78: 0000: 000121c4 02000001 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109cec84: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109cec90: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x1a + :0,25,115,26 +109cec98: 0000: 0000057f 0000001a +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 120 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd04b0 } + { INDX_SIZE = 240 } + draw[4] register values +!+ 00000019 CP_SCRATCH[0x5].REG: 0x19 + :0,25,115,26 +!+ 0000001a CP_SCRATCH[0x7].REG: 0x1a + :0,25,115,26 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +109ceca0: 0000: c0053800 00000404 00000001 00000078 00000000 10bd04b0 000000f0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x1b + :0,25,115,27 +109cecbc: 0000: 0000057f 0000001b +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x1f + :0,31,115,27 +109cecc4: 0000: 0000057d 0000001f +t0 write RB_DEPTH_CONTROL (2101) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } +109ceccc: 0000: 00002101 80000016 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0 } +109cecd4: 0000: 00002073 00000000 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109cecdc: 0000: 000121c4 02000001 00000012 +t0 write HLSQ_UPDATE_CONTROL (23db) + HLSQ_UPDATE_CONTROL: 0x3 +109cece8: 0000: 000023db 00000003 +t0 write HLSQ_CONTROL_0_REG (23c0) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +109cecf0: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc +t0 write HLSQ_VS_CONTROL_REG (23c5) + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +109ced08: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { 0x140010 } +109ced20: 0000: 000022c0 00140010 +t0 write SP_INSTR_CACHE_CTRL (22c1) + SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +109ced28: 0000: 000022c1 000005ff +t0 write SP_VS_LENGTH_REG (22e5) + SP_VS_LENGTH_REG: 4 +109ced30: 0000: 000022e5 00000004 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } + SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +109ced38: 0000: 000222c4 00201400 08000042 0010fc0a +t0 write SP_VS_OUT[0].REG (22c7) + SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +109ced48: 0000: 000022c7 00001e0e +t0 write SP_VS_VPC_DST[0].REG (22d8) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } +109ced50: 0000: 000022d8 08080808 +t0 write SP_VS_OBJ_OFFSET_REG (22e0) + SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + SP_VS_OBJ_START: 0x10cd5000 +109ced58: 0000: 000122e0 00000000 10cd5000 +t0 write SP_FS_LENGTH_REG (22ef) + SP_FS_LENGTH_REG: 1 +109ced64: 0000: 000022ef 00000001 +t0 write SP_FS_CTRL_REG0 (22e8) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } +109ced6c: 0000: 000122e8 00340402 8010003e +t0 write SP_FS_OBJ_OFFSET_REG (22ea) + SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + SP_FS_OBJ_START: 0x10cd2000 +109ced78: 0000: 000122ea 7e420000 10cd2000 +t0 write SP_HS_OBJ_OFFSET_REG (230d) + SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109ced84: 0000: 0000230d 7e420000 +t0 write SP_DS_OBJ_OFFSET_REG (2334) + SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109ced8c: 0000: 00002334 7e420000 +t0 write SP_GS_OBJ_OFFSET_REG (235b) + SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109ced94: 0000: 0000235b 7e420000 +t0 write GRAS_CNTL (2003) + GRAS_CNTL: { 0 } +109ced9c: 0000: 00002003 00000000 +t0 write RB_RENDER_CONTROL2 (20a3) + RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } +109ceda4: 0000: 000020a3 00000000 +t0 write RB_FS_OUTPUT_REG (2100) + RB_FS_OUTPUT_REG: { MRT = 1 } +109cedac: 0000: 00002100 00000001 +t0 write SP_FS_OUTPUT_REG (22f0) + SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +109cedb4: 0000: 000022f0 0000fc01 +t0 write SP_FS_MRT[0].REG (22f1) + SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } +109cedbc: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_ATTR (2140) + VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +109cede0: 0000: 00012140 42001004 00040400 +t0 write VPC_VARYING_INTERP[0].MODE (2142) + VPC_VARYING_INTERP[0].MODE: 0x55 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +109cedec: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_VARYING_PS_REPL[0].MODE (214a) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +109cee10: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x + :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w + :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x + :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y + :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x + :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y + :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x + :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y + :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y + :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x + :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x + :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x + :0:0012:0012[00000000x_00000000x] nop + :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x + :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z + :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y + :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x + :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y + :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x + :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w + :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x + :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w + :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z + :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x + :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x + :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x + :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z + :0:0027:0027[00000200x_00000000x] (rpt2)nop + :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w + :0:0029:0031[00000000x_00000000x] nop + :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x + :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x + :0:0032:0034[00000200x_00000000x] (rpt2)nop + :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y + :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x + :0:0035:0039[00000200x_00000000x] (rpt2)nop + :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x + :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x + :0:0038:0044[00000200x_00000000x] (rpt2)nop + :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x + :0:0040:0048[00000200x_00000000x] (rpt2)nop + :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x + :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x + :0:0043:0053[00000100x_00000000x] (rpt1)nop + :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x + :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y + :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z + :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w + :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y + :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z + :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x + :0:0051:0062[03000000x_00000000x] end + :0:0052:0063[00000000x_00000000x] nop + :0:0053:0064[00000000x_00000000x] nop + :0:0054:0065[00000000x_00000000x] nop + :0:0055:0066[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-8 10-17 (cnt=17, max=17) + - used (merged): 0-17 20-35 (cnt=34, max=35) + - input (half): (cnt=0, max=0) + - input (full): 2-8 (cnt=7, max=8) + - const (half): (cnt=0, max=0) + - const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 10-17 (cnt=8, max=17) (estimated) + - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full + - shaderdb: 1 (ss), 0 (sy) +109cee34: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 +109cee54: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c +109cee74: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 +109cee94: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 +109ceeb4: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a +109ceed4: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d +109ceef4: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 +109cef14: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 +109cef34: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 +109cef54: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 +109cef74: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 +109cef94: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 +109cefb4: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 +109cefd4: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :0:0000:0000[00000000x_00000000x] nop + :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 + :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 + :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 + :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 + :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x + :0:0006:0006[03000000x_00000000x] end + :0:0007:0007[00000000x_00000000x] nop + :0:0008:0008[00000000x_00000000x] nop + :0:0009:0009[00000000x_00000000x] nop + :0:0010:0010[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-3 252 (cnt=5, max=3) + - used (merged): 0-7 504-505 (cnt=10, max=7) + - input (half): (cnt=0, max=0) + - input (full): 0-3 (cnt=4, max=3) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 252 (cnt=1, max=0) (estimated) + - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full + - shaderdb: 1 (ss), 0 (sy) +109cf040: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 +109cf060: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 +109cf080: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109cf0cc: 0000: c0002600 00000000 +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109cf0e0: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020 +109cf100: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502 +109cf120: 0.160000 0.020000 0.000000 1.000000 0.039740 0.662886 0.747665 0.000000 +109cf140: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 +109cf160: 0.800000 0.100000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 +109cf180: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 +109cf0e0: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43 +109cf100: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917 +109cf120: 0040: 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000 +109cf140: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 +109cf160: 0080: 3f4ccccd 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 +109cf180: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 +109cf0d4: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 +109cf0f4: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 +109cf114: 0040: c13f64ac 420e0660 421d1917 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e +109cf134: 0060: 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 +109cf154: 0080: 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 00000000 +109cf174: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 +109cf194: 00c0: 02020202 02020202 00000202 +t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) + { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109cf1ac: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 +109cf1ac: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +109cf1a0: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +t0 write VFD_FETCH[0].INSTR_0 (220a) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } + VFD_FETCH[0].INSTR_1: 0x107cb000 + VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +109cf1bc: 0000: 0003220a 00080c0b 107cb000 00100000 00000001 +t0 write VFD_DECODE[0].INSTR (228a) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } +109cf1d0: 0000: 0000228a 6c0020df +t0 write VFD_FETCH[0x1].INSTR_0 (220e) + VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } + VFD_FETCH[0x1].INSTR_1: 0x107cb00c + VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } + VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } +109cf1d8: 0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001 +t0 write VFD_DECODE[0x1].INSTR (228b) + VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +109cf1ec: 0000: 0000228b 2c0060df +t0 write VFD_CONTROL_0 (2200) + VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + VFD_CONTROL_2: 0 + VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + VFD_CONTROL_4: 0 +109cf1f4: 0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000 +t0 write UCHE_INVALIDATE0 (0e8a) + UCHE_INVALIDATE0: 0 + UCHE_INVALIDATE1: 0x12 +109cf20c: 0000: 00010e8a 00000000 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109cf218: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109cf224: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x20 + :0,31,115,32 +109cf22c: 0000: 0000057f 00000020 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 480 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd05a0 } + { INDX_SIZE = 960 } + draw[5] register values +!+ 0000001f CP_SCRATCH[0x5].REG: 0x1f + :0,31,115,32 +!+ 00000020 CP_SCRATCH[0x7].REG: 0x20 + :0,31,115,32 + + 00000000 UCHE_INVALIDATE0: 0 + + 00000012 UCHE_INVALIDATE1: 0x12 + + 00000000 GRAS_CNTL: { 0 } + + 00000000 GRAS_ALPHA_CONTROL: { 0 } + + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } + + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } + + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + + 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + + 00000000 VFD_CONTROL_2: 0 + + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + + 00000000 VFD_CONTROL_4: 0 + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +!+ 00080c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } + + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 + + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +!+ 00000c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } +!+ 107cb00c VFD_FETCH[0x1].INSTR_1: 0x107cb00c +!+ 000ffff4 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } +!+ 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } +!+ 6c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } +!+ 2c0060df VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } + + 00140010 SP_SP_CTRL_REG: { 0x140010 } + + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +!+ 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } +!+ 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } +!+ 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +!+ 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } + + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } +!+ 10cd5000 SP_VS_OBJ_START: 0x10cd5000 + + 00000004 SP_VS_LENGTH_REG: 4 + + 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } + + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 10cd2000 SP_FS_OBJ_START: 0x10cd2000 + + 00000001 SP_FS_LENGTH_REG: 1 + + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } + + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 00000003 HLSQ_UPDATE_CONTROL: 0x3 +109cf234: 0000: c0053800 00000404 00000001 000001e0 00000000 10bd05a0 000003c0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x21 + :0,31,115,33 +109cf250: 0000: 0000057f 00000021 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x25 + :0,37,115,33 +109cf258: 0000: 0000057d 00000025 +t0 write RB_DEPTH_CONTROL (2101) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } +109cf260: 0000: 00002101 80000016 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0 } +109cf268: 0000: 00002073 00000000 +t0 write GRAS_SU_MODE_CONTROL (2078) + GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } +109cf270: 0000: 00002078 00100012 +t0 write GRAS_SU_POINT_MINMAX (2070) + GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + GRAS_SU_POINT_SIZE: 1.000000 +109cf278: 0000: 00012070 00100010 00000010 +t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) + GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 +109cf284: 0000: 00022074 00000000 00000000 00000000 +t0 write GRAS_CL_CLIP_CNTL (2000) + GRAS_CL_CLIP_CNTL: { 0x80000 } +109cf294: 0000: 00002000 00080000 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109cf29c: 0000: 000121c4 02000001 00000012 +t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) + GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +109cf2a8: 0000: 0001209c 012b012b 00000000 +t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) + RB_VPORT_Z_CLAMP[0].MIN: 0 + RB_VPORT_Z_CLAMP[0].MAX: 0xffffff +109cf2b4: 0000: 00012120 00000000 00ffffff +t0 write HLSQ_UPDATE_CONTROL (23db) + HLSQ_UPDATE_CONTROL: 0x3 +109cf2c0: 0000: 000023db 00000003 +t0 write HLSQ_CONTROL_0_REG (23c0) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +109cf2c8: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc +t0 write HLSQ_VS_CONTROL_REG (23c5) + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +109cf2e0: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { 0x140010 } +109cf2f8: 0000: 000022c0 00140010 +t0 write SP_INSTR_CACHE_CTRL (22c1) + SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +109cf300: 0000: 000022c1 000005ff +t0 write SP_VS_LENGTH_REG (22e5) + SP_VS_LENGTH_REG: 4 +109cf308: 0000: 000022e5 00000004 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } + SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +109cf310: 0000: 000222c4 00201400 08000042 0010fc0a +t0 write SP_VS_OUT[0].REG (22c7) + SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +109cf320: 0000: 000022c7 00001e0e +t0 write SP_VS_VPC_DST[0].REG (22d8) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } +109cf328: 0000: 000022d8 08080808 +t0 write SP_VS_OBJ_OFFSET_REG (22e0) + SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + SP_VS_OBJ_START: 0x10cd5000 +109cf330: 0000: 000122e0 00000000 10cd5000 +t0 write SP_FS_LENGTH_REG (22ef) + SP_FS_LENGTH_REG: 1 +109cf33c: 0000: 000022ef 00000001 +t0 write SP_FS_CTRL_REG0 (22e8) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } +109cf344: 0000: 000122e8 00340802 8010003e +t0 write SP_FS_OBJ_OFFSET_REG (22ea) + SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + SP_FS_OBJ_START: 0x108cb000 +109cf350: 0000: 000122ea 7e420000 108cb000 +t0 write SP_HS_OBJ_OFFSET_REG (230d) + SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109cf35c: 0000: 0000230d 7e420000 +t0 write SP_DS_OBJ_OFFSET_REG (2334) + SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109cf364: 0000: 00002334 7e420000 +t0 write SP_GS_OBJ_OFFSET_REG (235b) + SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109cf36c: 0000: 0000235b 7e420000 +t0 write GRAS_CNTL (2003) + GRAS_CNTL: { IJ_PERSP } +109cf374: 0000: 00002003 00000001 +t0 write RB_RENDER_CONTROL2 (20a3) + RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } +109cf37c: 0000: 000020a3 00001000 +t0 write RB_FS_OUTPUT_REG (2100) + RB_FS_OUTPUT_REG: { MRT = 1 } +109cf384: 0000: 00002100 00000001 +t0 write SP_FS_OUTPUT_REG (22f0) + SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +109cf38c: 0000: 000022f0 0000fc01 +t0 write SP_FS_MRT[0].REG (22f1) + SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } + SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } +109cf394: 0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002 +109cf3b4: 0020: 00000002 +t0 write VPC_ATTR (2140) + VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +109cf3b8: 0000: 00012140 42001004 00040400 +t0 write VPC_VARYING_INTERP[0].MODE (2142) + VPC_VARYING_INTERP[0].MODE: 0 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +109cf3c4: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_VARYING_PS_REPL[0].MODE (214a) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +109cf3e8: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x + :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w + :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x + :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y + :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x + :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y + :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x + :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y + :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y + :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x + :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x + :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x + :0:0012:0012[00000000x_00000000x] nop + :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x + :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z + :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y + :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x + :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y + :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x + :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w + :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x + :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w + :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z + :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x + :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x + :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x + :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z + :0:0027:0027[00000200x_00000000x] (rpt2)nop + :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w + :0:0029:0031[00000000x_00000000x] nop + :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x + :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x + :0:0032:0034[00000200x_00000000x] (rpt2)nop + :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y + :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x + :0:0035:0039[00000200x_00000000x] (rpt2)nop + :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x + :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x + :0:0038:0044[00000200x_00000000x] (rpt2)nop + :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x + :0:0040:0048[00000200x_00000000x] (rpt2)nop + :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x + :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x + :0:0043:0053[00000100x_00000000x] (rpt1)nop + :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x + :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y + :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z + :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w + :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y + :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z + :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x + :0:0051:0062[03000000x_00000000x] end + :0:0052:0063[00000000x_00000000x] nop + :0:0053:0064[00000000x_00000000x] nop + :0:0054:0065[00000000x_00000000x] nop + :0:0055:0066[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-8 10-17 (cnt=17, max=17) + - used (merged): 0-17 20-35 (cnt=34, max=35) + - input (half): (cnt=0, max=0) + - input (full): 2-8 (cnt=7, max=8) + - const (half): (cnt=0, max=0) + - const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 10-17 (cnt=8, max=17) (estimated) + - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full + - shaderdb: 1 (ss), 0 (sy) +109cf40c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 +109cf42c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c +109cf44c: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 +109cf46c: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 +109cf48c: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a +109cf4ac: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d +109cf4cc: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 +109cf4ec: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 +109cf50c: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 +109cf52c: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 +109cf54c: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 +109cf56c: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 +109cf58c: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 +109cf5ac: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x + :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x + :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x + :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x + :0:0004:0004[03000000x_00000000x] end + :0:0005:0005[00000000x_00000000x] nop + :0:0006:0006[00000000x_00000000x] nop + :0:0007:0007[00000000x_00000000x] nop + :0:0008:0008[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0 2-5 (cnt=5, max=5) + - used (merged): 0-1 4-11 (cnt=10, max=11) + - input (half): (cnt=0, max=0) + - input (full): 0 (cnt=1, max=0) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 2-5 (cnt=4, max=5) (estimated) + - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 0 half, 2 full + - shaderdb: 0 (ss), 0 (sy) +109cf618: 0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002 +109cf638: 0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000 +* +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109cf6a4: 0000: c0002600 00000000 +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109cf6b8: 4.330127 0.855050 0.555273 0.469846 0.000000 4.698463 -0.404206 -0.342020 +109cf6d8: 2.500000 -1.480991 -0.961761 -0.813798 -12.990380 -11.962078 35.506226 39.274502 +109cf6f8: 0.160000 0.020000 0.000000 1.000000 0.039740 0.662886 0.747665 0.000000 +109cf718: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 +109cf738: 0.800000 0.100000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 +109cf758: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 +109cf6b8: 0000: 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 409659cf becef409 beaf1d43 +109cf6d8: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 c13f64ac 420e0660 421d1917 +109cf6f8: 0040: 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e 3f29b2e7 3f3f66f5 00000000 +109cf718: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 +109cf738: 0080: 3f4ccccd 3dcccccd 00000000 3f800000 00000000 00000000 00000000 3f800000 +109cf758: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 +109cf6ac: 0000: c0313000 03200000 00000001 408a9066 3f5ae494 3f0e265d 3ef08fb2 00000000 +109cf6cc: 0020: 409659cf becef409 beaf1d43 40200000 bfbd9119 bf7635f5 bf50550b c14fd899 +109cf6ec: 0040: c13f64ac 420e0660 421d1917 3e23d70b 3ca3d70b 00000000 3f800000 3d22c66e +109cf70c: 0060: 3f29b2e7 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 +109cf72c: 0080: 00000000 00000000 3f800000 3f4ccccd 3dcccccd 00000000 3f800000 00000000 +109cf74c: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 +109cf76c: 00c0: 02020202 02020202 00000202 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109cf778: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109cf784: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x26 + :0,37,115,38 +109cf78c: 0000: 0000057f 00000026 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 120 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd0960 } + { INDX_SIZE = 240 } + draw[6] register values +!+ 00000025 CP_SCRATCH[0x5].REG: 0x25 + :0,37,115,38 +!+ 00000026 CP_SCRATCH[0x7].REG: 0x26 + :0,37,115,38 + + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } +!+ 00000001 GRAS_CNTL: { IJ_PERSP } + + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + + 00000010 GRAS_SU_POINT_SIZE: 1.000000 + + 00000000 GRAS_ALPHA_CONTROL: { 0 } + + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } + + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } + + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } + + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 + + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff + + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +!+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 + + 00140010 SP_SP_CTRL_REG: { 0x140010 } + + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } + + 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + + 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } + + 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } + + 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } + + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + + 10cd5000 SP_VS_OBJ_START: 0x10cd5000 + + 00000004 SP_VS_LENGTH_REG: 4 +!+ 00340802 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } + + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +!+ 108cb000 SP_FS_OBJ_START: 0x108cb000 + + 00000001 SP_FS_LENGTH_REG: 1 + + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +!+ 0001a002 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } +!+ 00000002 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } + + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } +!+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 00000003 HLSQ_UPDATE_CONTROL: 0x3 +109cf794: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0960 000000f0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x27 + :0,37,115,39 +109cf7b0: 0000: 0000057f 00000027 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x2b + :0,43,115,39 +109cf7b8: 0000: 0000057d 0000002b +t0 write RB_DEPTH_CONTROL (2101) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } +109cf7c0: 0000: 00002101 80000016 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0 } +109cf7c8: 0000: 00002073 00000000 +t0 write GRAS_SU_MODE_CONTROL (2078) + GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } +109cf7d0: 0000: 00002078 00100012 +t0 write GRAS_SU_POINT_MINMAX (2070) + GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + GRAS_SU_POINT_SIZE: 1.000000 +109cf7d8: 0000: 00012070 00100010 00000010 +t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) + GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 +109cf7e4: 0000: 00022074 00000000 00000000 00000000 +t0 write GRAS_CL_CLIP_CNTL (2000) + GRAS_CL_CLIP_CNTL: { 0x80000 } +109cf7f4: 0000: 00002000 00080000 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109cf7fc: 0000: 000121c4 02000001 00000012 +t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) + GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +109cf808: 0000: 0001209c 012b012b 00000000 +t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) + RB_VPORT_Z_CLAMP[0].MIN: 0 + RB_VPORT_Z_CLAMP[0].MAX: 0xffffff +109cf814: 0000: 00012120 00000000 00ffffff +t0 write HLSQ_UPDATE_CONTROL (23db) + HLSQ_UPDATE_CONTROL: 0x3 +109cf820: 0000: 000023db 00000003 +t0 write HLSQ_CONTROL_0_REG (23c0) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +109cf828: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc +t0 write HLSQ_VS_CONTROL_REG (23c5) + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +109cf840: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { 0x140010 } +109cf858: 0000: 000022c0 00140010 +t0 write SP_INSTR_CACHE_CTRL (22c1) + SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +109cf860: 0000: 000022c1 000005ff +t0 write SP_VS_LENGTH_REG (22e5) + SP_VS_LENGTH_REG: 4 +109cf868: 0000: 000022e5 00000004 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } + SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +109cf870: 0000: 000222c4 00201000 04000042 0010fc06 +t0 write SP_VS_OUT[0].REG (22c7) + SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +109cf880: 0000: 000022c7 00001e0a +t0 write SP_VS_VPC_DST[0].REG (22d8) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } +109cf888: 0000: 000022d8 08080808 +t0 write SP_VS_OBJ_OFFSET_REG (22e0) + SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + SP_VS_OBJ_START: 0x10cd0000 +109cf890: 0000: 000122e0 00000000 10cd0000 +t0 write SP_FS_LENGTH_REG (22ef) + SP_FS_LENGTH_REG: 1 +109cf89c: 0000: 000022ef 00000001 +t0 write SP_FS_CTRL_REG0 (22e8) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } +109cf8a4: 0000: 000122e8 00340402 8010003e +t0 write SP_FS_OBJ_OFFSET_REG (22ea) + SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + SP_FS_OBJ_START: 0x10cd2000 +109cf8b0: 0000: 000122ea 7e420000 10cd2000 +t0 write SP_HS_OBJ_OFFSET_REG (230d) + SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109cf8bc: 0000: 0000230d 7e420000 +t0 write SP_DS_OBJ_OFFSET_REG (2334) + SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109cf8c4: 0000: 00002334 7e420000 +t0 write SP_GS_OBJ_OFFSET_REG (235b) + SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109cf8cc: 0000: 0000235b 7e420000 +t0 write GRAS_CNTL (2003) + GRAS_CNTL: { 0 } +109cf8d4: 0000: 00002003 00000000 +t0 write RB_RENDER_CONTROL2 (20a3) + RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } +109cf8dc: 0000: 000020a3 00000000 +t0 write RB_FS_OUTPUT_REG (2100) + RB_FS_OUTPUT_REG: { MRT = 1 } +109cf8e4: 0000: 00002100 00000001 +t0 write SP_FS_OUTPUT_REG (22f0) + SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +109cf8ec: 0000: 000022f0 0000fc01 +t0 write SP_FS_MRT[0].REG (22f1) + SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } +109cf8f4: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_ATTR (2140) + VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +109cf918: 0000: 00012140 42001004 00040400 +t0 write VPC_VARYING_INTERP[0].MODE (2142) + VPC_VARYING_INTERP[0].MODE: 0x55 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +109cf924: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_VARYING_PS_REPL[0].MODE (214a) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +109cf948: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x + :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w + :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x + :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y + :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x + :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y + :3:0006:0006[63828006x_0000100cx] mad.f32 r1.z, c3.x, r1.y, r0.x + :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y + :3:0008:0008[63828009x_0001100fx] mad.f32 r2.y, c3.w, r1.y, r0.y + :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x + :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x + :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x + :0:0012:0012[00000000x_00000000x] nop + :3:0013:0013[63828007x_0000100dx] mad.f32 r1.w, c3.y, r1.y, r0.x + :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z + :1:0015:0015[20244002x_00000015x] mov.f32f32 r0.z, c5.y + :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x + :1:0017:0017[20244003x_00000016x] mov.f32f32 r0.w, c5.z + :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x + :1:0019:0019[20244004x_00000017x] mov.f32f32 r1.x, c5.w + :3:0020:0020[63828008x_0000100ex] mad.f32 r2.x, c3.z, r1.y, r0.x + :1:0021:0021[20244000x_00000011x] mov.f32f32 r0.x, c4.y + :2:0022:0022[40100002x_00021021x] add.f r0.z, c8.y, r0.z + :2:0023:0023[4050040dx_00041017x] (sat)max.f r3.y, c5.w, r1.x + :2:0024:0024[40100003x_00031022x] add.f r0.w, c8.z, r0.w + :2:0025:0025[40700000x_00001011x] mul.f r0.x, c4.y, r0.x + :0:0026:0026[00000000x_00000000x] nop + :3:0027:0027[63808000x_00001010x] mad.f32 r0.x, c4.x, r0.y, r0.x + :1:0028:0028[20244001x_00000012x] mov.f32f32 r0.y, c4.z + :0:0029:0029[00000200x_00000000x] (rpt2)nop + :3:0030:0032[63808000x_00001012x] mad.f32 r0.x, c4.z, r0.y, r0.x + :1:0031:0033[20244001x_00000014x] mov.f32f32 r0.y, c5.x + :0:0032:0034[00000200x_00000000x] (rpt2)nop + :2:0033:0037[40100001x_00011020x] add.f r0.y, c8.x, r0.y + :0:0034:0038[00000000x_00000000x] nop + :4:0035:0039[80300000x_00000000x] rsq r0.x, r0.x + :2:0036:0040[40701004x_00001011x] (ss)mul.f r1.x, c4.y, r0.x + :0:0037:0041[00000200x_00000000x] (rpt2)nop + :2:0038:0044[40700004x_10190004x] mul.f r1.x, r1.x, c6.y + :2:0039:0045[40700005x_00001010x] mul.f r1.y, c4.x, r0.x + :0:0040:0046[00000200x_00000000x] (rpt2)nop + :3:0041:0049[63828004x_00041018x] mad.f32 r1.x, c6.x, r1.y, r1.x + :2:0042:0050[40700000x_00001012x] mul.f r0.x, c4.z, r0.x + :0:0043:0051[00000200x_00000000x] (rpt2)nop + :3:0044:0054[63800000x_0004101ax] mad.f32 r0.x, c6.z, r0.x, r1.x + :0:0045:0055[00000200x_00000000x] (rpt2)nop + :2:0046:0058[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x + :2:0047:0059[40500000x_00001034x] max.f r0.x, c13.x, r0.x + :0:0048:0060[00000100x_00000000x] (rpt1)nop + :1:0049:0062[200c4004x_00000004x] cov.u32f32 r1.x, r1.x + :3:0050:0063[63800001x_00011024x] mad.f32 r0.y, c9.x, r0.x, r0.y + :3:0051:0064[63800002x_00021025x] mad.f32 r0.z, c9.y, r0.x, r0.z + :3:0052:0065[63800000x_00031026x] mad.f32 r0.x, c9.z, r0.x, r0.w + :3:0053:0066[6382040ax_00011028x] (sat)mad.f32 r2.z, c10.x, r1.x, r0.y + :3:0054:0067[6382040bx_00021029x] (sat)mad.f32 r2.w, c10.y, r1.x, r0.z + :3:0055:0068[6382040cx_0000102ax] (sat)mad.f32 r3.x, c10.z, r1.x, r0.x + :0:0056:0069[03000000x_00000000x] end + :0:0057:0070[00000000x_00000000x] nop + :0:0058:0071[00000000x_00000000x] nop + :0:0059:0072[00000000x_00000000x] nop + :0:0060:0073[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-13 (cnt=14, max=13) + - used (merged): 0-27 (cnt=28, max=27) + - input (half): (cnt=0, max=0) + - input (full): 2-5 (cnt=4, max=5) + - const (half): (cnt=0, max=0) + - const (full): 0-18 20-26 32-34 36-38 40-42 52 (cnt=36, max=52) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 6-13 (cnt=8, max=13) (estimated) + - shaderdb: 74 instructions, 38 nops, 36 non-nops, (61 instlen), 0 half, 4 full + - shaderdb: 1 (ss), 0 (sy) +109cf96c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 +109cf98c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c +109cf9ac: 0040: 63828006 10010002 40700000 0001100f 63828009 00001005 63818000 00000010 +109cf9cc: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 63828007 10020002 +109cf9ec: 0080: 40700000 00000015 20244002 00001006 63818000 00000016 20244003 0000100a +109cfa0c: 00a0: 63820000 00000017 20244004 0000100e 63828008 00000011 20244000 00021021 +109cfa2c: 00c0: 40100002 00041017 4050040d 00031022 40100003 00001011 40700000 00000000 +109cfa4c: 00e0: 00000000 00001010 63808000 00000012 20244001 00000000 00000200 00001012 +109cfa6c: 0100: 63808000 00000014 20244001 00000000 00000200 00011020 40100001 00000000 +109cfa8c: 0120: 00000000 00000000 80300000 00001011 40701004 00000000 00000200 10190004 +109cfaac: 0140: 40700004 00001010 40700005 00000000 00000200 00041018 63828004 00001012 +109cfacc: 0160: 40700000 00000000 00000200 0004101a 63800000 00000000 00000200 00001034 +109cfaec: 0180: 40b00004 00001034 40500000 00000000 00000100 00000004 200c4004 00011024 +109cfb0c: 01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029 +109cfb2c: 01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :0:0000:0000[00000000x_00000000x] nop + :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 + :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 + :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 + :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 + :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x + :0:0006:0006[03000000x_00000000x] end + :0:0007:0007[00000000x_00000000x] nop + :0:0008:0008[00000000x_00000000x] nop + :0:0009:0009[00000000x_00000000x] nop + :0:0010:0010[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-3 252 (cnt=5, max=3) + - used (merged): 0-7 504-505 (cnt=10, max=7) + - input (half): (cnt=0, max=0) + - input (full): 0-3 (cnt=4, max=3) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 252 (cnt=1, max=0) (estimated) + - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full + - shaderdb: 1 (ss), 0 (sy) +109cfb78: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 +109cfb98: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 +109cfbb8: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109cfc04: 0000: c0002600 00000000 +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109cfc18: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309 +109cfc38: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564 +109cfc58: 0.000000 0.000000 1.000000 1.000000 0.000000 0.160000 0.040000 1.000000 +109cfc78: -0.064448 0.660942 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 +109cfc98: 0.000000 0.000000 0.000000 1.000000 0.000000 0.800000 0.200000 1.000000 +109cfcb8: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 +109cfc18: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387 +109cfc38: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0 +109cfc58: 0040: 00000000 00000000 3f800000 3f800000 00000000 3e23d70b 3d23d70b 3f800000 +109cfc78: 0060: bd83fd0e 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 +109cfc98: 0080: 00000000 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 +109cfcb8: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 +109cfc0c: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da +109cfc2c: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 +109cfc4c: 0040: c0d7e173 421b92d5 42288ff0 00000000 00000000 3f800000 3f800000 00000000 +109cfc6c: 0060: 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000 3f800000 +109cfc8c: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 00000000 +109cfcac: 00a0: 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 00000000 +109cfccc: 00c0: 00000000 00000000 3f800000 +t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) + { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109cfce4: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 +109cfce4: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +109cfcd8: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +t0 write VFD_FETCH[0].INSTR_0 (220a) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } + VFD_FETCH[0].INSTR_1: 0x107cb000 + VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +109cfcf4: 0000: 0003220a 0000060b 107cb000 00100000 00000001 +t0 write VFD_DECODE[0].INSTR (228a) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +109cfd08: 0000: 0000228a 2c0020df +t0 write VFD_CONTROL_0 (2200) + VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } + VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + VFD_CONTROL_2: 0 + VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + VFD_CONTROL_4: 0 +109cfd10: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000 +t0 write UCHE_INVALIDATE0 (0e8a) + UCHE_INVALIDATE0: 0 + UCHE_INVALIDATE1: 0x12 +109cfd28: 0000: 00010e8a 00000000 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109cfd34: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109cfd40: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x2c + :0,43,115,44 +109cfd48: 0000: 0000057f 0000002c +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 120 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd0a50 } + { INDX_SIZE = 240 } + draw[7] register values +!+ 0000002b CP_SCRATCH[0x5].REG: 0x2b + :0,43,115,44 +!+ 0000002c CP_SCRATCH[0x7].REG: 0x2c + :0,43,115,44 + + 00000000 UCHE_INVALIDATE0: 0 + + 00000012 UCHE_INVALIDATE1: 0x12 + + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } +!+ 00000000 GRAS_CNTL: { 0 } + + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + + 00000010 GRAS_SU_POINT_SIZE: 1.000000 + + 00000000 GRAS_ALPHA_CONTROL: { 0 } + + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } + + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } + + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } + + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 + + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff + + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +!+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } + + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + + 00000000 VFD_CONTROL_2: 0 + + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + + 00000000 VFD_CONTROL_4: 0 + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +!+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } + + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 + + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +!+ 2c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } + + 00140010 SP_SP_CTRL_REG: { 0x140010 } + + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +!+ 00201000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } +!+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } +!+ 0010fc06 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +!+ 00001e0a SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } + + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } +!+ 10cd0000 SP_VS_OBJ_START: 0x10cd0000 + + 00000004 SP_VS_LENGTH_REG: 4 +!+ 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } + + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +!+ 10cd2000 SP_FS_OBJ_START: 0x10cd2000 + + 00000001 SP_FS_LENGTH_REG: 1 + + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +!+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } +!+ 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } +!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 00000003 HLSQ_UPDATE_CONTROL: 0x3 +109cfd50: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0a50 000000f0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x2d + :0,43,115,45 +109cfd6c: 0000: 0000057f 0000002d +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x31 + :0,49,115,45 +109cfd74: 0000: 0000057d 00000031 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109cfd7c: 0000: 000121c4 02000001 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109cfd88: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109cfd94: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x32 + :0,49,115,50 +109cfd9c: 0000: 0000057f 00000032 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 60 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd0b40 } + { INDX_SIZE = 120 } + draw[8] register values +!+ 00000031 CP_SCRATCH[0x5].REG: 0x31 + :0,49,115,50 +!+ 00000032 CP_SCRATCH[0x7].REG: 0x32 + :0,49,115,50 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +109cfda4: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd0b40 00000078 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x33 + :0,49,115,51 +109cfdc0: 0000: 0000057f 00000033 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x37 + :0,55,115,51 +109cfdc8: 0000: 0000057d 00000037 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109cfdd0: 0000: 000121c4 02000001 00000012 +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109cfddc: 0000: c0002600 00000000 +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109cfdf0: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309 +109cfe10: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564 +109cfe30: 0.000000 0.000000 -1.000000 1.000000 0.000000 0.160000 0.040000 1.000000 +109cfe50: -0.064448 0.660942 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 +109cfe70: 0.000000 0.000000 0.000000 1.000000 0.000000 0.800000 0.200000 1.000000 +109cfe90: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 +109cfdf0: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387 +109cfe10: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0 +109cfe30: 0040: 00000000 00000000 bf800000 3f800000 00000000 3e23d70b 3d23d70b 3f800000 +109cfe50: 0060: bd83fd0e 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 +109cfe70: 0080: 00000000 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 +109cfe90: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 +109cfde4: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da +109cfe04: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 +109cfe24: 0040: c0d7e173 421b92d5 42288ff0 00000000 00000000 bf800000 3f800000 00000000 +109cfe44: 0060: 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000 3f800000 +109cfe64: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 00000000 +109cfe84: 00a0: 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 00000000 +109cfea4: 00c0: 00000000 00000000 3f800000 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109cfeb0: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109cfebc: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x38 + :0,55,115,56 +109cfec4: 0000: 0000057f 00000038 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 120 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd0bb8 } + { INDX_SIZE = 240 } + draw[9] register values +!+ 00000037 CP_SCRATCH[0x5].REG: 0x37 + :0,55,115,56 +!+ 00000038 CP_SCRATCH[0x7].REG: 0x38 + :0,55,115,56 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +109cfecc: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0bb8 000000f0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x39 + :0,55,115,57 +109cfee8: 0000: 0000057f 00000039 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x3d + :0,61,115,57 +109cfef0: 0000: 0000057d 0000003d +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109cfef8: 0000: 000121c4 02000001 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109cff04: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109cff10: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x3e + :0,61,115,62 +109cff18: 0000: 0000057f 0000003e +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 60 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd0ca8 } + { INDX_SIZE = 120 } + draw[10] register values +!+ 0000003d CP_SCRATCH[0x5].REG: 0x3d + :0,61,115,62 +!+ 0000003e CP_SCRATCH[0x7].REG: 0x3e + :0,61,115,62 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +109cff20: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd0ca8 00000078 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x3f + :0,61,115,63 +109cff3c: 0000: 0000057f 0000003f +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x43 + :0,67,115,63 +109cff44: 0000: 0000057d 00000043 +t0 write RB_DEPTH_CONTROL (2101) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } +109cff4c: 0000: 00002101 80000016 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0 } +109cff54: 0000: 00002073 00000000 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109cff5c: 0000: 000121c4 02000001 00000012 +t0 write HLSQ_UPDATE_CONTROL (23db) + HLSQ_UPDATE_CONTROL: 0x3 +109cff68: 0000: 000023db 00000003 +t0 write HLSQ_CONTROL_0_REG (23c0) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +109cff70: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc +t0 write HLSQ_VS_CONTROL_REG (23c5) + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +109cff88: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { 0x140010 } +109cffa0: 0000: 000022c0 00140010 +t0 write SP_INSTR_CACHE_CTRL (22c1) + SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +109cffa8: 0000: 000022c1 000005ff +t0 write SP_VS_LENGTH_REG (22e5) + SP_VS_LENGTH_REG: 4 +109cffb0: 0000: 000022e5 00000004 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } + SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +109cffb8: 0000: 000222c4 00201400 08000042 0010fc0a +t0 write SP_VS_OUT[0].REG (22c7) + SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +109cffc8: 0000: 000022c7 00001e0e +t0 write SP_VS_VPC_DST[0].REG (22d8) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } +109cffd0: 0000: 000022d8 08080808 +t0 write SP_VS_OBJ_OFFSET_REG (22e0) + SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + SP_VS_OBJ_START: 0x10cd5000 +109cffd8: 0000: 000122e0 00000000 10cd5000 +t0 write SP_FS_LENGTH_REG (22ef) + SP_FS_LENGTH_REG: 1 +109cffe4: 0000: 000022ef 00000001 +t0 write SP_FS_CTRL_REG0 (22e8) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } +109cffec: 0000: 000122e8 00340402 8010003e +t0 write SP_FS_OBJ_OFFSET_REG (22ea) + SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + SP_FS_OBJ_START: 0x10cd2000 +109cfff8: 0000: 000122ea 7e420000 10cd2000 +t0 write SP_HS_OBJ_OFFSET_REG (230d) + SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d0004: 0000: 0000230d 7e420000 +t0 write SP_DS_OBJ_OFFSET_REG (2334) + SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d000c: 0000: 00002334 7e420000 +t0 write SP_GS_OBJ_OFFSET_REG (235b) + SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d0014: 0000: 0000235b 7e420000 +t0 write GRAS_CNTL (2003) + GRAS_CNTL: { 0 } +109d001c: 0000: 00002003 00000000 +t0 write RB_RENDER_CONTROL2 (20a3) + RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } +109d0024: 0000: 000020a3 00000000 +t0 write RB_FS_OUTPUT_REG (2100) + RB_FS_OUTPUT_REG: { MRT = 1 } +109d002c: 0000: 00002100 00000001 +t0 write SP_FS_OUTPUT_REG (22f0) + SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +109d0034: 0000: 000022f0 0000fc01 +t0 write SP_FS_MRT[0].REG (22f1) + SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } +109d003c: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_ATTR (2140) + VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +109d0060: 0000: 00012140 42001004 00040400 +t0 write VPC_VARYING_INTERP[0].MODE (2142) + VPC_VARYING_INTERP[0].MODE: 0x55 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +109d006c: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_VARYING_PS_REPL[0].MODE (214a) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +109d0090: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x + :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w + :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x + :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y + :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x + :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y + :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x + :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y + :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y + :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x + :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x + :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x + :0:0012:0012[00000000x_00000000x] nop + :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x + :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z + :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y + :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x + :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y + :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x + :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w + :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x + :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w + :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z + :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x + :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x + :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x + :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z + :0:0027:0027[00000200x_00000000x] (rpt2)nop + :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w + :0:0029:0031[00000000x_00000000x] nop + :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x + :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x + :0:0032:0034[00000200x_00000000x] (rpt2)nop + :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y + :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x + :0:0035:0039[00000200x_00000000x] (rpt2)nop + :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x + :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x + :0:0038:0044[00000200x_00000000x] (rpt2)nop + :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x + :0:0040:0048[00000200x_00000000x] (rpt2)nop + :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x + :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x + :0:0043:0053[00000100x_00000000x] (rpt1)nop + :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x + :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y + :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z + :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w + :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y + :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z + :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x + :0:0051:0062[03000000x_00000000x] end + :0:0052:0063[00000000x_00000000x] nop + :0:0053:0064[00000000x_00000000x] nop + :0:0054:0065[00000000x_00000000x] nop + :0:0055:0066[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-8 10-17 (cnt=17, max=17) + - used (merged): 0-17 20-35 (cnt=34, max=35) + - input (half): (cnt=0, max=0) + - input (full): 2-8 (cnt=7, max=8) + - const (half): (cnt=0, max=0) + - const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 10-17 (cnt=8, max=17) (estimated) + - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full + - shaderdb: 1 (ss), 0 (sy) +109d00b4: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 +109d00d4: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c +109d00f4: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 +109d0114: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 +109d0134: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a +109d0154: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d +109d0174: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 +109d0194: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 +109d01b4: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 +109d01d4: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 +109d01f4: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 +109d0214: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 +109d0234: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 +109d0254: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :0:0000:0000[00000000x_00000000x] nop + :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 + :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 + :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 + :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 + :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x + :0:0006:0006[03000000x_00000000x] end + :0:0007:0007[00000000x_00000000x] nop + :0:0008:0008[00000000x_00000000x] nop + :0:0009:0009[00000000x_00000000x] nop + :0:0010:0010[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-3 252 (cnt=5, max=3) + - used (merged): 0-7 504-505 (cnt=10, max=7) + - input (half): (cnt=0, max=0) + - input (full): 0-3 (cnt=4, max=3) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 252 (cnt=1, max=0) (estimated) + - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full + - shaderdb: 1 (ss), 0 (sy) +109d02c0: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 +109d02e0: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 +109d0300: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109d034c: 0000: c0002600 00000000 +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109d0360: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309 +109d0380: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564 +109d03a0: 0.000000 0.160000 0.040000 1.000000 -0.064448 0.660942 0.747665 0.000000 +109d03c0: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 +109d03e0: 0.000000 0.800000 0.200000 1.000000 0.000000 0.000000 0.000000 1.000000 +109d0400: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 +109d0360: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387 +109d0380: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0 +109d03a0: 0040: 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000 +109d03c0: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 +109d03e0: 0080: 00000000 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 +109d0400: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 +109d0354: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da +109d0374: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 +109d0394: 0040: c0d7e173 421b92d5 42288ff0 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e +109d03b4: 0060: 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 +109d03d4: 0080: 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 00000000 +109d03f4: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 +109d0414: 00c0: 02020202 02020202 00000202 +t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) + { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109d042c: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 +109d042c: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +109d0420: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +t0 write VFD_FETCH[0].INSTR_0 (220a) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } + VFD_FETCH[0].INSTR_1: 0x107cb000 + VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +109d043c: 0000: 0003220a 00080c0b 107cb000 00100000 00000001 +t0 write VFD_DECODE[0].INSTR (228a) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } +109d0450: 0000: 0000228a 6c0020df +t0 write VFD_FETCH[0x1].INSTR_0 (220e) + VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } + VFD_FETCH[0x1].INSTR_1: 0x107cb00c + VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } + VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } +109d0458: 0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001 +t0 write VFD_DECODE[0x1].INSTR (228b) + VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +109d046c: 0000: 0000228b 2c0060df +t0 write VFD_CONTROL_0 (2200) + VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + VFD_CONTROL_2: 0 + VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + VFD_CONTROL_4: 0 +109d0474: 0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000 +t0 write UCHE_INVALIDATE0 (0e8a) + UCHE_INVALIDATE0: 0 + UCHE_INVALIDATE1: 0x12 +109d048c: 0000: 00010e8a 00000000 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109d0498: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109d04a4: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x44 + :0,67,115,68 +109d04ac: 0000: 0000057f 00000044 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 240 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd0d20 } + { INDX_SIZE = 480 } + draw[11] register values +!+ 00000043 CP_SCRATCH[0x5].REG: 0x43 + :0,67,115,68 +!+ 00000044 CP_SCRATCH[0x7].REG: 0x44 + :0,67,115,68 + + 00000000 UCHE_INVALIDATE0: 0 + + 00000012 UCHE_INVALIDATE1: 0x12 + + 00000000 GRAS_CNTL: { 0 } + + 00000000 GRAS_ALPHA_CONTROL: { 0 } + + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } + + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } + + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + + 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + + 00000000 VFD_CONTROL_2: 0 + + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + + 00000000 VFD_CONTROL_4: 0 + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +!+ 00080c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } + + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 + + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + + 00000c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } + + 107cb00c VFD_FETCH[0x1].INSTR_1: 0x107cb00c + + 000ffff4 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } + + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } +!+ 6c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } + + 2c0060df VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } + + 00140010 SP_SP_CTRL_REG: { 0x140010 } + + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +!+ 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } +!+ 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } +!+ 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +!+ 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } + + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } +!+ 10cd5000 SP_VS_OBJ_START: 0x10cd5000 + + 00000004 SP_VS_LENGTH_REG: 4 + + 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } + + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 10cd2000 SP_FS_OBJ_START: 0x10cd2000 + + 00000001 SP_FS_LENGTH_REG: 1 + + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } + + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 00000003 HLSQ_UPDATE_CONTROL: 0x3 +109d04b4: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd0d20 000001e0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x45 + :0,67,115,69 +109d04d0: 0000: 0000057f 00000045 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x49 + :0,73,115,69 +109d04d8: 0000: 0000057d 00000049 +t0 write RB_DEPTH_CONTROL (2101) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } +109d04e0: 0000: 00002101 80000016 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0 } +109d04e8: 0000: 00002073 00000000 +t0 write GRAS_SU_MODE_CONTROL (2078) + GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } +109d04f0: 0000: 00002078 00100012 +t0 write GRAS_SU_POINT_MINMAX (2070) + GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + GRAS_SU_POINT_SIZE: 1.000000 +109d04f8: 0000: 00012070 00100010 00000010 +t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) + GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 +109d0504: 0000: 00022074 00000000 00000000 00000000 +t0 write GRAS_CL_CLIP_CNTL (2000) + GRAS_CL_CLIP_CNTL: { 0x80000 } +109d0514: 0000: 00002000 00080000 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109d051c: 0000: 000121c4 02000001 00000012 +t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) + GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +109d0528: 0000: 0001209c 012b012b 00000000 +t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) + RB_VPORT_Z_CLAMP[0].MIN: 0 + RB_VPORT_Z_CLAMP[0].MAX: 0xffffff +109d0534: 0000: 00012120 00000000 00ffffff +t0 write HLSQ_UPDATE_CONTROL (23db) + HLSQ_UPDATE_CONTROL: 0x3 +109d0540: 0000: 000023db 00000003 +t0 write HLSQ_CONTROL_0_REG (23c0) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +109d0548: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc +t0 write HLSQ_VS_CONTROL_REG (23c5) + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +109d0560: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { 0x140010 } +109d0578: 0000: 000022c0 00140010 +t0 write SP_INSTR_CACHE_CTRL (22c1) + SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +109d0580: 0000: 000022c1 000005ff +t0 write SP_VS_LENGTH_REG (22e5) + SP_VS_LENGTH_REG: 4 +109d0588: 0000: 000022e5 00000004 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } + SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +109d0590: 0000: 000222c4 00201400 08000042 0010fc0a +t0 write SP_VS_OUT[0].REG (22c7) + SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +109d05a0: 0000: 000022c7 00001e0e +t0 write SP_VS_VPC_DST[0].REG (22d8) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } +109d05a8: 0000: 000022d8 08080808 +t0 write SP_VS_OBJ_OFFSET_REG (22e0) + SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + SP_VS_OBJ_START: 0x10cd5000 +109d05b0: 0000: 000122e0 00000000 10cd5000 +t0 write SP_FS_LENGTH_REG (22ef) + SP_FS_LENGTH_REG: 1 +109d05bc: 0000: 000022ef 00000001 +t0 write SP_FS_CTRL_REG0 (22e8) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } +109d05c4: 0000: 000122e8 00340802 8010003e +t0 write SP_FS_OBJ_OFFSET_REG (22ea) + SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + SP_FS_OBJ_START: 0x108cb000 +109d05d0: 0000: 000122ea 7e420000 108cb000 +t0 write SP_HS_OBJ_OFFSET_REG (230d) + SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d05dc: 0000: 0000230d 7e420000 +t0 write SP_DS_OBJ_OFFSET_REG (2334) + SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d05e4: 0000: 00002334 7e420000 +t0 write SP_GS_OBJ_OFFSET_REG (235b) + SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d05ec: 0000: 0000235b 7e420000 +t0 write GRAS_CNTL (2003) + GRAS_CNTL: { IJ_PERSP } +109d05f4: 0000: 00002003 00000001 +t0 write RB_RENDER_CONTROL2 (20a3) + RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } +109d05fc: 0000: 000020a3 00001000 +t0 write RB_FS_OUTPUT_REG (2100) + RB_FS_OUTPUT_REG: { MRT = 1 } +109d0604: 0000: 00002100 00000001 +t0 write SP_FS_OUTPUT_REG (22f0) + SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +109d060c: 0000: 000022f0 0000fc01 +t0 write SP_FS_MRT[0].REG (22f1) + SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } + SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } +109d0614: 0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002 +109d0634: 0020: 00000002 +t0 write VPC_ATTR (2140) + VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +109d0638: 0000: 00012140 42001004 00040400 +t0 write VPC_VARYING_INTERP[0].MODE (2142) + VPC_VARYING_INTERP[0].MODE: 0 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +109d0644: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_VARYING_PS_REPL[0].MODE (214a) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +109d0668: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x + :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w + :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x + :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y + :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x + :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y + :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x + :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y + :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y + :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x + :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x + :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x + :0:0012:0012[00000000x_00000000x] nop + :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x + :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z + :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y + :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x + :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y + :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x + :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w + :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x + :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w + :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z + :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x + :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x + :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x + :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z + :0:0027:0027[00000200x_00000000x] (rpt2)nop + :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w + :0:0029:0031[00000000x_00000000x] nop + :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x + :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x + :0:0032:0034[00000200x_00000000x] (rpt2)nop + :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y + :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x + :0:0035:0039[00000200x_00000000x] (rpt2)nop + :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x + :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x + :0:0038:0044[00000200x_00000000x] (rpt2)nop + :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x + :0:0040:0048[00000200x_00000000x] (rpt2)nop + :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x + :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x + :0:0043:0053[00000100x_00000000x] (rpt1)nop + :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x + :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y + :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z + :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w + :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y + :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z + :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x + :0:0051:0062[03000000x_00000000x] end + :0:0052:0063[00000000x_00000000x] nop + :0:0053:0064[00000000x_00000000x] nop + :0:0054:0065[00000000x_00000000x] nop + :0:0055:0066[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-8 10-17 (cnt=17, max=17) + - used (merged): 0-17 20-35 (cnt=34, max=35) + - input (half): (cnt=0, max=0) + - input (full): 2-8 (cnt=7, max=8) + - const (half): (cnt=0, max=0) + - const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 10-17 (cnt=8, max=17) (estimated) + - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full + - shaderdb: 1 (ss), 0 (sy) +109d068c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 +109d06ac: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c +109d06cc: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 +109d06ec: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 +109d070c: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a +109d072c: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d +109d074c: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 +109d076c: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 +109d078c: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 +109d07ac: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 +109d07cc: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 +109d07ec: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 +109d080c: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 +109d082c: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x + :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x + :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x + :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x + :0:0004:0004[03000000x_00000000x] end + :0:0005:0005[00000000x_00000000x] nop + :0:0006:0006[00000000x_00000000x] nop + :0:0007:0007[00000000x_00000000x] nop + :0:0008:0008[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0 2-5 (cnt=5, max=5) + - used (merged): 0-1 4-11 (cnt=10, max=11) + - input (half): (cnt=0, max=0) + - input (full): 0 (cnt=1, max=0) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 2-5 (cnt=4, max=5) (estimated) + - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 0 half, 2 full + - shaderdb: 0 (ss), 0 (sy) +109d0898: 0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002 +109d08b8: 0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000 +* +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109d0924: 0000: c0002600 00000000 +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109d0938: 4.276816 0.109522 0.611668 0.517565 0.677381 4.774377 -0.312365 -0.264309 +109d0958: 2.500000 -1.480991 -0.961761 -0.813798 13.423393 -6.746271 38.893391 42.140564 +109d0978: 0.000000 0.160000 0.040000 1.000000 -0.064448 0.660942 0.747665 0.000000 +109d0998: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 +109d09b8: 0.000000 0.800000 0.200000 1.000000 0.000000 0.000000 0.000000 1.000000 +109d09d8: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 +109d0938: 0000: 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da 4098c7b2 be9fee59 be875387 +109d0958: 0020: 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 c0d7e173 421b92d5 42288ff0 +109d0978: 0040: 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e 3f293379 3f3f66f5 00000000 +109d0998: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 +109d09b8: 0080: 00000000 3f4ccccd 3e4ccccd 3f800000 00000000 00000000 00000000 3f800000 +109d09d8: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 +109d092c: 0000: c0313000 03200000 00000001 4088dbad 3de04cdc 3f1c964b 3f047f2c 3f2d68da +109d094c: 0020: 4098c7b2 be9fee59 be875387 40200000 bfbd9119 bf7635f5 bf50550b 4156c638 +109d096c: 0040: c0d7e173 421b92d5 42288ff0 00000000 3e23d70b 3d23d70b 3f800000 bd83fd0e +109d098c: 0060: 3f293379 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 +109d09ac: 0080: 00000000 00000000 3f800000 00000000 3f4ccccd 3e4ccccd 3f800000 00000000 +109d09cc: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 +109d09ec: 00c0: 02020202 02020202 00000202 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109d09f8: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109d0a04: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x4a + :0,73,115,74 +109d0a0c: 0000: 0000057f 0000004a +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 60 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd0f00 } + { INDX_SIZE = 120 } + draw[12] register values +!+ 00000049 CP_SCRATCH[0x5].REG: 0x49 + :0,73,115,74 +!+ 0000004a CP_SCRATCH[0x7].REG: 0x4a + :0,73,115,74 + + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } +!+ 00000001 GRAS_CNTL: { IJ_PERSP } + + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + + 00000010 GRAS_SU_POINT_SIZE: 1.000000 + + 00000000 GRAS_ALPHA_CONTROL: { 0 } + + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } + + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } + + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } + + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 + + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff + + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +!+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 + + 00140010 SP_SP_CTRL_REG: { 0x140010 } + + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } + + 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + + 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } + + 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } + + 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } + + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + + 10cd5000 SP_VS_OBJ_START: 0x10cd5000 + + 00000004 SP_VS_LENGTH_REG: 4 +!+ 00340802 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } + + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +!+ 108cb000 SP_FS_OBJ_START: 0x108cb000 + + 00000001 SP_FS_LENGTH_REG: 1 + + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +!+ 0001a002 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } +!+ 00000002 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } + + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } +!+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 00000003 HLSQ_UPDATE_CONTROL: 0x3 +109d0a14: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd0f00 00000078 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x4b + :0,73,115,75 +109d0a30: 0000: 0000057f 0000004b +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x4f + :0,79,115,75 +109d0a38: 0000: 0000057d 0000004f +t0 write RB_DEPTH_CONTROL (2101) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } +109d0a40: 0000: 00002101 80000016 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0 } +109d0a48: 0000: 00002073 00000000 +t0 write GRAS_SU_MODE_CONTROL (2078) + GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } +109d0a50: 0000: 00002078 00100012 +t0 write GRAS_SU_POINT_MINMAX (2070) + GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + GRAS_SU_POINT_SIZE: 1.000000 +109d0a58: 0000: 00012070 00100010 00000010 +t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) + GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 +109d0a64: 0000: 00022074 00000000 00000000 00000000 +t0 write GRAS_CL_CLIP_CNTL (2000) + GRAS_CL_CLIP_CNTL: { 0x80000 } +109d0a74: 0000: 00002000 00080000 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109d0a7c: 0000: 000121c4 02000001 00000012 +t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) + GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +109d0a88: 0000: 0001209c 012b012b 00000000 +t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) + RB_VPORT_Z_CLAMP[0].MIN: 0 + RB_VPORT_Z_CLAMP[0].MAX: 0xffffff +109d0a94: 0000: 00012120 00000000 00ffffff +t0 write HLSQ_UPDATE_CONTROL (23db) + HLSQ_UPDATE_CONTROL: 0x3 +109d0aa0: 0000: 000023db 00000003 +t0 write HLSQ_CONTROL_0_REG (23c0) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +109d0aa8: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc +t0 write HLSQ_VS_CONTROL_REG (23c5) + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +109d0ac0: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { 0x140010 } +109d0ad8: 0000: 000022c0 00140010 +t0 write SP_INSTR_CACHE_CTRL (22c1) + SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +109d0ae0: 0000: 000022c1 000005ff +t0 write SP_VS_LENGTH_REG (22e5) + SP_VS_LENGTH_REG: 4 +109d0ae8: 0000: 000022e5 00000004 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } + SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +109d0af0: 0000: 000222c4 00201000 04000042 0010fc06 +t0 write SP_VS_OUT[0].REG (22c7) + SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +109d0b00: 0000: 000022c7 00001e0a +t0 write SP_VS_VPC_DST[0].REG (22d8) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } +109d0b08: 0000: 000022d8 08080808 +t0 write SP_VS_OBJ_OFFSET_REG (22e0) + SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + SP_VS_OBJ_START: 0x10cd0000 +109d0b10: 0000: 000122e0 00000000 10cd0000 +t0 write SP_FS_LENGTH_REG (22ef) + SP_FS_LENGTH_REG: 1 +109d0b1c: 0000: 000022ef 00000001 +t0 write SP_FS_CTRL_REG0 (22e8) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } +109d0b24: 0000: 000122e8 00340402 8010003e +t0 write SP_FS_OBJ_OFFSET_REG (22ea) + SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + SP_FS_OBJ_START: 0x10cd2000 +109d0b30: 0000: 000122ea 7e420000 10cd2000 +t0 write SP_HS_OBJ_OFFSET_REG (230d) + SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d0b3c: 0000: 0000230d 7e420000 +t0 write SP_DS_OBJ_OFFSET_REG (2334) + SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d0b44: 0000: 00002334 7e420000 +t0 write SP_GS_OBJ_OFFSET_REG (235b) + SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d0b4c: 0000: 0000235b 7e420000 +t0 write GRAS_CNTL (2003) + GRAS_CNTL: { 0 } +109d0b54: 0000: 00002003 00000000 +t0 write RB_RENDER_CONTROL2 (20a3) + RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } +109d0b5c: 0000: 000020a3 00000000 +t0 write RB_FS_OUTPUT_REG (2100) + RB_FS_OUTPUT_REG: { MRT = 1 } +109d0b64: 0000: 00002100 00000001 +t0 write SP_FS_OUTPUT_REG (22f0) + SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +109d0b6c: 0000: 000022f0 0000fc01 +t0 write SP_FS_MRT[0].REG (22f1) + SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } +109d0b74: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_ATTR (2140) + VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +109d0b98: 0000: 00012140 42001004 00040400 +t0 write VPC_VARYING_INTERP[0].MODE (2142) + VPC_VARYING_INTERP[0].MODE: 0x55 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +109d0ba4: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_VARYING_PS_REPL[0].MODE (214a) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +109d0bc8: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x + :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w + :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x + :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y + :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x + :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y + :3:0006:0006[63828006x_0000100cx] mad.f32 r1.z, c3.x, r1.y, r0.x + :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y + :3:0008:0008[63828009x_0001100fx] mad.f32 r2.y, c3.w, r1.y, r0.y + :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x + :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x + :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x + :0:0012:0012[00000000x_00000000x] nop + :3:0013:0013[63828007x_0000100dx] mad.f32 r1.w, c3.y, r1.y, r0.x + :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z + :1:0015:0015[20244002x_00000015x] mov.f32f32 r0.z, c5.y + :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x + :1:0017:0017[20244003x_00000016x] mov.f32f32 r0.w, c5.z + :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x + :1:0019:0019[20244004x_00000017x] mov.f32f32 r1.x, c5.w + :3:0020:0020[63828008x_0000100ex] mad.f32 r2.x, c3.z, r1.y, r0.x + :1:0021:0021[20244000x_00000011x] mov.f32f32 r0.x, c4.y + :2:0022:0022[40100002x_00021021x] add.f r0.z, c8.y, r0.z + :2:0023:0023[4050040dx_00041017x] (sat)max.f r3.y, c5.w, r1.x + :2:0024:0024[40100003x_00031022x] add.f r0.w, c8.z, r0.w + :2:0025:0025[40700000x_00001011x] mul.f r0.x, c4.y, r0.x + :0:0026:0026[00000000x_00000000x] nop + :3:0027:0027[63808000x_00001010x] mad.f32 r0.x, c4.x, r0.y, r0.x + :1:0028:0028[20244001x_00000012x] mov.f32f32 r0.y, c4.z + :0:0029:0029[00000200x_00000000x] (rpt2)nop + :3:0030:0032[63808000x_00001012x] mad.f32 r0.x, c4.z, r0.y, r0.x + :1:0031:0033[20244001x_00000014x] mov.f32f32 r0.y, c5.x + :0:0032:0034[00000200x_00000000x] (rpt2)nop + :2:0033:0037[40100001x_00011020x] add.f r0.y, c8.x, r0.y + :0:0034:0038[00000000x_00000000x] nop + :4:0035:0039[80300000x_00000000x] rsq r0.x, r0.x + :2:0036:0040[40701004x_00001011x] (ss)mul.f r1.x, c4.y, r0.x + :0:0037:0041[00000200x_00000000x] (rpt2)nop + :2:0038:0044[40700004x_10190004x] mul.f r1.x, r1.x, c6.y + :2:0039:0045[40700005x_00001010x] mul.f r1.y, c4.x, r0.x + :0:0040:0046[00000200x_00000000x] (rpt2)nop + :3:0041:0049[63828004x_00041018x] mad.f32 r1.x, c6.x, r1.y, r1.x + :2:0042:0050[40700000x_00001012x] mul.f r0.x, c4.z, r0.x + :0:0043:0051[00000200x_00000000x] (rpt2)nop + :3:0044:0054[63800000x_0004101ax] mad.f32 r0.x, c6.z, r0.x, r1.x + :0:0045:0055[00000200x_00000000x] (rpt2)nop + :2:0046:0058[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x + :2:0047:0059[40500000x_00001034x] max.f r0.x, c13.x, r0.x + :0:0048:0060[00000100x_00000000x] (rpt1)nop + :1:0049:0062[200c4004x_00000004x] cov.u32f32 r1.x, r1.x + :3:0050:0063[63800001x_00011024x] mad.f32 r0.y, c9.x, r0.x, r0.y + :3:0051:0064[63800002x_00021025x] mad.f32 r0.z, c9.y, r0.x, r0.z + :3:0052:0065[63800000x_00031026x] mad.f32 r0.x, c9.z, r0.x, r0.w + :3:0053:0066[6382040ax_00011028x] (sat)mad.f32 r2.z, c10.x, r1.x, r0.y + :3:0054:0067[6382040bx_00021029x] (sat)mad.f32 r2.w, c10.y, r1.x, r0.z + :3:0055:0068[6382040cx_0000102ax] (sat)mad.f32 r3.x, c10.z, r1.x, r0.x + :0:0056:0069[03000000x_00000000x] end + :0:0057:0070[00000000x_00000000x] nop + :0:0058:0071[00000000x_00000000x] nop + :0:0059:0072[00000000x_00000000x] nop + :0:0060:0073[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-13 (cnt=14, max=13) + - used (merged): 0-27 (cnt=28, max=27) + - input (half): (cnt=0, max=0) + - input (full): 2-5 (cnt=4, max=5) + - const (half): (cnt=0, max=0) + - const (full): 0-18 20-26 32-34 36-38 40-42 52 (cnt=36, max=52) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 6-13 (cnt=8, max=13) (estimated) + - shaderdb: 74 instructions, 38 nops, 36 non-nops, (61 instlen), 0 half, 4 full + - shaderdb: 1 (ss), 0 (sy) +109d0bec: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 +109d0c0c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c +109d0c2c: 0040: 63828006 10010002 40700000 0001100f 63828009 00001005 63818000 00000010 +109d0c4c: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 63828007 10020002 +109d0c6c: 0080: 40700000 00000015 20244002 00001006 63818000 00000016 20244003 0000100a +109d0c8c: 00a0: 63820000 00000017 20244004 0000100e 63828008 00000011 20244000 00021021 +109d0cac: 00c0: 40100002 00041017 4050040d 00031022 40100003 00001011 40700000 00000000 +109d0ccc: 00e0: 00000000 00001010 63808000 00000012 20244001 00000000 00000200 00001012 +109d0cec: 0100: 63808000 00000014 20244001 00000000 00000200 00011020 40100001 00000000 +109d0d0c: 0120: 00000000 00000000 80300000 00001011 40701004 00000000 00000200 10190004 +109d0d2c: 0140: 40700004 00001010 40700005 00000000 00000200 00041018 63828004 00001012 +109d0d4c: 0160: 40700000 00000000 00000200 0004101a 63800000 00000000 00000200 00001034 +109d0d6c: 0180: 40b00004 00001034 40500000 00000000 00000100 00000004 200c4004 00011024 +109d0d8c: 01a0: 63800001 00021025 63800002 00031026 63800000 00011028 6382040a 00021029 +109d0dac: 01c0: 6382040b 0000102a 6382040c 00000000 03000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :0:0000:0000[00000000x_00000000x] nop + :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 + :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 + :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 + :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 + :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x + :0:0006:0006[03000000x_00000000x] end + :0:0007:0007[00000000x_00000000x] nop + :0:0008:0008[00000000x_00000000x] nop + :0:0009:0009[00000000x_00000000x] nop + :0:0010:0010[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-3 252 (cnt=5, max=3) + - used (merged): 0-7 504-505 (cnt=10, max=7) + - input (half): (cnt=0, max=0) + - input (full): 0-3 (cnt=4, max=3) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 252 (cnt=1, max=0) (estimated) + - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full + - shaderdb: 1 (ss), 0 (sy) +109d0df8: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 +109d0e18: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 +109d0e38: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109d0e84: 0000: c0002600 00000000 +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109d0e98: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410 +109d0eb8: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991 +109d0ed8: 0.000000 0.000000 1.000000 1.000000 0.040000 0.040000 0.200000 1.000000 +109d0ef8: -0.244131 0.617574 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 +109d0f18: 0.000000 0.000000 0.000000 1.000000 0.200000 0.200000 1.000000 1.000000 +109d0f38: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 +109d0e98: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc +109d0eb8: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f +109d0ed8: 0040: 00000000 00000000 3f800000 3f800000 3d23d70b 3d23d70b 3e4ccccd 3f800000 +109d0ef8: 0060: be79fd80 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 +109d0f18: 0080: 00000000 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 +109d0f38: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 +109d0e8c: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 +109d0eac: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638 +109d0ecc: 0040: 4188a9c2 4203c74b 42146d8f 00000000 00000000 3f800000 3f800000 3d23d70b +109d0eec: 0060: 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000 3f800000 +109d0f0c: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3e4ccccd +109d0f2c: 00a0: 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 00000000 +109d0f4c: 00c0: 00000000 00000000 3f800000 +t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) + { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109d0f64: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 +109d0f64: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +109d0f58: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +t0 write VFD_FETCH[0].INSTR_0 (220a) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } + VFD_FETCH[0].INSTR_1: 0x107cb000 + VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +109d0f74: 0000: 0003220a 0000060b 107cb000 00100000 00000001 +t0 write VFD_DECODE[0].INSTR (228a) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +109d0f88: 0000: 0000228a 2c0020df +t0 write VFD_CONTROL_0 (2200) + VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } + VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + VFD_CONTROL_2: 0 + VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + VFD_CONTROL_4: 0 +109d0f90: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000 +t0 write UCHE_INVALIDATE0 (0e8a) + UCHE_INVALIDATE0: 0 + UCHE_INVALIDATE1: 0x12 +109d0fa8: 0000: 00010e8a 00000000 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109d0fb4: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109d0fc0: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x50 + :0,79,115,80 +109d0fc8: 0000: 0000057f 00000050 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 120 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd0f78 } + { INDX_SIZE = 240 } + draw[13] register values +!+ 0000004f CP_SCRATCH[0x5].REG: 0x4f + :0,79,115,80 +!+ 00000050 CP_SCRATCH[0x7].REG: 0x50 + :0,79,115,80 + + 00000000 UCHE_INVALIDATE0: 0 + + 00000012 UCHE_INVALIDATE1: 0x12 + + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } +!+ 00000000 GRAS_CNTL: { 0 } + + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + + 00000010 GRAS_SU_POINT_SIZE: 1.000000 + + 00000000 GRAS_ALPHA_CONTROL: { 0 } + + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } + + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } + + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } + + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 + + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff + + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +!+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } + + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + + 00000000 VFD_CONTROL_2: 0 + + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + + 00000000 VFD_CONTROL_4: 0 + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +!+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } + + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 + + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +!+ 2c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } + + 00140010 SP_SP_CTRL_REG: { 0x140010 } + + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +!+ 00201000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 4 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } +!+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } +!+ 0010fc06 SP_VS_PARAM_REG: { POSREGID = r1.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +!+ 00001e0a SP_VS_OUT[0].REG: { A_REGID = r2.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } + + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } +!+ 10cd0000 SP_VS_OBJ_START: 0x10cd0000 + + 00000004 SP_VS_LENGTH_REG: 4 +!+ 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } + + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +!+ 10cd2000 SP_FS_OBJ_START: 0x10cd2000 + + 00000001 SP_FS_LENGTH_REG: 1 + + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +!+ 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } +!+ 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } +!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 00000003 HLSQ_UPDATE_CONTROL: 0x3 +109d0fd0: 0000: c0053800 00000404 00000001 00000078 00000000 10bd0f78 000000f0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x51 + :0,79,115,81 +109d0fec: 0000: 0000057f 00000051 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x55 + :0,85,115,81 +109d0ff4: 0000: 0000057d 00000055 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109d0ffc: 0000: 000121c4 02000001 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109d1008: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109d1014: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x56 + :0,85,115,86 +109d101c: 0000: 0000057f 00000056 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 60 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd1068 } + { INDX_SIZE = 120 } + draw[14] register values +!+ 00000055 CP_SCRATCH[0x5].REG: 0x55 + :0,85,115,86 +!+ 00000056 CP_SCRATCH[0x7].REG: 0x56 + :0,85,115,86 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +109d1024: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd1068 00000078 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x57 + :0,85,115,87 +109d1040: 0000: 0000057f 00000057 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x5b + :0,91,115,87 +109d1048: 0000: 0000057d 0000005b +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109d1050: 0000: 000121c4 02000001 00000012 +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109d105c: 0000: c0002600 00000000 +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109d1070: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410 +109d1090: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991 +109d10b0: 0.000000 0.000000 -1.000000 1.000000 0.040000 0.040000 0.200000 1.000000 +109d10d0: -0.244131 0.617574 0.747665 0.000000 1.000000 0.000000 0.000000 0.000000 +109d10f0: 0.000000 0.000000 0.000000 1.000000 0.200000 0.200000 1.000000 1.000000 +109d1110: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 1.000000 +109d1070: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc +109d1090: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f +109d10b0: 0040: 00000000 00000000 bf800000 3f800000 3d23d70b 3d23d70b 3e4ccccd 3f800000 +109d10d0: 0060: be79fd80 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 +109d10f0: 0080: 00000000 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 +109d1110: 00a0: 00000000 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 +109d1064: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 +109d1084: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638 +109d10a4: 0040: 4188a9c2 4203c74b 42146d8f 00000000 00000000 bf800000 3f800000 3d23d70b +109d10c4: 0060: 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000 3f800000 +109d10e4: 0080: 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 3e4ccccd +109d1104: 00a0: 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 00000000 +109d1124: 00c0: 00000000 00000000 3f800000 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109d1130: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109d113c: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x5c + :0,91,115,92 +109d1144: 0000: 0000057f 0000005c +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 120 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd10e0 } + { INDX_SIZE = 240 } + draw[15] register values +!+ 0000005b CP_SCRATCH[0x5].REG: 0x5b + :0,91,115,92 +!+ 0000005c CP_SCRATCH[0x7].REG: 0x5c + :0,91,115,92 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +109d114c: 0000: c0053800 00000404 00000001 00000078 00000000 10bd10e0 000000f0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x5d + :0,91,115,93 +109d1168: 0000: 0000057f 0000005d +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x61 + :0,97,115,93 +109d1170: 0000: 0000057d 00000061 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109d1178: 0000: 000121c4 02000001 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109d1184: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109d1190: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x62 + :0,97,115,98 +109d1198: 0000: 0000057f 00000062 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 60 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd11d0 } + { INDX_SIZE = 120 } + draw[16] register values +!+ 00000061 CP_SCRATCH[0x5].REG: 0x61 + :0,97,115,98 +!+ 00000062 CP_SCRATCH[0x7].REG: 0x62 + :0,97,115,98 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +109d11a0: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd11d0 00000078 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x63 + :0,97,115,99 +109d11bc: 0000: 0000057f 00000063 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x67 + :0,103,115,99 +109d11c4: 0000: 0000057d 00000067 +t0 write RB_DEPTH_CONTROL (2101) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } +109d11cc: 0000: 00002101 80000016 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0 } +109d11d4: 0000: 00002073 00000000 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109d11dc: 0000: 000121c4 02000001 00000012 +t0 write HLSQ_UPDATE_CONTROL (23db) + HLSQ_UPDATE_CONTROL: 0x3 +109d11e8: 0000: 000023db 00000003 +t0 write HLSQ_CONTROL_0_REG (23c0) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +109d11f0: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc +t0 write HLSQ_VS_CONTROL_REG (23c5) + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +109d1208: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { 0x140010 } +109d1220: 0000: 000022c0 00140010 +t0 write SP_INSTR_CACHE_CTRL (22c1) + SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +109d1228: 0000: 000022c1 000005ff +t0 write SP_VS_LENGTH_REG (22e5) + SP_VS_LENGTH_REG: 4 +109d1230: 0000: 000022e5 00000004 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } + SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +109d1238: 0000: 000222c4 00201400 08000042 0010fc0a +t0 write SP_VS_OUT[0].REG (22c7) + SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +109d1248: 0000: 000022c7 00001e0e +t0 write SP_VS_VPC_DST[0].REG (22d8) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } +109d1250: 0000: 000022d8 08080808 +t0 write SP_VS_OBJ_OFFSET_REG (22e0) + SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + SP_VS_OBJ_START: 0x10cd5000 +109d1258: 0000: 000122e0 00000000 10cd5000 +t0 write SP_FS_LENGTH_REG (22ef) + SP_FS_LENGTH_REG: 1 +109d1264: 0000: 000022ef 00000001 +t0 write SP_FS_CTRL_REG0 (22e8) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } +109d126c: 0000: 000122e8 00340402 8010003e +t0 write SP_FS_OBJ_OFFSET_REG (22ea) + SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + SP_FS_OBJ_START: 0x10cd2000 +109d1278: 0000: 000122ea 7e420000 10cd2000 +t0 write SP_HS_OBJ_OFFSET_REG (230d) + SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d1284: 0000: 0000230d 7e420000 +t0 write SP_DS_OBJ_OFFSET_REG (2334) + SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d128c: 0000: 00002334 7e420000 +t0 write SP_GS_OBJ_OFFSET_REG (235b) + SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d1294: 0000: 0000235b 7e420000 +t0 write GRAS_CNTL (2003) + GRAS_CNTL: { 0 } +109d129c: 0000: 00002003 00000000 +t0 write RB_RENDER_CONTROL2 (20a3) + RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } +109d12a4: 0000: 000020a3 00000000 +t0 write RB_FS_OUTPUT_REG (2100) + RB_FS_OUTPUT_REG: { MRT = 1 } +109d12ac: 0000: 00002100 00000001 +t0 write SP_FS_OUTPUT_REG (22f0) + SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +109d12b4: 0000: 000022f0 0000fc01 +t0 write SP_FS_MRT[0].REG (22f1) + SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } +109d12bc: 0000: 000722f1 0001a000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_ATTR (2140) + VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +109d12e0: 0000: 00012140 42001004 00040400 +t0 write VPC_VARYING_INTERP[0].MODE (2142) + VPC_VARYING_INTERP[0].MODE: 0x55 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +109d12ec: 0000: 00072142 00000055 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_VARYING_PS_REPL[0].MODE (214a) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +109d1310: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x + :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w + :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x + :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y + :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x + :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y + :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x + :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y + :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y + :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x + :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x + :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x + :0:0012:0012[00000000x_00000000x] nop + :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x + :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z + :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y + :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x + :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y + :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x + :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w + :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x + :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w + :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z + :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x + :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x + :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x + :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z + :0:0027:0027[00000200x_00000000x] (rpt2)nop + :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w + :0:0029:0031[00000000x_00000000x] nop + :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x + :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x + :0:0032:0034[00000200x_00000000x] (rpt2)nop + :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y + :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x + :0:0035:0039[00000200x_00000000x] (rpt2)nop + :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x + :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x + :0:0038:0044[00000200x_00000000x] (rpt2)nop + :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x + :0:0040:0048[00000200x_00000000x] (rpt2)nop + :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x + :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x + :0:0043:0053[00000100x_00000000x] (rpt1)nop + :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x + :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y + :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z + :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w + :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y + :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z + :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x + :0:0051:0062[03000000x_00000000x] end + :0:0052:0063[00000000x_00000000x] nop + :0:0053:0064[00000000x_00000000x] nop + :0:0054:0065[00000000x_00000000x] nop + :0:0055:0066[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-8 10-17 (cnt=17, max=17) + - used (merged): 0-17 20-35 (cnt=34, max=35) + - input (half): (cnt=0, max=0) + - input (full): 2-8 (cnt=7, max=8) + - const (half): (cnt=0, max=0) + - const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 10-17 (cnt=8, max=17) (estimated) + - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full + - shaderdb: 1 (ss), 0 (sy) +109d1334: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 +109d1354: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c +109d1374: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 +109d1394: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 +109d13b4: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a +109d13d4: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d +109d13f4: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 +109d1414: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 +109d1434: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 +109d1454: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 +109d1474: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 +109d1494: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 +109d14b4: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 +109d14d4: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :0:0000:0000[00000000x_00000000x] nop + :6:0001:0001[c7c60000x_01c00000x] ldlv.u32 r0.x, l[0], 1 + :6:0002:0002[c7c60001x_01c00002x] ldlv.u32 r0.y, l[1], 1 + :6:0003:0003[c7c60002x_01c00004x] ldlv.u32 r0.z, l[2], 1 + :6:0004:0004[c7c60003x_01c00006x] ldlv.u32 r0.w, l[3], 1 + :2:0005:0005[473090fcx_00002000x] (ss)bary.f (ei)r63.x, 0, r0.x + :0:0006:0006[03000000x_00000000x] end + :0:0007:0007[00000000x_00000000x] nop + :0:0008:0008[00000000x_00000000x] nop + :0:0009:0009[00000000x_00000000x] nop + :0:0010:0010[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-3 252 (cnt=5, max=3) + - used (merged): 0-7 504-505 (cnt=10, max=7) + - input (half): (cnt=0, max=0) + - input (full): 0-3 (cnt=4, max=3) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 252 (cnt=1, max=0) (estimated) + - shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full + - shaderdb: 1 (ss), 0 (sy) +109d1540: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002 +109d1560: 0020: c7c60001 01c00004 c7c60002 01c00006 c7c60003 00002000 473090fc 00000000 +109d1580: 0040: 03000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109d15cc: 0000: c0002600 00000000 +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109d15e0: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410 +109d1600: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991 +109d1620: 0.040000 0.040000 0.200000 1.000000 -0.244131 0.617574 0.747665 0.000000 +109d1640: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 +109d1660: 0.200000 0.200000 1.000000 1.000000 0.000000 0.000000 0.000000 1.000000 +109d1680: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 +109d15e0: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc +109d1600: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f +109d1620: 0040: 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000 +109d1640: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 +109d1660: 0080: 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 +109d1680: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 +109d15d4: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 +109d15f4: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638 +109d1614: 0040: 4188a9c2 4203c74b 42146d8f 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80 +109d1634: 0060: 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 +109d1654: 0080: 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000 +109d1674: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 +109d1694: 00c0: 02020202 02020202 00000202 +t3 opcode: CP_LOAD_STATE4 (30) (7 dwords) + { DST_OFF = 13 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109d16ac: 0.000000 -28026765312.000000 -28026765312.000000 -28026765312.000000 +109d16ac: 0000: 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +109d16a0: 0000: c0053000 0060000d 00000001 00000000 d0d0d0d0 d0d0d0d0 d0d0d0d0 +t0 write VFD_FETCH[0].INSTR_0 (220a) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } + VFD_FETCH[0].INSTR_1: 0x107cb000 + VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +109d16bc: 0000: 0003220a 00080c0b 107cb000 00100000 00000001 +t0 write VFD_DECODE[0].INSTR (228a) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } +109d16d0: 0000: 0000228a 6c0020df +t0 write VFD_FETCH[0x1].INSTR_0 (220e) + VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } + VFD_FETCH[0x1].INSTR_1: 0x107cb00c + VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } + VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } +109d16d8: 0000: 0003220e 00000c0b 107cb00c 000ffff4 00000001 +t0 write VFD_DECODE[0x1].INSTR (228b) + VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +109d16ec: 0000: 0000228b 2c0060df +t0 write VFD_CONTROL_0 (2200) + VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + VFD_CONTROL_2: 0 + VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + VFD_CONTROL_4: 0 +109d16f4: 0000: 00042200 082a0008 fcfc0081 00000000 0000fc00 00000000 +t0 write UCHE_INVALIDATE0 (0e8a) + UCHE_INVALIDATE0: 0 + UCHE_INVALIDATE1: 0x12 +109d170c: 0000: 00010e8a 00000000 00000012 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109d1718: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109d1724: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x68 + :0,103,115,104 +109d172c: 0000: 0000057f 00000068 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 240 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd1248 } + { INDX_SIZE = 480 } + draw[17] register values +!+ 00000067 CP_SCRATCH[0x5].REG: 0x67 + :0,103,115,104 +!+ 00000068 CP_SCRATCH[0x7].REG: 0x68 + :0,103,115,104 + + 00000000 UCHE_INVALIDATE0: 0 + + 00000012 UCHE_INVALIDATE1: 0x12 + + 00000000 GRAS_CNTL: { 0 } + + 00000000 GRAS_ALPHA_CONTROL: { 0 } + + 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } + + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } + + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } + + 00000055 VPC_VARYING_INTERP[0].MODE: 0x55 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff +!+ 082a0008 VFD_CONTROL_0: { TOTALATTRTOVS = 8 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 2 | STRMFETCHINSTRCNT = 2 | 0xa0000 } + + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + + 00000000 VFD_CONTROL_2: 0 + + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + + 00000000 VFD_CONTROL_4: 0 + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +!+ 00080c0b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 | SWITCHNEXT } + + 107cb000 VFD_FETCH[0].INSTR_1: 0x107cb000 + + 00100000 VFD_FETCH[0].INSTR_2: { SIZE = 0x100000 } + + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } + + 00000c0b VFD_FETCH[0x1].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 24 } + + 107cb00c VFD_FETCH[0x1].INSTR_1: 0x107cb00c + + 000ffff4 VFD_FETCH[0x1].INSTR_2: { SIZE = 0xffff4 } + + 00000001 VFD_FETCH[0x1].INSTR_3: { STEPRATE = 1 } +!+ 6c0020df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID | SWITCHNEXT } + + 2c0060df VFD_DECODE[0x1].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r1.z | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } + + 00140010 SP_SP_CTRL_REG: { 0x140010 } + + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +!+ 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } +!+ 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } +!+ 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +!+ 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } + + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } +!+ 10cd5000 SP_VS_OBJ_START: 0x10cd5000 + + 00000004 SP_VS_LENGTH_REG: 4 + + 00340402 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } + + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 10cd2000 SP_FS_OBJ_START: 0x10cd2000 + + 00000001 SP_FS_LENGTH_REG: 1 + + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } + + 0001a000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = RB4_R8G8B8A8_UNORM } + + 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + + fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 00000003 HLSQ_UPDATE_CONTROL: 0x3 +109d1734: 0000: c0053800 00000404 00000001 000000f0 00000000 10bd1248 000001e0 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x69 + :0,103,115,105 +109d1750: 0000: 0000057f 00000069 +t0 write CP_SCRATCH[0x5].REG (057d) + CP_SCRATCH[0x5].REG: 0x6d + :0,109,115,105 +109d1758: 0000: 0000057d 0000006d +t0 write RB_DEPTH_CONTROL (2101) + RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } +109d1760: 0000: 00002101 80000016 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0 } +109d1768: 0000: 00002073 00000000 +t0 write GRAS_SU_MODE_CONTROL (2078) + GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } +109d1770: 0000: 00002078 00100012 +t0 write GRAS_SU_POINT_MINMAX (2070) + GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + GRAS_SU_POINT_SIZE: 1.000000 +109d1778: 0000: 00012070 00100010 00000010 +t0 write GRAS_SU_POLY_OFFSET_SCALE (2074) + GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 +109d1784: 0000: 00022074 00000000 00000000 00000000 +t0 write GRAS_CL_CLIP_CNTL (2000) + GRAS_CL_CLIP_CNTL: { 0x80000 } +109d1794: 0000: 00002000 00080000 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } +109d179c: 0000: 000121c4 02000001 00000012 +t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) + GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +109d17a8: 0000: 0001209c 012b012b 00000000 +t0 write RB_VPORT_Z_CLAMP[0].MIN (2120) + RB_VPORT_Z_CLAMP[0].MIN: 0 + RB_VPORT_Z_CLAMP[0].MAX: 0xffffff +109d17b4: 0000: 00012120 00000000 00ffffff +t0 write HLSQ_UPDATE_CONTROL (23db) + HLSQ_UPDATE_CONTROL: 0x3 +109d17c0: 0000: 000023db 00000003 +t0 write HLSQ_CONTROL_0_REG (23c0) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +109d17c8: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfc00 00fcfcfc +t0 write HLSQ_VS_CONTROL_REG (23c5) + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +109d17e0: 0000: 000423c5 04000042 017e423e 007e4200 007e4200 007e4200 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { 0x140010 } +109d17f8: 0000: 000022c0 00140010 +t0 write SP_INSTR_CACHE_CTRL (22c1) + SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +109d1800: 0000: 000022c1 000005ff +t0 write SP_VS_LENGTH_REG (22e5) + SP_VS_LENGTH_REG: 4 +109d1808: 0000: 000022e5 00000004 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } + SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } +109d1810: 0000: 000222c4 00201400 08000042 0010fc0a +t0 write SP_VS_OUT[0].REG (22c7) + SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } +109d1820: 0000: 000022c7 00001e0e +t0 write SP_VS_VPC_DST[0].REG (22d8) + SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } +109d1828: 0000: 000022d8 08080808 +t0 write SP_VS_OBJ_OFFSET_REG (22e0) + SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + SP_VS_OBJ_START: 0x10cd5000 +109d1830: 0000: 000122e0 00000000 10cd5000 +t0 write SP_FS_LENGTH_REG (22ef) + SP_FS_LENGTH_REG: 1 +109d183c: 0000: 000022ef 00000001 +t0 write SP_FS_CTRL_REG0 (22e8) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } +109d1844: 0000: 000122e8 00340802 8010003e +t0 write SP_FS_OBJ_OFFSET_REG (22ea) + SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + SP_FS_OBJ_START: 0x108cb000 +109d1850: 0000: 000122ea 7e420000 108cb000 +t0 write SP_HS_OBJ_OFFSET_REG (230d) + SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d185c: 0000: 0000230d 7e420000 +t0 write SP_DS_OBJ_OFFSET_REG (2334) + SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d1864: 0000: 00002334 7e420000 +t0 write SP_GS_OBJ_OFFSET_REG (235b) + SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +109d186c: 0000: 0000235b 7e420000 +t0 write GRAS_CNTL (2003) + GRAS_CNTL: { IJ_PERSP } +109d1874: 0000: 00002003 00000001 +t0 write RB_RENDER_CONTROL2 (20a3) + RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } +109d187c: 0000: 000020a3 00001000 +t0 write RB_FS_OUTPUT_REG (2100) + RB_FS_OUTPUT_REG: { MRT = 1 } +109d1884: 0000: 00002100 00000001 +t0 write SP_FS_OUTPUT_REG (22f0) + SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +109d188c: 0000: 000022f0 0000fc01 +t0 write SP_FS_MRT[0].REG (22f1) + SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } + SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } + SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } +109d1894: 0000: 000722f1 0001a002 00000002 00000002 00000002 00000002 00000002 00000002 +109d18b4: 0020: 00000002 +t0 write VPC_ATTR (2140) + VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +109d18b8: 0000: 00012140 42001004 00040400 +t0 write VPC_VARYING_INTERP[0].MODE (2142) + VPC_VARYING_INTERP[0].MODE: 0 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +109d18c4: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_VARYING_PS_REPL[0].MODE (214a) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +109d18e8: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (131 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[40700000x_10000002x] mul.f r0.x, r0.z, c0.x + :2:0001:0001[40700001x_10030002x] mul.f r0.y, r0.z, c0.w + :3:0002:0002[63818000x_00001004x] mad.f32 r0.x, c1.x, r0.w, r0.x + :3:0003:0003[63818001x_00011007x] mad.f32 r0.y, c1.w, r0.w, r0.y + :3:0004:0004[63820000x_00001008x] mad.f32 r0.x, c2.x, r1.x, r0.x + :3:0005:0005[63820001x_0001100bx] mad.f32 r0.y, c2.w, r1.x, r0.y + :3:0006:0006[6382800ax_0000100cx] mad.f32 r2.z, c3.x, r1.y, r0.x + :2:0007:0007[40700000x_10010002x] mul.f r0.x, r0.z, c0.y + :3:0008:0008[6382800dx_0001100fx] mad.f32 r3.y, c3.w, r1.y, r0.y + :3:0009:0009[63818000x_00001005x] mad.f32 r0.x, c1.y, r0.w, r0.x + :1:0010:0010[20244001x_00000010x] mov.f32f32 r0.y, c4.x + :3:0011:0011[63820000x_00001009x] mad.f32 r0.x, c2.y, r1.x, r0.x + :0:0012:0012[00000000x_00000000x] nop + :3:0013:0013[6382800bx_0000100dx] mad.f32 r2.w, c3.y, r1.y, r0.x + :2:0014:0014[40700000x_10020002x] mul.f r0.x, r0.z, c0.z + :2:0015:0015[40100001x_0001101cx] add.f r0.y, c7.x, r0.y + :3:0016:0016[63818000x_00001006x] mad.f32 r0.x, c1.z, r0.w, r0.x + :1:0017:0017[20244002x_00000011x] mov.f32f32 r0.z, c4.y + :3:0018:0018[63820000x_0000100ax] mad.f32 r0.x, c2.z, r1.x, r0.x + :1:0019:0019[20244004x_00000013x] mov.f32f32 r1.x, c4.w + :3:0020:0020[6382800cx_0000100ex] mad.f32 r3.x, c3.z, r1.y, r0.x + :2:0021:0021[40700000x_00070007x] mul.f r0.x, r1.w, r1.w + :2:0022:0022[40100002x_0002101dx] add.f r0.z, c7.y, r0.z + :3:0023:0023[63830000x_00000006x] mad.f32 r0.x, r1.z, r1.z, r0.x + :2:0024:0024[40500411x_00041013x] (sat)max.f r4.y, c4.w, r1.x + :3:0025:0025[63840000x_00000008x] mad.f32 r0.x, r2.x, r2.x, r0.x + :1:0026:0026[20244003x_00000012x] mov.f32f32 r0.w, c4.z + :0:0027:0027[00000200x_00000000x] (rpt2)nop + :2:0028:0030[40100003x_0003101ex] add.f r0.w, c7.z, r0.w + :0:0029:0031[00000000x_00000000x] nop + :4:0030:0032[80300000x_00000000x] rsq r0.x, r0.x + :2:0031:0033[40701004x_00000007x] (ss)mul.f r1.x, r1.w, r0.x + :0:0032:0034[00000200x_00000000x] (rpt2)nop + :2:0033:0037[40700004x_10150004x] mul.f r1.x, r1.x, c5.y + :2:0034:0038[40700005x_00000006x] mul.f r1.y, r1.z, r0.x + :0:0035:0039[00000200x_00000000x] (rpt2)nop + :3:0036:0042[63828004x_00041014x] mad.f32 r1.x, c5.x, r1.y, r1.x + :2:0037:0043[40700000x_00000008x] mul.f r0.x, r2.x, r0.x + :0:0038:0044[00000200x_00000000x] (rpt2)nop + :3:0039:0047[63800000x_00041016x] mad.f32 r0.x, c5.z, r0.x, r1.x + :0:0040:0048[00000200x_00000000x] (rpt2)nop + :2:0041:0051[40b00004x_00001034x] cmps.f.lt r1.x, c13.x, r0.x + :2:0042:0052[40500000x_00001034x] max.f r0.x, c13.x, r0.x + :0:0043:0053[00000100x_00000000x] (rpt1)nop + :1:0044:0055[200c4004x_00000004x] cov.u32f32 r1.x, r1.x + :3:0045:0056[63800001x_00011020x] mad.f32 r0.y, c8.x, r0.x, r0.y + :3:0046:0057[63800002x_00021021x] mad.f32 r0.z, c8.y, r0.x, r0.z + :3:0047:0058[63800000x_00031022x] mad.f32 r0.x, c8.z, r0.x, r0.w + :3:0048:0059[6382040ex_00011024x] (sat)mad.f32 r3.z, c9.x, r1.x, r0.y + :3:0049:0060[6382040fx_00021025x] (sat)mad.f32 r3.w, c9.y, r1.x, r0.z + :3:0050:0061[63820410x_00001026x] (sat)mad.f32 r4.x, c9.z, r1.x, r0.x + :0:0051:0062[03000000x_00000000x] end + :0:0052:0063[00000000x_00000000x] nop + :0:0053:0064[00000000x_00000000x] nop + :0:0054:0065[00000000x_00000000x] nop + :0:0055:0066[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-8 10-17 (cnt=17, max=17) + - used (merged): 0-17 20-35 (cnt=34, max=35) + - input (half): (cnt=0, max=0) + - input (full): 2-8 (cnt=7, max=8) + - const (half): (cnt=0, max=0) + - const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 10-17 (cnt=8, max=17) (estimated) + - shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full + - shaderdb: 1 (ss), 0 (sy) +109d190c: 0000: c0813000 01200000 00000000 10000002 40700000 10030002 40700001 00001004 +109d192c: 0020: 63818000 00011007 63818001 00001008 63820000 0001100b 63820001 0000100c +109d194c: 0040: 6382800a 10010002 40700000 0001100f 6382800d 00001005 63818000 00000010 +109d196c: 0060: 20244001 00001009 63820000 00000000 00000000 0000100d 6382800b 10020002 +109d198c: 0080: 40700000 0001101c 40100001 00001006 63818000 00000011 20244002 0000100a +109d19ac: 00a0: 63820000 00000013 20244004 0000100e 6382800c 00070007 40700000 0002101d +109d19cc: 00c0: 40100002 00000006 63830000 00041013 40500411 00000008 63840000 00000012 +109d19ec: 00e0: 20244003 00000000 00000200 0003101e 40100003 00000000 00000000 00000000 +109d1a0c: 0100: 80300000 00000007 40701004 00000000 00000200 10150004 40700004 00000006 +109d1a2c: 0120: 40700005 00000000 00000200 00041014 63828004 00000008 40700000 00000000 +109d1a4c: 0140: 00000200 00041016 63800000 00000000 00000200 00001034 40b00004 00001034 +109d1a6c: 0160: 40500000 00000000 00000100 00000004 200c4004 00011020 63800001 00021021 +109d1a8c: 0180: 63800002 00031022 63800000 00011024 6382040e 00021025 6382040f 00001026 +109d1aac: 01a0: 63820410 00000000 03000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x + :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x + :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x + :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x + :0:0004:0004[03000000x_00000000x] end + :0:0005:0005[00000000x_00000000x] nop + :0:0006:0006[00000000x_00000000x] nop + :0:0007:0007[00000000x_00000000x] nop + :0:0008:0008[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0 2-5 (cnt=5, max=5) + - used (merged): 0-1 4-11 (cnt=10, max=11) + - input (half): (cnt=0, max=0) + - input (full): 0 (cnt=1, max=0) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 2-5 (cnt=4, max=5) (estimated) + - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 0 half, 2 full + - shaderdb: 0 (ss), 0 (sy) +109d1b18: 0000: c0213000 00700000 00000000 00002000 47300002 00002001 47300003 00002002 +109d1b38: 0020: 47300004 00002003 47308005 00000000 03000000 00000000 00000000 00000000 +* +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +109d1ba4: 0000: c0002600 00000000 +t3 opcode: CP_LOAD_STATE4 (30) (51 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 12 } + { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0 } +109d1bb8: 3.924428 -1.210718 0.674073 0.570369 1.829991 4.619613 -0.131666 -0.111410 +109d1bd8: 2.500000 -1.480991 -0.961761 -0.813798 -13.423393 17.082890 32.944622 37.106991 +109d1bf8: 0.040000 0.040000 0.200000 1.000000 -0.244131 0.617574 0.747665 0.000000 +109d1c18: 1.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 1.000000 +109d1c38: 0.200000 0.200000 1.000000 1.000000 0.000000 0.000000 0.000000 1.000000 +109d1c58: 0.000000 0.000000 0.000000 1.000000 0.000000 0.000000 0.000000 0.000000 +109d1bb8: 0000: 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 4093d3df be06d382 bde42adc +109d1bd8: 0020: 40200000 bfbd9119 bf7635f5 bf50550b c156c638 4188a9c2 4203c74b 42146d8f +109d1bf8: 0040: 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80 3f1e194f 3f3f66f5 00000000 +109d1c18: 0060: 3f800000 00000000 00000000 00000000 00000000 00000000 00000000 3f800000 +109d1c38: 0080: 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000 00000000 00000000 3f800000 +109d1c58: 00a0: 00000000 00000000 00000000 3f800000 02020000 02020202 02020202 00000202 +109d1bac: 0000: c0313000 03200000 00000001 407b29d2 bf9af8cb 3f2c9009 3f1203b9 3fea3d23 +109d1bcc: 0020: 4093d3df be06d382 bde42adc 40200000 bfbd9119 bf7635f5 bf50550b c156c638 +109d1bec: 0040: 4188a9c2 4203c74b 42146d8f 3d23d70b 3d23d70b 3e4ccccd 3f800000 be79fd80 +109d1c0c: 0060: 3f1e194f 3f3f66f5 00000000 3f800000 00000000 00000000 00000000 00000000 +109d1c2c: 0080: 00000000 00000000 3f800000 3e4ccccd 3e4ccccd 3f800000 3f800000 00000000 +109d1c4c: 00a0: 00000000 00000000 3f800000 00000000 00000000 00000000 3f800000 02020000 +109d1c6c: 00c0: 02020202 02020202 00000202 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +109d1c78: 0000: 00012208 00000000 00000000 +t0 write PC_RESTART_INDEX (21c6) + PC_RESTART_INDEX: 0xffffffff +109d1c84: 0000: 000021c6 ffffffff +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x6e + :0,109,115,110 +109d1c8c: 0000: 0000057f 0000006e +t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords) + { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 60 } + { FIRST_INDX = 0 } + { INDX_BASE = 0x10bd1428 } + { INDX_SIZE = 120 } + draw[18] register values +!+ 0000006d CP_SCRATCH[0x5].REG: 0x6d + :0,109,115,110 +!+ 0000006e CP_SCRATCH[0x7].REG: 0x6e + :0,109,115,110 + + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } +!+ 00000001 GRAS_CNTL: { IJ_PERSP } + + 00100010 GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 } + + 00000010 GRAS_SU_POINT_SIZE: 1.000000 + + 00000000 GRAS_ALPHA_CONTROL: { 0 } + + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 + + 00000000 GRAS_SU_POLY_OFFSET_CLAMP: 0.000000 + + 00100012 GRAS_SU_MODE_CONTROL: { CULL_BACK | LINEHALFWIDTH = 0.500000 | RENDERING_PASS } + + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL } + + 00000001 RB_FS_OUTPUT_REG: { MRT = 1 } + + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE } + + 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0 + + 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff + + 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 } + + 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 } +!+ 00000000 VPC_VARYING_INTERP[0].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 + + 02000001 PC_PRIM_VTX_CNTL: { VAROUT = 1 | PROVOKING_VTX_LAST } + + 00000012 PC_PRIM_VTX_CNTL2: { POLYMODE_FRONT_PTYPE = PC_DRAW_TRIANGLES | POLYMODE_BACK_PTYPE = PC_DRAW_TRIANGLES } + + ffffffff PC_RESTART_INDEX: 0xffffffff + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 + + 00140010 SP_SP_CTRL_REG: { 0x140010 } + + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } + + 00201400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + + 08000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 8 } + + 0010fc0a SP_VS_PARAM_REG: { POSREGID = r2.z | PSIZEREGID = r63.x | TOTALVSOUTVAR = 1 } + + 00001e0e SP_VS_OUT[0].REG: { A_REGID = r3.z | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 } + + 08080808 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 8 | OUTLOC1 = 8 | OUTLOC2 = 8 | OUTLOC3 = 8 } + + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + + 10cd5000 SP_VS_OBJ_START: 0x10cd5000 + + 00000004 SP_VS_LENGTH_REG: 4 +!+ 00340802 SP_FS_CTRL_REG0: { THREADMODE = MULTI | VARYING | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + + 8010003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | VARYING | 0x80000000 } + + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +!+ 108cb000 SP_FS_OBJ_START: 0x108cb000 + + 00000001 SP_FS_LENGTH_REG: 1 + + 0000fc01 SP_FS_OUTPUT_REG: { MRT = 1 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +!+ 0001a002 SP_FS_MRT[0].REG: { REGID = r0.z | MRTFORMAT = RB4_R8G8B8A8_UNORM } +!+ 00000002 SP_FS_MRT[0x1].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x2].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x3].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x4].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x5].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x6].REG: { REGID = r0.z | MRTFORMAT = 0 } +!+ 00000002 SP_FS_MRT[0x7].REG: { REGID = r0.z | MRTFORMAT = 0 } + + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } +!+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } + + 04000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 4 } + + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 00000003 HLSQ_UPDATE_CONTROL: 0x3 +109d1c94: 0000: c0053800 00000404 00000001 0000003c 00000000 10bd1428 00000078 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x6f + :0,109,115,111 +109d1cb0: 0000: 0000057f 0000006f +108ce2d0: 0000: c0013f00 109ce000 00000f2e +t2 nop +t0 write RB_DEPTH_CONTROL (2101) + RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } +108ce2e8: 0000: 00002101 00000000 +t0 write RB_STENCIL_CONTROL (2106) + RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + RB_STENCIL_CONTROL2: { 0 } +108ce2f0: 0000: 00012106 00000000 00000000 +t0 write RB_STENCILREFMASK (210b) + RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } + RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } +108ce2fc: 0000: 0001210b ffff0000 ffff0000 +t0 write GRAS_SU_MODE_CONTROL (2078) + GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } +108ce308: 0000: 00002078 00000000 +t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords) +108ce310: 0000: c0002600 00000000 +t0 write GRAS_CL_CLIP_CNTL (2000) + GRAS_CL_CLIP_CNTL: { 0x80000 } +108ce318: 0000: 00002000 00080000 +t0 write GRAS_CL_VPORT_XOFFSET_0 (2008) + GRAS_CL_VPORT_XOFFSET_0: 150.000000 + GRAS_CL_VPORT_XSCALE_0: 150.000000 + GRAS_CL_VPORT_YOFFSET_0: 150.000000 + GRAS_CL_VPORT_YSCALE_0: -150.000000 + GRAS_CL_VPORT_ZOFFSET_0: 0.000000 + GRAS_CL_VPORT_ZSCALE_0: 1.000000 +108ce320: 0000: 00052008 43160000 43160000 43160000 c3160000 00000000 3f800000 +t0 write RB_RENDER_CONTROL (20a1) + RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0xa } +108ce33c: 0000: 000020a1 0000002a +t0 write GRAS_SC_CONTROL (207b) + GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0x1 } +108ce344: 0000: 0000207b 00001808 +t0 write PC_PRIM_VTX_CNTL (21c4) + PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST } +108ce34c: 0000: 000021c4 02000000 +t0 write GRAS_ALPHA_CONTROL (2073) + GRAS_ALPHA_CONTROL: { 0x2 } +108ce354: 0000: 00002073 00000002 +t0 write GRAS_SC_WINDOW_SCISSOR_BR (209c) + GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +108ce35c: 0000: 0001209c 012b012b 00000000 +t0 write VFD_INDEX_OFFSET (2208) + VFD_INDEX_OFFSET: 0 + UNKNOWN_2209: 0 +108ce368: 0000: 00012208 00000000 00000000 +t0 write HLSQ_UPDATE_CONTROL (23db) + HLSQ_UPDATE_CONTROL: 0x3 +108ce374: 0000: 000023db 00000003 +t0 write HLSQ_CONTROL_0_REG (23c0) + HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } + HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +108ce37c: 0000: 000423c0 28000250 fcfc0100 fff3f3f0 fcfcfcfc 00fcfcfc +t0 write HLSQ_VS_CONTROL_REG (23c5) + HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } + HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } +108ce394: 0000: 000423c5 01000042 017e423e 007e4200 007e4200 007e4200 +t0 write SP_SP_CTRL_REG (22c0) + SP_SP_CTRL_REG: { 0x140010 } +108ce3ac: 0000: 000022c0 00140010 +t0 write SP_INSTR_CACHE_CTRL (22c1) + SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +108ce3b4: 0000: 000022c1 000005ff +t0 write SP_VS_LENGTH_REG (22e5) + SP_VS_LENGTH_REG: 1 +108ce3bc: 0000: 000022e5 00000001 +t0 write SP_VS_CTRL_REG0 (22c4) + SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } + SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } + SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } +108ce3c4: 0000: 000222c4 00200400 04000042 0000fc00 +t0 write SP_VS_OBJ_OFFSET_REG (22e0) + SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } + SP_VS_OBJ_START: 0x1073c000 +108ce3d4: 0000: 000122e0 00000000 1073c000 +t0 write SP_FS_LENGTH_REG (22ef) + SP_FS_LENGTH_REG: 1 +108ce3e0: 0000: 000022ef 00000001 +t0 write SP_FS_CTRL_REG0 (22e8) + SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } + SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 } +108ce3e8: 0000: 000122e8 00340400 8000003e +t0 write SP_FS_OBJ_OFFSET_REG (22ea) + SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + SP_FS_OBJ_START: 0x1073b000 +108ce3f4: 0000: 000122ea 7e420000 1073b000 +t0 write SP_HS_OBJ_OFFSET_REG (230d) + SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +108ce400: 0000: 0000230d 7e420000 +t0 write SP_DS_OBJ_OFFSET_REG (2334) + SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +108ce408: 0000: 00002334 7e420000 +t0 write SP_GS_OBJ_OFFSET_REG (235b) + SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +108ce410: 0000: 0000235b 7e420000 +t0 write GRAS_CNTL (2003) + GRAS_CNTL: { 0 } +108ce418: 0000: 00002003 00000000 +t0 write RB_RENDER_CONTROL2 (20a3) + RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } +108ce420: 0000: 000020a3 00000000 +t0 write RB_FS_OUTPUT_REG (2100) + RB_FS_OUTPUT_REG: { MRT = 0 } +108ce428: 0000: 00002100 00000000 +t0 write SP_FS_OUTPUT_REG (22f0) + SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +108ce430: 0000: 000022f0 0000fc00 +t0 write SP_FS_MRT[0].REG (22f1) + SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } + SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } +108ce438: 0000: 000722f1 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_ATTR (2140) + VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 } + VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } +108ce45c: 0000: 00012140 40001000 00000000 +t0 write VPC_VARYING_INTERP[0].MODE (2142) + VPC_VARYING_INTERP[0].MODE: 0 + VPC_VARYING_INTERP[0x1].MODE: 0 + VPC_VARYING_INTERP[0x2].MODE: 0 + VPC_VARYING_INTERP[0x3].MODE: 0 + VPC_VARYING_INTERP[0x4].MODE: 0 + VPC_VARYING_INTERP[0x5].MODE: 0 + VPC_VARYING_INTERP[0x6].MODE: 0 + VPC_VARYING_INTERP[0x7].MODE: 0 +108ce468: 0000: 00072142 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t0 write VPC_VARYING_PS_REPL[0].MODE (214a) + VPC_VARYING_PS_REPL[0].MODE: 0 + VPC_VARYING_PS_REPL[0x1].MODE: 0 + VPC_VARYING_PS_REPL[0x2].MODE: 0 + VPC_VARYING_PS_REPL[0x3].MODE: 0 + VPC_VARYING_PS_REPL[0x4].MODE: 0 + VPC_VARYING_PS_REPL[0x5].MODE: 0 + VPC_VARYING_PS_REPL[0x6].MODE: 0 + VPC_VARYING_PS_REPL[0x7].MODE: 0 +108ce48c: 0000: 0007214a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :0:0000:0000[03000000x_00000000x] end + :0:0001:0001[00000000x_00000000x] nop + :0:0002:0002[00000000x_00000000x] nop + :0:0003:0003[00000000x_00000000x] nop + :0:0004:0004[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): (cnt=0, max=0) + - used (merged): (cnt=0, max=0) + - input (half): (cnt=0, max=0) + - input (full): (cnt=0, max=0) + - const (half): (cnt=0, max=0) + - const (full): (cnt=0, max=0) + - output (half): (cnt=0, max=0) (estimated) + - output (full): (cnt=0, max=0) (estimated) + - shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full + - shaderdb: 0 (ss), 0 (sy) +108ce4b0: 0000: c0213000 00600000 00000000 00000000 03000000 00000000 00000000 00000000 +* +t3 opcode: CP_LOAD_STATE4 (30) (35 dwords) + { DST_OFF = 0 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = SB4_FS_SHADER | NUM_UNIT = 1 } + { STATE_TYPE = ST4_SHADER | EXT_SRC_ADDR = 0 } + :1:0000:0000[20244000x_00000000x] mov.f32f32 r0.x, c0.x + :1:0001:0001[20244001x_00000001x] mov.f32f32 r0.y, c0.y + :1:0002:0002[20244002x_00000002x] mov.f32f32 r0.z, c0.z + :1:0003:0003[20244003x_00000003x] mov.f32f32 r0.w, c0.w + :0:0004:0004[03000000x_00000000x] end + :0:0005:0005[00000000x_00000000x] nop + :0:0006:0006[00000000x_00000000x] nop + :0:0007:0007[00000000x_00000000x] nop + :0:0008:0008[00000000x_00000000x] nop + Register Stats: + - used (half): (cnt=0, max=0) + - used (full): 0-3 (cnt=4, max=3) + - used (merged): 0-7 (cnt=8, max=7) + - input (half): (cnt=0, max=0) + - input (full): (cnt=0, max=0) + - const (half): (cnt=0, max=0) + - const (full): 0-3 (cnt=4, max=3) + - output (half): (cnt=0, max=0) (estimated) + - output (full): 0-3 (cnt=4, max=3) (estimated) + - shaderdb: 9 instructions, 8 nops, 1 non-nops, (9 instlen), 0 half, 1 full + - shaderdb: 0 (ss), 0 (sy) +108ce53c: 0000: c0213000 00700000 00000000 00000000 20244000 00000001 20244001 00000002 +108ce55c: 0020: 20244002 00000003 20244003 00000000 03000000 00000000 00000000 00000000 +* +t0 write VFD_FETCH[0].INSTR_0 (220a) + VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } + VFD_FETCH[0].INSTR_1: 0x1074a000 + VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 } + VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +108ce5c8: 0000: 0003220a 0000060b 1074a000 00001000 00000001 +t0 write VFD_DECODE[0].INSTR (228a) + VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } +108ce5dc: 0000: 0000228a 2c0000df +t0 write VFD_CONTROL_0 (2200) + VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } + VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + VFD_CONTROL_2: 0 + VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + VFD_CONTROL_4: 0 +108ce5e4: 0000: 00042200 041a0004 fcfc0081 00000000 0000fc00 00000000 +t0 write UCHE_INVALIDATE0 (0e8a) + UCHE_INVALIDATE0: 0 + UCHE_INVALIDATE1: 0x12 +108ce5fc: 0000: 00010e8a 00000000 00000012 +t0 write RB_COPY_CONTROL (20fc) + RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0x64000 } + RB_COPY_DEST_BASE: { BASE = 0x10edc000 } + RB_COPY_DEST_PITCH: { PITCH = 1280 } + RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR } +108ce608: 0000: 000320fc 00064010 10edc000 00000028 0003c068 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x75 + :0,109,115,117 +108ce61c: 0000: 0000057f 00000075 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 2 } + draw[19] register values +!+ 00000075 CP_SCRATCH[0x7].REG: 0x75 + :0,109,115,117 + + 00000000 UCHE_INVALIDATE0: 0 + + 00000012 UCHE_INVALIDATE1: 0x12 + + 00080000 GRAS_CL_CLIP_CNTL: { 0x80000 } +!+ 00000000 GRAS_CNTL: { 0 } + + 43160000 GRAS_CL_VPORT_XOFFSET_0: 150.000000 + + 43160000 GRAS_CL_VPORT_XSCALE_0: 150.000000 + + 43160000 GRAS_CL_VPORT_YOFFSET_0: 150.000000 + + c3160000 GRAS_CL_VPORT_YSCALE_0: -150.000000 +!+ 00000000 GRAS_CL_VPORT_ZOFFSET_0: 0.000000 +!+ 3f800000 GRAS_CL_VPORT_ZSCALE_0: 1.000000 +!+ 00000002 GRAS_ALPHA_CONTROL: { 0x2 } +!+ 00000000 GRAS_SU_MODE_CONTROL: { LINEHALFWIDTH = 0.000000 } +!+ 00001808 GRAS_SC_CONTROL: { RENDER_MODE = RB_RESOLVE_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0x1 } + + 012b012b GRAS_SC_WINDOW_SCISSOR_BR: { X = 299 | Y = 299 } + + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } +!+ 0000002a RB_RENDER_CONTROL: { DISABLE_COLOR_PIPE | 0xa } +!+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 } +!+ 00064010 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0x64000 } +!+ 10edc000 RB_COPY_DEST_BASE: { BASE = 0x10edc000 } +!+ 00000028 RB_COPY_DEST_PITCH: { PITCH = 1280 } +!+ 0003c068 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WZYX | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR } +!+ 00000000 RB_FS_OUTPUT_REG: { MRT = 0 } +!+ 00000000 RB_DEPTH_CONTROL: { ZFUNC = FUNC_NEVER } + + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } + + 00000000 RB_STENCIL_CONTROL2: { 0 } +!+ ffff0000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } +!+ ffff0000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0xff | 0xff000000 } +!+ 40001000 VPC_ATTR: { TOTALATTR = 0 | THRDASSIGN = 1 | 0x40000000 } +!+ 00000000 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 0 | NUMNONPOSVSVAR = 0 } + + 00000000 VPC_VARYING_INTERP[0].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 + + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 + + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 +!+ 02000000 PC_PRIM_VTX_CNTL: { VAROUT = 0 | PROVOKING_VTX_LAST } +!+ 041a0004 VFD_CONTROL_0: { TOTALATTRTOVS = 4 | BYPASSATTROVS = 0 | STRMDECINSTRCNT = 1 | STRMFETCHINSTRCNT = 1 | 0xa0000 } + + fcfc0081 VFD_CONTROL_1: { MAXSTORAGE = 129 | REGID4VTX = r63.x | REGID4INST = r63.x } + + 00000000 VFD_CONTROL_2: 0 + + 0000fc00 VFD_CONTROL_3: { REGID_VTXCNT = r63.x | REGID_TESSX = r0.x | REGID_TESSY = r0.x } + + 00000000 VFD_CONTROL_4: 0 + + 00000000 VFD_INDEX_OFFSET: 0 + + 00000000 UNKNOWN_2209: 0 +!+ 0000060b VFD_FETCH[0].INSTR_0: { FETCHSIZE = 11 | BUFSTRIDE = 12 } +!+ 1074a000 VFD_FETCH[0].INSTR_1: 0x1074a000 +!+ 00001000 VFD_FETCH[0].INSTR_2: { SIZE = 0x1000 } + + 00000001 VFD_FETCH[0].INSTR_3: { STEPRATE = 1 } +!+ 2c0000df VFD_DECODE[0].INSTR: { WRITEMASK = 0xf | CONSTFILL | FORMAT = VFMT4_32_32_32_FLOAT | REGID = r0.x | SWAP = WZYX | SHIFTCNT = 12 | LASTCOMPVALID } + + 00140010 SP_SP_CTRL_REG: { 0x140010 } + + 000005ff SP_INSTR_CACHE_CTRL: { VS_BUFFER | FS_BUFFER | INSTR_BUFFER | 0x7f } +!+ 00200400 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 0 | THREADSIZE = TWO_QUADS | SUPERTHREADMODE } +!+ 04000042 SP_VS_CTRL_REG1: { CONSTLENGTH = 66 | INITIALOUTSTANDING = 4 } +!+ 0000fc00 SP_VS_PARAM_REG: { POSREGID = r0.x | PSIZEREGID = r63.x | TOTALVSOUTVAR = 0 } + + 00000000 SP_VS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 } +!+ 1073c000 SP_VS_OBJ_START: 0x1073c000 +!+ 00000001 SP_VS_LENGTH_REG: 1 +!+ 00340400 SP_FS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | INOUTREGOVERLAP = 1 | THREADSIZE = FOUR_QUADS | SUPERTHREADMODE } +!+ 8000003e SP_FS_CTRL_REG1: { CONSTLENGTH = 62 | 0x80000000 } + + 7e420000 SP_FS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } +!+ 1073b000 SP_FS_OBJ_START: 0x1073b000 + + 00000001 SP_FS_LENGTH_REG: 1 +!+ 0000fc00 SP_FS_OUTPUT_REG: { MRT = 0 | DEPTH_REGID = r63.x | SAMPLEMASK_REGID = r0.x } +!+ 00000000 SP_FS_MRT[0].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x1].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x2].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x3].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x4].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x5].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x6].REG: { REGID = r0.x | MRTFORMAT = 0 } +!+ 00000000 SP_FS_MRT[0x7].REG: { REGID = r0.x | MRTFORMAT = 0 } + + 7e420000 SP_HS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_DS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 7e420000 SP_GS_OBJ_OFFSET_REG: { CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 } + + 28000250 HLSQ_CONTROL_0_REG: { FSTHREADSIZE = FOUR_QUADS | FSSUPERTHREADENABLE | SPSHADERRESTART | CONSTMODE = 1 | SPCONSTFULLUPDATE } + + fcfc0100 HLSQ_CONTROL_1_REG: { VSTHREADSIZE = TWO_QUADS | VSSUPERTHREADENABLE | COORDREGID = r63.x | ZWCOORDREGID = r63.x } + + fff3f3f0 HLSQ_CONTROL_2_REG: { PRIMALLOCTHRESHOLD = 63 | FACEREGID = r63.x | SAMPLEID_REGID = r63.x | SAMPLEMASK_REGID = r63.x } +!+ fcfcfcfc HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r63.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } + + 00fcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | 0xfc0000 } +!+ 01000042 HLSQ_VS_CONTROL_REG: { CONSTLENGTH = 66 | CONSTOBJECTOFFSET = 0 | SHADEROBJOFFSET = 0 | INSTRLENGTH = 1 } + + 017e423e HLSQ_FS_CONTROL_REG: { CONSTLENGTH = 62 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 1 } + + 007e4200 HLSQ_HS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_DS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 007e4200 HLSQ_GS_CONTROL_REG: { CONSTLENGTH = 0 | CONSTOBJECTOFFSET = 66 | SHADEROBJOFFSET = 63 | INSTRLENGTH = 0 } + + 00000003 HLSQ_UPDATE_CONTROL: 0x3 +108ce624: 0000: c0023800 00000088 00000001 00000002 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x76 + :0,109,115,118 +108ce634: 0000: 0000057f 00000076 +t0 write RB_COPY_CONTROL (20fc) + RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 } + RB_COPY_DEST_BASE: { BASE = 0x10f3c000 } + RB_COPY_DEST_PITCH: { PITCH = 1280 } + RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR } +108ce63c: 0000: 000320fc 00000010 10f3c000 00000028 0003c168 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x77 + :0,109,115,119 +108ce650: 0000: 0000057f 00000077 +t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + { PRIM_TYPE = DI_PT_RECTLIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS } + { NUM_INSTANCES = 1 } + { NUM_INDICES = 2 } + draw[20] register values +!+ 00000077 CP_SCRATCH[0x7].REG: 0x77 + :0,109,115,119 +!+ 00000010 RB_COPY_CONTROL: { MSAA_RESOLVE = MSAA_ONE | MODE = RB_COPY_RESOLVE | FASTCLEAR = 0 | GMEM_BASE = 0 } +!+ 10f3c000 RB_COPY_DEST_BASE: { BASE = 0x10f3c000 } + + 00000028 RB_COPY_DEST_PITCH: { PITCH = 1280 } +!+ 0003c168 RB_COPY_DEST_INFO: { FORMAT = RB4_R8G8B8A8_UNORM | SWAP = WXYZ | DITHER_MODE = DITHER_DISABLE | COMPONENT_ENABLE = 0xf | ENDIAN = ENDIAN_NONE | TILE = TILE4_LINEAR } +108ce658: 0000: c0023800 00000088 00000001 00000002 +t0 write CP_SCRATCH[0x7].REG (057f) + CP_SCRATCH[0x7].REG: 0x78 + :0,109,115,120 +108ce668: 0000: 0000057f 00000078 +t0 write GRAS_SC_CONTROL (207b) + GRAS_SC_CONTROL: { RENDER_MODE = RB_RENDERING_PASS | MSAA_SAMPLES = 0 | MSAA_DISABLE | RASTER_MODE = 0 } +108ce670: 0000: 0000207b 00000800 +############################################################ +vertices: 0 +cmd: glxgears/23375: fence=1029605 +cmd: glxgears/23375: fence=1029606 +cmd: glxgears/23375: fence=1029607 +cmd: glxgears/23375: fence=1029608 +cmd: glxgears/23375: fence=1029609 +cmd: glxgears/23375: fence=1029610 +cmd: glxgears/23375: fence=1029611 +cmd: glxgears/23375: fence=1029612 +cmd: glxgears/23375: fence=1029613 +cmd: glxgears/23375: fence=1029614 +cmd: glxgears/23375: fence=1029615 +cmd: glxgears/23375: fence=1029616 +cmd: glxgears/23375: fence=1029617 +cmd: glxgears/23375: fence=1029618 +cmd: glxgears/23375: fence=1029619 +cmd: glxgears/23375: fence=1029620 +cmd: glxgears/23375: fence=1029621 +cmd: glxgears/23375: fence=1029622 +cmd: glxgears/23375: fence=1029623 +cmd: glxgears/23375: fence=1029624 +cmd: glxgears/23375: fence=1029625 +cmd: glxgears/23375: fence=1029626 +cmd: glxgears/23375: fence=1029627 +cmd: glxgears/23375: fence=1029628 +cmd: glxgears/23375: fence=1029629 +cmd: glxgears/23375: fence=1029630 +cmd: glxgears/23375: fence=1029631 +cmd: glxgears/23375: fence=1029632 +cmd: glxgears/23375: fence=1029633 +cmd: glxgears/23375: fence=1029634 +cmd: glxgears/23375: fence=1029635 +cmd: glxgears/23375: fence=1029636 +cmd: glxgears/23375: fence=1029637 +cmd: glxgears/23375: fence=1029638 +cmd: glxgears/23375: fence=1029639 +cmd: glxgears/23375: fence=1029640 +cmd: glxgears/23375: fence=1029641 +cmd: glxgears/23375: fence=1029642 +cmd: glxgears/23375: fence=1029643 +cmd: glxgears/23375: fence=1029644 +cmd: glxgears/23375: fence=1029645 +cmd: glxgears/23375: fence=1029646 +cmd: glxgears/23375: fence=1029647 +cmd: glxgears/23375: fence=1029648 +cmd: glxgears/23375: fence=1029649 +cmd: glxgears/23375: fence=1029650 +cmd: glxgears/23375: fence=1029651 +cmd: glxgears/23375: fence=1029652 +cmd: glxgears/23375: fence=1029653 +cmd: glxgears/23375: fence=1029654 +cmd: glxgears/23375: fence=1029655 +cmd: glxgears/23375: fence=1029656 +cmd: glxgears/23375: fence=1029657 +cmd: glxgears/23375: fence=1029658 +cmd: glxgears/23375: fence=1029659 +cmd: glxgears/23375: fence=1029660 +cmd: glxgears/23375: fence=1029661 +cmd: glxgears/23375: fence=1029662 +cmd: glxgears/23375: fence=1029663 +cmd: glxgears/23375: fence=1029664 +cmd: glxgears/23375: fence=1029665 +cmd: glxgears/23375: fence=1029666 +cmd: glxgears/23375: fence=1029667 +cmd: glxgears/23375: fence=1029668 +cmd: glxgears/23375: fence=1029669 +cmd: glxgears/23375: fence=1029670 +cmd: glxgears/23375: fence=1029671 +cmd: glxgears/23375: fence=1029672 +cmd: glxgears/23375: fence=1029673 +cmd: glxgears/23375: fence=1029674 +cmd: glxgears/23375: fence=1029675 +cmd: glxgears/23375: fence=1029676 +cmd: glxgears/23375: fence=1029677 +cmd: glxgears/23375: fence=1029678 +cmd: glxgears/23375: fence=1029679 +cmd: glxgears/23375: fence=1029680 +cmd: glxgears/23375: fence=1029681 +cmd: glxgears/23375: fence=1029682 +cmd: glxgears/23375: fence=1029683 +cmd: glxgears/23375: fence=1029684 +cmd: glxgears/23375: fence=1029685 +cmd: glxgears/23375: fence=1029686 +cmd: glxgears/23375: fence=1029687 +cmd: glxgears/23375: fence=1029688 +cmd: glxgears/23375: fence=1029689 +cmd: glxgears/23375: fence=1029690 +cmd: glxgears/23375: fence=1029691 +cmd: glxgears/23375: fence=1029692 +cmd: glxgears/23375: fence=1029693 +cmd: glxgears/23375: fence=1029694 +cmd: glxgears/23375: fence=1029695 +cmd: glxgears/23375: fence=1029696 +cmd: glxgears/23375: fence=1029697 +cmd: glxgears/23375: fence=1029698 +cmd: glxgears/23375: fence=1029699 +cmd: glxgears/23375: fence=1029700 +cmd: glxgears/23375: fence=1029701 +cmd: glxgears/23375: fence=1029702 +cmd: glxgears/23375: fence=1029703 +cmd: glxgears/23375: fence=1029704 +cmd: glxgears/23375: fence=1029705 +cmd: glxgears/23375: fence=1029706 +cmd: glxgears/23375: fence=1029707 +cmd: glxgears/23375: fence=1029708 +cmd: glxgears/23375: fence=1029709 +cmd: glxgears/23375: fence=1029710 +cmd: glxgears/23375: fence=1029711 +cmd: glxgears/23375: fence=1029712 +cmd: glxgears/23375: fence=1029713 +cmd: glxgears/23375: fence=1029714 +cmd: glxgears/23375: fence=1029715 +cmd: glxgears/23375: fence=1029716 +cmd: glxgears/23375: fence=1029717 +cmd: glxgears/23375: fence=1029718 +cmd: glxgears/23375: fence=1029719 +cmd: glxgears/23375: fence=1029720 +cmd: glxgears/23375: fence=1029721 +cmd: glxgears/23375: fence=1029722 +cmd: glxgears/23375: fence=1029723 +cmd: glxgears/23375: fence=1029724 +cmd: glxgears/23375: fence=1029725 +cmd: glxgears/23375: fence=1029726 +cmd: glxgears/23375: fence=1029727 +cmd: glxgears/23375: fence=1029728 +cmd: glxgears/23375: fence=1029729 +cmd: glxgears/23375: fence=1029730 +cmd: glxgears/23375: fence=1029731 +cmd: glxgears/23375: fence=1029732 +cmd: glxgears/23375: fence=1029733 +cmd: glxgears/23375: fence=1029734 +cmd: glxgears/23375: fence=1029735 +cmd: glxgears/23375: fence=1029736 +cmd: glxgears/23375: fence=1029737 +cmd: glxgears/23375: fence=1029738 +cmd: glxgears/23375: fence=1029739 +cmd: glxgears/23375: fence=1029740 +cmd: glxgears/23375: fence=1029741 +cmd: glxgears/23375: fence=1029742 +cmd: glxgears/23375: fence=1029743 +cmd: glxgears/23375: fence=1029744 +cmd: glxgears/23375: fence=1029745 +cmd: glxgears/23375: fence=1029746 +cmd: glxgears/23375: fence=1029747 +cmd: glxgears/23375: fence=1029748 +cmd: glxgears/23375: fence=1029749 +cmd: glxgears/23375: fence=1029750 +cmd: glxgears/23375: fence=1029751 +cmd: glxgears/23375: fence=1029752 +cmd: glxgears/23375: fence=1029753 +cmd: glxgears/23375: fence=1029754 +cmd: glxgears/23375: fence=1029755 +cmd: glxgears/23375: fence=1029756 +cmd: glxgears/23375: fence=1029757 +cmd: glxgears/23375: fence=1029758 +cmd: glxgears/23375: fence=1029759 +cmd: glxgears/23375: fence=1029760 +cmd: glxgears/23375: fence=1029761 +cmd: glxgears/23375: fence=1029762 +cmd: glxgears/23375: fence=1029763 +cmd: glxgears/23375: fence=1029764 +cmd: glxgears/23375: fence=1029765 +cmd: glxgears/23375: fence=1029766 +cmd: glxgears/23375: fence=1029767 +cmd: glxgears/23375: fence=1029768 +cmd: glxgears/23375: fence=1029769 +cmd: glxgears/23375: fence=1029770 +cmd: glxgears/23375: fence=1029771 +cmd: glxgears/23375: fence=1029772 +cmd: glxgears/23375: fence=1029773 +cmd: glxgears/23375: fence=1029774 +cmd: glxgears/23375: fence=1029775 +cmd: glxgears/23375: fence=1029776 +cmd: glxgears/23375: fence=1029777 +cmd: glxgears/23375: fence=1029778 +cmd: glxgears/23375: fence=1029779 +cmd: glxgears/23375: fence=1029780 +cmd: glxgears/23375: fence=1029781 +cmd: glxgears/23375: fence=1029782 +cmd: glxgears/23375: fence=1029783 +cmd: glxgears/23375: fence=1029784 +cmd: glxgears/23375: fence=1029785 +cmd: glxgears/23375: fence=1029786 +cmd: glxgears/23375: fence=1029787 +cmd: glxgears/23375: fence=1029788 +cmd: glxgears/23375: fence=1029789 +cmd: glxgears/23375: fence=1029790 +cmd: glxgears/23375: fence=1029791 +cmd: glxgears/23375: fence=1029792 +cmd: glxgears/23375: fence=1029793 +cmd: glxgears/23375: fence=1029794 +cmd: glxgears/23375: fence=1029795 +cmd: glxgears/23375: fence=1029796 +cmd: glxgears/23375: fence=1029797 +cmd: glxgears/23375: fence=1029798 +cmd: glxgears/23375: fence=1029799 +cmd: glxgears/23375: fence=1029800 +cmd: glxgears/23375: fence=1029801 +cmd: glxgears/23375: fence=1029802 +cmd: glxgears/23375: fence=1029803 +cmd: glxgears/23375: fence=1029804 +cmd: glxgears/23375: fence=1029805 +cmd: glxgears/23375: fence=1029806 +cmd: glxgears/23375: fence=1029807 +cmd: glxgears/23375: fence=1029808 +cmd: glxgears/23375: fence=1029809 +cmd: glxgears/23375: fence=1029810 +cmd: glxgears/23375: fence=1029811 +cmd: glxgears/23375: fence=1029812 +cmd: glxgears/23375: fence=1029813 +cmd: glxgears/23375: fence=1029814 +cmd: glxgears/23375: fence=1029815 +cmd: glxgears/23375: fence=1029816 +cmd: glxgears/23375: fence=1029817 +cmd: glxgears/23375: fence=1029818 +cmd: glxgears/23375: fence=1029819 +cmd: glxgears/23375: fence=1029820 +cmd: glxgears/23375: fence=1029821 +cmd: glxgears/23375: fence=1029822 +cmd: glxgears/23375: fence=1029823 +cmd: glxgears/23375: fence=1029824 +cmd: glxgears/23375: fence=1029825 +cmd: glxgears/23375: fence=1029826 +cmd: glxgears/23375: fence=1029827 +cmd: glxgears/23375: fence=1029828 +cmd: X/23360: fence=1029829 +cmd: glxgears/23375: fence=1029830 +cmd: glxgears/23375: fence=1029831 +cmd: X/23360: fence=1029832 +cmd: glxgears/23375: fence=1029833 +cmd: glxgears/23375: fence=1029834 +cmd: X/23360: fence=1029835 +cmd: glxgears/23375: fence=1029836 +cmd: glxgears/23375: fence=1029837 +cmd: X/23360: fence=1029838 +cmd: glxgears/23375: fence=1029839 +cmd: glxgears/23375: fence=1029840 +cmd: X/23360: fence=1029841 +cmd: glxgears/23375: fence=1029842 +cmd: glxgears/23375: fence=1029843 +cmd: X/23360: fence=1029844 +cmd: glxgears/23375: fence=1029845 +cmd: glxgears/23375: fence=1029846 +cmd: X/23360: fence=1029847 diff --git a/src/freedreno/.gitlab-ci/reference/shadow.log b/src/freedreno/.gitlab-ci/reference/shadow.log new file mode 100644 index 00000000000..47c7f2e2e5e --- /dev/null +++ b/src/freedreno/.gitlab-ci/reference/shadow.log @@ -0,0 +1,48 @@ +Analyzing Data... +Reading src/freedreno/.gitlab-ci/traces/shadow.rd.gz... +Parsing src/freedreno/.gitlab-ci/traces/shadow.rd.gz + +Blit: +----- + MRT[0x28b4000:0x0]: 256x144 FMT6_16_UNORM (MSAA_ONE) CLEARED + + + +NULL BATCH! + +Blit: +----- + MRT[0x20ae000:0x0]: 480x272 FMT6_16_UNORM (MSAA_ONE) CLEARED + +Batch: +------- + # of draws: 1 + mode: RM6_GMEM + bin size: 768x320 (35 bins) + DEPTHTEST DEPTHWRITE + MRT[0x4715000:0x0]: 3840x2160 FMT6_Z24_UNORM_S8_UINT (MSAA_ONE) CLEARED RESOLVED + + + +Blit: +----- + MRT[0x27d1000:0x0]: 256x144 FMT6_16_UNORM (MSAA_ONE) CLEARED + + + +Blit: +----- + MRT[0x28a0000:0x0]: 256x144 FMT6_16_UNORM (MSAA_ONE) CLEARED + +Batch: +------- + # of draws: 2 + mode: RM6_GMEM + bin size: 640x192 (18 bins) + DEPTHTEST DEPTHWRITE + MRT[0x28fc000:0x0]: 1920x1080 FMT6_Z24_UNORM_S8_UINT (MSAA_ONE) CLEARED RESOLVED + MRT[0x18ae000:0x0]: 1920x1080 FMT6_8_8_8_8_UNORM (MSAA_ONE) CLEARED RESOLVED + MRT[0x0:0x0]: 1920x1080 FMT6_8_8_8_8_UNORM (MSAA_ONE) CLEARED RESOLVED + SRC[0x4715000:0x46f3000]: 3840x2160 FMT6_Z24_UNORM_S8_UINT (MSAA_ONE) + + diff --git a/src/freedreno/.gitlab-ci/run-fdtools.sh b/src/freedreno/.gitlab-ci/run-fdtools.sh new file mode 100755 index 00000000000..261969a7510 --- /dev/null +++ b/src/freedreno/.gitlab-ci/run-fdtools.sh @@ -0,0 +1,16 @@ +#!/bin/bash + +set -e +set -x + +p=`dirname $0` + +# Run cffdump/crashdec tests: +$p/genoutput.sh +diff -r $p/reference $p/out + +# Also, while we are still using headergen2 for generating kernel +# headers, make sure that doesn't break: +headergen="_build/src/freedreno/rnn/headergen2" +$headergen adreno.xml +$headergen msm.xml diff --git a/src/freedreno/.gitlab-ci/traces/crash.devcore b/src/freedreno/.gitlab-ci/traces/crash.devcore new file mode 100644 index 00000000000..45f182042df --- /dev/null +++ b/src/freedreno/.gitlab-ci/traces/crash.devcore @@ -0,0 +1,5377 @@ +--- +kernel: 5.8.0-rc1-c630+ +module: msm +time: 1593887022.767858793 +comm: crashit +cmdline: ./crashit IB1 4 5 +revision: 630 (6.3.0.2) +rbbm-status: 0x00000000 +ringbuffer: + - id: 0 + iova: 0x0001000000001000 + last-fence: 1 + retired-fence: 0 + rptr: 40 + wptr: 56 + size: 32768 + data: !!ascii85 | + E6&"b!!!!P!!!!$+92BAzzzzzE97-$zE8LWrzE74di;nuc@!!!!#zzE8LWr!!!!"E'41(!!!91!!*'";nuc@!!!!#E'AdS5R7Jm!!!!I!!*'"E'AdS5RI4A!!!!Y!!*'"E(0g.!!!!9E(0g.!!!!:E5-o*z!!!!"!!!!-E'AdS5R7Jm!!!!Q!!*'"E'AdS5RI4A!!!!a!!*'"8-jnM!!!!"E(0g1J,fQP!!!!%!!*'"!!!!" +bos: + - iova: 0x0000000100000000 + size: 4096 + data: !!ascii85 | + E9.'#!!!!"E"IO"E"IO"E"IO"E"IO"hQ>-6E"IO"E"IO"E"IO"E"IO"E"IO" +registers: + - { offset: 0x000840, value: 0x00800005 } + - { offset: 0x000844, value: 0x00000000 } + - { offset: 0x000848, value: 0x00000000 } + - { offset: 0x00084c, value: 0x00000000 } + - { offset: 0x002094, value: 0x8100430e } + - { offset: 0x00c000, value: 0x200a0000 } + - { offset: 0x00c004, value: 0x00000000 } + - { offset: 0x00c008, value: 0x00000000 } + - { offset: 0x00c00c, value: 0x00000000 } + - { offset: 0x00c010, value: 0x00000000 } + - { offset: 0x00c014, value: 0x00000000 } + - { offset: 0x00c018, value: 0x00000000 } + - { offset: 0x00c01c, value: 0x00000000 } + - { offset: 0x00c030, value: 0x00000000 } + - { offset: 0x00c034, value: 0x00000000 } + - { offset: 0x00c038, value: 0x00000000 } + - { offset: 0x00c03c, value: 0x00000000 } + - { offset: 0x00c040, value: 0x00000000 } + - { offset: 0x00c044, value: 0x00000000 } + - { offset: 0x00c048, value: 0x00000000 } + - { offset: 0x00c04c, value: 0x00000000 } + - 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cluster-name: CLUSTER_SP_PS + - context: 0 + - { offset: 0x02cc00, value: 0x00000000 } + - { offset: 0x02cc04, value: 0x00000000 } + - { offset: 0x02cc08, value: 0x00000000 } + - { offset: 0x02cc0c, value: 0x00000000 } + - { offset: 0x02cc10, value: 0x00000000 } + - { offset: 0x02cc14, value: 0x00000000 } + - { offset: 0x02cc18, value: 0x00000000 } + - { offset: 0x02cc1c, value: 0x00000000 } + - { offset: 0x02cc24, value: 0x0000004c } + - { offset: 0x02ce00, value: 0xdeadbeef } + - { offset: 0x02ce04, value: 0xdeadbeef } + - { offset: 0x02ce08, value: 0xdeadbeef } + - context: 1 + - { offset: 0x02cc00, value: 0x00000000 } + - { offset: 0x02cc04, value: 0x00000000 } + - { offset: 0x02cc08, value: 0x00000000 } + - { offset: 0x02cc0c, value: 0x00000000 } + - { offset: 0x02cc10, value: 0x00000000 } + - { offset: 0x02cc14, value: 0x00000000 } + - { offset: 0x02cc18, value: 0x00000000 } + - { offset: 0x02cc1c, value: 0x00000000 } + - { offset: 0x02cc24, value: 0x0000004c } + - { offset: 0x02ce00, value: 0xdeadbeef } + - { offset: 0x02ce04, value: 0xdeadbeef } + - { offset: 0x02ce08, value: 0xdeadbeef } +debugbus: + - debugbus-block: A6XX_DBGBUS_CP + count: 512 + - debugbus-block: A6XX_DBGBUS_RBBM + count: 512 + - debugbus-block: A6XX_DBGBUS_HLSQ + count: 512 + - debugbus-block: A6XX_DBGBUS_UCHE + count: 512 + - debugbus-block: A6XX_DBGBUS_DPM + count: 512 + - debugbus-block: A6XX_DBGBUS_TESS + count: 512 + - debugbus-block: A6XX_DBGBUS_PC + count: 512 + - debugbus-block: A6XX_DBGBUS_VFDP + count: 512 + - debugbus-block: A6XX_DBGBUS_VPC + count: 512 + - debugbus-block: A6XX_DBGBUS_TSE + count: 512 + - debugbus-block: A6XX_DBGBUS_RAS + count: 512 + - debugbus-block: A6XX_DBGBUS_VSC + count: 512 + - debugbus-block: A6XX_DBGBUS_COM + count: 512 + - debugbus-block: A6XX_DBGBUS_LRZ + count: 512 + - debugbus-block: A6XX_DBGBUS_A2D + count: 512 + - debugbus-block: A6XX_DBGBUS_CCUFCHE + count: 512 + - debugbus-block: A6XX_DBGBUS_RBP + count: 512 + - debugbus-block: A6XX_DBGBUS_DCS + count: 512 + - debugbus-block: A6XX_DBGBUS_DBGC + count: 512 + - debugbus-block: A6XX_DBGBUS_GMU_GX + count: 512 + - debugbus-block: A6XX_DBGBUS_TPFCHE + count: 512 + - debugbus-block: A6XX_DBGBUS_GPC + count: 512 + - debugbus-block: A6XX_DBGBUS_LARC + count: 512 + - debugbus-block: A6XX_DBGBUS_HLSQ_SPTP + count: 512 + - debugbus-block: A6XX_DBGBUS_RB_0 + count: 512 + - debugbus-block: A6XX_DBGBUS_RB_1 + count: 512 + - debugbus-block: A6XX_DBGBUS_UCHE_WRAPPER + count: 512 + - debugbus-block: A6XX_DBGBUS_CCU_0 + count: 512 + - debugbus-block: A6XX_DBGBUS_CCU_1 + count: 512 + - debugbus-block: A6XX_DBGBUS_VFD_0 + count: 512 + - debugbus-block: A6XX_DBGBUS_VFD_1 + count: 512 + - debugbus-block: A6XX_DBGBUS_VFD_2 + count: 512 + - debugbus-block: A6XX_DBGBUS_VFD_3 + count: 512 + - debugbus-block: A6XX_DBGBUS_SP_0 + count: 512 + - debugbus-block: A6XX_DBGBUS_SP_1 + count: 512 + - debugbus-block: A6XX_DBGBUS_TPL1_0 + count: 512 + - debugbus-block: A6XX_DBGBUS_TPL1_1 + count: 512 + - debugbus-block: A6XX_DBGBUS_TPL1_2 + count: 512 + - debugbus-block: A6XX_DBGBUS_TPL1_3 + count: 512 + - debugbus-block: A6XX_DBGBUS_VBIF + count: 170 diff --git a/src/freedreno/.gitlab-ci/traces/es2gears-a320.rd.gz b/src/freedreno/.gitlab-ci/traces/es2gears-a320.rd.gz new file mode 100644 index 00000000000..3366030eafd Binary files /dev/null and b/src/freedreno/.gitlab-ci/traces/es2gears-a320.rd.gz differ diff --git a/src/freedreno/.gitlab-ci/traces/fd-clouds.rd.gz b/src/freedreno/.gitlab-ci/traces/fd-clouds.rd.gz new file mode 100644 index 00000000000..43ded22490f Binary files /dev/null and b/src/freedreno/.gitlab-ci/traces/fd-clouds.rd.gz differ diff --git a/src/freedreno/.gitlab-ci/traces/glxgears-a420.rd.gz b/src/freedreno/.gitlab-ci/traces/glxgears-a420.rd.gz new file mode 100644 index 00000000000..89166214802 Binary files /dev/null and b/src/freedreno/.gitlab-ci/traces/glxgears-a420.rd.gz differ diff --git a/src/freedreno/.gitlab-ci/traces/shadow.rd.gz b/src/freedreno/.gitlab-ci/traces/shadow.rd.gz new file mode 100644 index 00000000000..ecab5d2c349 Binary files /dev/null and b/src/freedreno/.gitlab-ci/traces/shadow.rd.gz differ