From: lkcl <lkcl@web>
Date: Mon, 3 Oct 2022 23:03:08 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~206
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ddd4f3717ea81c3ce63c9ec84d8d32a8515d7ffe;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index dc9324bb5..c97625660 100644
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -300,7 +300,15 @@ which has a workaround below (merge to single bit mask)
 
 **LD/ST Indexed**
 
-TODO
+Element-Striding is specifically enabled on RA and RB being
+scalar.  If VL=1 behaviour is also activated then this is potentially
+interfered with, except that, again, RT may be set as a vector destination.
+
+
+```
+    if svctx.ldstmode == elementstride:
+        EA = ireg[RA] + ireg[RB]*j   # register-strided
+```
 
 ## answers to 4, loops/uses