From: lkcl <lkcl@web>
Date: Thu, 23 Jan 2020 13:55:18 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~3765
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dde16db35f78a25014c389b4fa5b4822306a486b;p=libreriscv.git

---

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index 3dbc98069..25e2562da 100644
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -147,3 +147,4 @@ The reasons for doing a proper modularisation job are several-fold:
 
 Find appropriate tutorials for nmigen and yosys, as well as symbiyosys.
 
+* Although a verilog example this is very useful to do <https://symbiyosys.readthedocs.io/en/latest/quickstart.html#first-step-a-simple-bmc-example>