From: lkcl <lkcl@web>
Date: Sat, 14 Aug 2021 00:07:59 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~445
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dde8378e498b5de7c6b350fa62d8d1d4c078eb38;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 6529e9f8d..3f2896bc5 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -81,7 +81,7 @@ Note that the immediate (`SVi`) spans 7 bits (16 to 22)
 
 * `ms` - bit 23 - allows for setting of MVL.
 * `vs` - bit 24 - allows for setting of VL.
-* `vf` - bit 23 - sets "Vertical First Mode".
+* `vf` - bit 25 - sets "Vertical First Mode".
 
 Note that in immediate setting mode VL and MVL start from **one**
 i.e. that an immediate value of zero will result in VL/MVL being set to 1.