From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Thu, 27 Apr 2023 15:14:47 +0000 (+0000)
Subject: microwatt_tutorial: Fix formatting
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=dde9447363fbecf5871f246b429f2b558e6682cb;p=libreriscv.git

microwatt_tutorial: Fix formatting
---

diff --git a/HDL_workflow/microwatt_tutorial.mdwn b/HDL_workflow/microwatt_tutorial.mdwn
index e43f3d7e7..03cb94bcd 100644
--- a/HDL_workflow/microwatt_tutorial.mdwn
+++ b/HDL_workflow/microwatt_tutorial.mdwn
@@ -27,8 +27,9 @@ Make sure verilator binaries in $PATH:
 
 (GHDLSYNTH needs to be redefined because the Makefile has default `ghdl.so`,
 but somewhere else '.so' gets appended. You may see the following error if you
-don't redefine: `ERROR: Can't load module `./ghdl.so':
-/usr/local/bin/../share/yosys/plugins/**ghdl.so.so**`)
+don't redefine:
+`ERROR: Can't load module
+./ghdl.so':/usr/local/bin/../share/yosys/plugins/**ghdl.so.so**`)
 
 To run the Verilator simulation, set verilator as the target: