From: lkcl <lkcl@web>
Date: Sun, 7 Mar 2021 12:18:25 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~75
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ddea15b6fcccd928677f6da993b978dc267a9901;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index ec39b41b0..94daa39f7 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -159,7 +159,9 @@ Due to the need for exceptions to occur in the middle, the loop should *not* be
 
 * ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
 * power-gem5: TODO
-* TestIssuer: part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
+* TestIssuer:
+  - part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
+  - done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=97136d71397f420479d601dcb80f0df4abf73d22>
 * Microwatt: TODO
 
 Remember the following register files need to have for-loops, plus