From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 6 Sep 2020 18:43:40 +0000 (+0100)
Subject: add reset option to Register
X-Git-Tag: semi_working_ecp5~165
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ddebd445e7a2fa57570384607fae042508a43aa9;p=soc.git

add reset option to Register
---

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index 10b3fa06..30063726 100644
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -32,8 +32,9 @@ import operator
 
 
 class Register(Elaboratable):
-    def __init__(self, width, writethru=True, synced=True):
+    def __init__(self, width, writethru=True, synced=True, resetval=0):
         self.width = width
+        self.reset = resetval
         self.writethru = writethru
         self.synced = synced
         self._rdports = []
@@ -55,7 +56,7 @@ class Register(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        self.reg = reg = Signal(self.width, name="reg")
+        self.reg = reg = Signal(self.width, name="reg", reset=self.reset)
 
         if self.synced:
             domain = m.d.sync