From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 18 May 2018 13:25:23 +0000 (+0100)
Subject: note that VSETVL and MXAVECTORDEPTH have to be 15 for RV32E and 31 for RV32 or RV64
X-Git-Tag: convert-csv-opcode-to-binary~5370
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ddecee2047cfc33ae4e2834e9371d245dcbc0859;p=libreriscv.git

note that VSETVL and MXAVECTORDEPTH have to be 15 for RV32E and 31 for RV32 or RV64
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 13ab51006..8131a888d 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -608,6 +608,11 @@ XLEN bits.
 The second minor change is that when VSETVL is requested to be stored
 into x0, it is *ignored* silently.
 
+Unlike RVV, implementors *must* provide pseudo-parallelism (using sequential
+loops in hardware) if actual hardware-parallelism in the ALUs is not deployed.
+A hybrid is also permitted (as used in Broadcom's VideoCore-IV) however this
+must be *entirely* transparent to the ISA.
+
 ## Branch Instruction:
 
 Branch operations use standard RV opcodes that are reinterpreted to be