From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Jun 2020 12:02:07 +0000 (+0100)
Subject: enable byte-reverse in CompLDSTUnit test
X-Git-Tag: div_pipeline~298
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ddf4c748c9f6abb1b5b379d395eb07ef8af3e06a;p=soc.git

enable byte-reverse in CompLDSTUnit test
---

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 93b4e068..4bcfc7dd 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -543,10 +543,12 @@ def wait_for(sig, wait=True, test1st=False):
             break
 
 
-def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
+def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
+                                            byterev=True):
     print ("ST", src1, src2, src3, imm, imm_ok, update)
     yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
     yield dut.oper_i.data_len.eq(2) # half-word
+    yield dut.oper_i.byte_reverse.eq(byterev)
     yield dut.src1_i.eq(src1)
     yield dut.src2_i.eq(src2)
     yield dut.src3_i.eq(src3)
@@ -597,10 +599,12 @@ def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
     return addr
 
 
-def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False):
+def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
+                                            byterev=True):
     print ("LD", src1, src2, imm, imm_ok, update)
     yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
     yield dut.oper_i.data_len.eq(2) # half-word
+    yield dut.oper_i.byte_reverse.eq(byterev)
     yield dut.src1_i.eq(src1)
     yield dut.src2_i.eq(src2)
     yield dut.oper_i.zero_a.eq(zero_a)