From: Segher Boessenkool Date: Tue, 12 May 2015 13:55:46 +0000 (+0200) Subject: rs6000.md (*rotlsi3_internal4, [...]): Delete, revamp, transmogrify into ... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de065fbf8d13dd9a6c760f823c8a385bb660a8a8;p=gcc.git rs6000.md (*rotlsi3_internal4, [...]): Delete, revamp, transmogrify into ... * config/rs6000/rs6000.md (*rotlsi3_internal4, *rotlsi3_internal5, *rotlsi3_internal6, rlwinm, 5 unnamed define_insns, and 6 define_splits): Delete, revamp, transmogrify into ... (*rotlsi3_mask, *rotlsi3_mask_dot, *rotlsi3_mask_dot2, *ashlsi3_imm_mask, *ashlsi3_imm_mask_dot, *ashlsi3_imm_mask_dot2, *lshrsi3_imm_mask, *lshrsi3_imm_mask_dot, *lshrsi3_imm_mask_dot2): New. From-SVN: r223072 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7a07d50ff96..816f3ab2760 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2015-05-12 Segher Boessenkool + + * config/rs6000/rs6000.md (*rotlsi3_internal4, *rotlsi3_internal5, + *rotlsi3_internal6, rlwinm, 5 unnamed define_insns, and 6 + define_splits): Delete, revamp, transmogrify into ... + (*rotlsi3_mask, *rotlsi3_mask_dot, *rotlsi3_mask_dot2, + *ashlsi3_imm_mask, *ashlsi3_imm_mask_dot, *ashlsi3_imm_mask_dot2, + *lshrsi3_imm_mask, *lshrsi3_imm_mask_dot, *lshrsi3_imm_mask_dot2): + New. + 2015-05-12 Segher Boessenkool * config/rs6000/rs6000.md (rs6000_adjust_atomic_subword): Use diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d3b1a7a0df4..1fcd69e3d9c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3745,7 +3745,7 @@ (set_attr "length" "4,8")]) -(define_insn "*rotlsi3_internal4" +(define_insn "*rotlsi3_mask" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "rn")) @@ -3755,75 +3755,62 @@ [(set_attr "type" "shift") (set_attr "maybe_var_shift" "yes")]) -(define_insn "*rotlsi3_internal5" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) - (match_operand:SI 3 "mask_operand" "n,n")) - (const_int 0))) - (clobber (match_scratch:SI 4 "=r,r"))] - "" +(define_insn_and_split "*rotlsi3_mask_dot" + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + (compare:CC + (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) + (match_operand:SI 3 "mask_operand" "n,n")) + (const_int 0))) + (clobber (match_scratch:SI 0 "=r,r"))] + "rs6000_gen_cell_microcode + && (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff)" "@ - rlw%I2nm. %4,%1,%h2,%m3,%M3 + rlw%I2nm. %0,%1,%h2,%m3,%M3 #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)" + [(set (match_dup 0) + (and:SI (rotate:SI (match_dup 1) + (match_dup 2)) + (match_dup 3))) + (set (match_dup 4) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 4 ""))] - "reload_completed" - [(set (match_dup 4) - (and:SI (rotate:SI (match_dup 1) - (match_dup 2)) - (match_dup 3))) - (set (match_dup 0) - (compare:CC (match_dup 4) - (const_int 0)))] - "") - -(define_insn "*rotlsi3_internal6" +(define_insn_and_split "*rotlsi3_mask_dot2" [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") - (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) - (match_operand:SI 3 "mask_operand" "n,n")) - (const_int 0))) + (compare:CC + (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) + (match_operand:SI 3 "mask_operand" "n,n")) + (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "" + (and:SI (rotate:SI (match_dup 1) + (match_dup 2)) + (match_dup 3)))] + "rs6000_gen_cell_microcode + && (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff)" "@ rlw%I2nm. %0,%1,%h2,%m3,%M3 #" - [(set_attr "type" "shift") - (set_attr "maybe_var_shift" "yes") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "reload_completed" + "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)" [(set (match_dup 0) - (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) + (and:SI (rotate:SI (match_dup 1) + (match_dup 2)) + (match_dup 3))) (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "shift") + (set_attr "maybe_var_shift" "yes") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) (define_insn "ashl3" @@ -3894,7 +3881,7 @@ (set_attr "length" "4,8")]) -(define_insn "rlwinm" +(define_insn "*ashlsi3_imm_mask" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) @@ -3903,40 +3890,34 @@ "rlwinm %0,%1,%h2,%m3,%M3" [(set_attr "type" "shift")]) -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") +(define_insn_and_split "*ashlsi3_imm_mask_dot" + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "i,i")) (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) - (clobber (match_scratch:SI 4 "=r,r"))] - "includes_lshift_p (operands[2], operands[3])" + (clobber (match_scratch:SI 0 "=r,r"))] + "rs6000_gen_cell_microcode + && (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff) + && includes_lshift_p (operands[2], operands[3])" "@ - rlwinm. %4,%1,%h2,%m3,%M3 + rlwinm. %0,%1,%h2,%m3,%M3 #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)" + [(set (match_dup 0) + (and:SI (ashift:SI (match_dup 1) + (match_dup 2)) + (match_dup 3))) + (set (match_dup 4) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC - (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 4 ""))] - "includes_lshift_p (operands[2], operands[3]) && reload_completed" - [(set (match_dup 4) - (and:SI (ashift:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) - (set (match_dup 0) - (compare:CC (match_dup 4) - (const_int 0)))] - "") - -(define_insn "" +(define_insn_and_split "*ashlsi3_imm_mask_dot2" [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") @@ -3944,31 +3925,27 @@ (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "includes_lshift_p (operands[2], operands[3])" + (and:SI (ashift:SI (match_dup 1) + (match_dup 2)) + (match_dup 3)))] + "rs6000_gen_cell_microcode + && (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff) + && includes_lshift_p (operands[2], operands[3])" "@ rlwinm. %0,%1,%h2,%m3,%M3 #" - [(set_attr "type" "shift") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") - (compare:CC - (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "includes_lshift_p (operands[2], operands[3]) && reload_completed" + "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)" [(set (match_dup 0) - (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) + (and:SI (ashift:SI (match_dup 1) + (match_dup 2)) + (match_dup 3))) (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "shift") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) (define_insn "lshr3" @@ -4039,7 +4016,7 @@ (set_attr "length" "4,8")]) -(define_insn "" +(define_insn "*lshrsi3_imm_mask" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) @@ -4048,40 +4025,34 @@ "rlwinm %0,%1,%s2,%m3,%M3" [(set_attr "type" "shift")]) -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") +(define_insn_and_split "*lshrsi3_imm_mask_dot" + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "i,i")) (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) - (clobber (match_scratch:SI 4 "=r,r"))] - "includes_rshift_p (operands[2], operands[3])" + (clobber (match_scratch:SI 0 "=r,r"))] + "rs6000_gen_cell_microcode + && (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff) + && includes_rshift_p (operands[2], operands[3])" "@ - rlwinm. %4,%1,%s2,%m3,%M3 + rlwinm. %0,%1,%s2,%m3,%M3 #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)" + [(set (match_dup 0) + (and:SI (lshiftrt:SI (match_dup 1) + (match_dup 2)) + (match_dup 3))) + (set (match_dup 4) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC - (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 4 ""))] - "includes_rshift_p (operands[2], operands[3]) && reload_completed" - [(set (match_dup 4) - (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) - (set (match_dup 0) - (compare:CC (match_dup 4) - (const_int 0)))] - "") - -(define_insn "" +(define_insn_and_split "*lshrsi3_imm_mask_dot2" [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") @@ -4089,31 +4060,27 @@ (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "includes_rshift_p (operands[2], operands[3])" + (and:SI (lshiftrt:SI (match_dup 1) + (match_dup 2)) + (match_dup 3)))] + "rs6000_gen_cell_microcode + && (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff) + && includes_rshift_p (operands[2], operands[3])" "@ rlwinm. %0,%1,%s2,%m3,%M3 #" - [(set_attr "type" "shift") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") - (compare:CC - (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (match_operand:SI 3 "mask_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "includes_rshift_p (operands[2], operands[3]) && reload_completed" + "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)" [(set (match_dup 0) - (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) + (and:SI (lshiftrt:SI (match_dup 1) + (match_dup 2)) + (match_dup 3))) (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "shift") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) (define_expand "ashr3"