From: lkcl <lkcl@web>
Date: Mon, 21 Dec 2020 03:45:39 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1111
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de07786df4aedbafaf742ab21ec04d0bbe0e55cd;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 3bbdfabfc..8c5fafd79 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -593,7 +593,9 @@ but select different *bits* of the same CRs
 
 `offs` is defined as CR48 (6x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below).  Arithmetic Rc=1 operations start from CR16 (TBD); FP Rc=1 from CR32 (TBD).
 
-# Twin Predication
+# Appendix
+
+## Twin Predication
 
 This is a novel concept that allows predication to be applied to a single
 source and a single dest register.  The following types of traditional
@@ -624,8 +626,6 @@ Additional unusual capabilities of Twin Predication include a back-to-back
 version of VCOMPRESS-VEXPAND which is effectively the ability to do an
 ordered multiple VINSERT.
 
-# Appendix
-
 ## CR Operations
 
 CRs are slightly more involved than INT or FP registers due to the