From: lkcl <lkcl@web>
Date: Sat, 2 Apr 2022 11:25:47 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2934
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de15afc0ed5dbb6d2fd0637eed894bc5e9ff0ecb;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 3682e75d4..5259668ac 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -450,6 +450,23 @@ This contrived construct is avoided by the behavioural inversion bits.
 
 # Pseudocode and examples
 
+For comparative purposes this is a copy of the v3.0B bc pseudocode,
+noting that M and AA have not been added to the SVP64 versions
+for simplicity of illustration.  ctr_ok does not appear in the SVP64
+versions because of the way that CTRtest Mode interacts.
+
+```
+if (mode_is_64bit) then M <- 0
+else M <- 32
+if ¬BO[2] then CTR <- CTR - 1
+ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
+cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
+if ctr_ok & cond_ok then
+  if AA then NIA <-iea EXTS(BD || 0b00)
+  else       NIA <-iea CIA + EXTS(BD || 0b00)
+if LK then LR  <-iea  CIA + 4
+```
+
 Pseudocode for Horizontal-First Mode:
 
 ```