From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sat, 17 Dec 2016 04:01:22 +0000 (+0800)
Subject: greenpak4: Updated GP_DCMP cell model
X-Git-Tag: yosys-0.8~553^2^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de1d81511af7a5ca362c334635190609c45e998b;p=yosys.git

greenpak4: Updated GP_DCMP cell model
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 0f1eaf8fb..27c5ff054 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -136,8 +136,26 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 
 endmodule
 
-module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg OUTP, output reg OUTN);
-	//TODO finish implementing
+module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
+	parameter PWRDN_SYNC = 1'b0;
+	parameter CLK_EDGE = "RISING";
+	parameter GREATER_OR_EQUAL = 1'b0;
+
+	//TODO implement power-down mode
+
+	initial GREATER = 0;
+	initial EQUAL = 0;
+
+	wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
+	always @(posedge clk_minv) begin
+		if(GREATER_OR_EQUAL)
+			GREATER <= (INP >= INN);
+		else
+			GREATER <= (INP > INN);
+
+		EQUAL <= (INP == INN);
+	end
+
 endmodule
 
 module GP_DCMPREF(output reg[7:0]OUT);