From: Luke Kenneth Casson Leighton Date: Thu, 15 Nov 2018 23:45:31 +0000 (+0000) Subject: add in predication remapping into src, dest and branch target X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de2bccd226f137ca27b65912c3f519bc2294dda1;p=riscv-isa-sim.git add in predication remapping into src, dest and branch target --- diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index 64f9fe7..4389fd6 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -51,11 +51,15 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc) // need to know if register is used as float or int. // REGS_PATTERN is generated by id_regs.py (per opcode) unsigned int floatintmap = REGS_PATTERN; + reg_t dest_preg = 0; reg_t dest_pred = ~0x0; + bool dest_pset = false; int *dest_offs = &(p->get_state()->sv().destoffs); bool zeroing = false; #ifdef INSN_CATEGORY_TWINPREDICATION + reg_t src_preg = 0; reg_t src_pred = ~0x0; + bool src_pset = false; int *src_offs = &(p->get_state()->sv().srcoffs); bool zeroingsrc = false; #endif @@ -115,18 +119,20 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc) #endif #ifdef INSN_CATEGORY_TWINPREDICATION #ifdef INSN_TYPE_C_STACK_LD - src_pred = insn.predicate(sp.reg, SRC_PREDINT, zeroingsrc); + src_preg = sp.reg; #else - src_pred = insn.predicate(s_insn.SRC_REG(), SRC_PREDINT, zeroingsrc); + src_preg = s_insn.SRC_REG(); #endif + src_pred = insn.predicate(src_preg, SRC_PREDINT, zeroingsrc); #endif #ifdef DEST_PREDINT #ifdef INSN_TYPE_C_STACK_ST - dest_pred = insn.predicate(sp.reg, DEST_PREDINT, zeroing); + dest_preg = sp.reg; #else // use the ORIGINAL, i.e. NON-REDIRECTED, register here - dest_pred = insn.predicate(s_insn.DEST_REG(), DEST_PREDINT, zeroing); + dest_preg = s_insn.DEST_REG(); #endif + dest_pred = insn.predicate(dest_preg, DEST_PREDINT, zeroing); #endif } #if 0 // useful test at one point... @@ -167,7 +173,8 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc) #endif if (!zeroingsrc) { - while ((src_pred & (1<<*src_offs)) == 0) { + while ((src_pset = (src_pred & (1<= vlen) { break; @@ -176,7 +183,8 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc) } if (!zeroing) { - while ((dest_pred & (1<<*dest_offs)) == 0) { + while ((dest_pset = (dest_pred & (1<= vlen) { break; diff --git a/riscv/sv.cc b/riscv/sv.cc index 8f24631..69a4637 100644 --- a/riscv/sv.cc +++ b/riscv/sv.cc @@ -279,7 +279,6 @@ uint64_t sv_insn_t::_rvc_spoffs_imm(uint64_t elwidth, uint64_t offs) // for use in predicated branches. sets bit N if val=true; clears bit N if false uint64_t sv_insn_t::rd_bitset(reg_t reg, int bit, bool set) { - reg_spec_t rs = {reg, &bit}; uint64_t val = STATE.XPR[reg]; if (set) { val |= (1UL<s.READ_REG(rs), prs1); } + if (target_reg) { + offs = p->s.pred_remap(*target_reg, offs); + } if ((1<