From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 20 Feb 2020 17:09:58 +0000 (+0000)
Subject: add description of simplev to openpower eval page
X-Git-Tag: convert-csv-opcode-to-binary~3330
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de33c399fe449d87b351ac1768a690d82d14a196;p=libreriscv.git

add description of simplev to openpower eval page
---

diff --git a/openpower.mdwn b/openpower.mdwn
index 1b85356fc..f3a685154 100644
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -19,6 +19,19 @@ Summary
 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
 * needs escape sequencing (ISAMUX/NS)
 
+# SimpleV
+
+see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
+SimpleV: a "hardware for-loop" which involves type-casting (both) the
+register files to "a sequence of elements".  The **one** instruction
+(an unmodified **scalar** instruction) is interpreted as a *hardware
+for-loop* that issues **multiple** internal instructions with
+sequentially-incrementing register numbers.
+
+Thus it is completely unnecessary to add any vector opcodes - at all -
+saving hugely on both hardware and compiler development time when
+the concept is dropped on top of a pre-existing ISA.
+
 # atomics
 
 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.