From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 29 Mar 2023 16:28:03 +0000 (+0100)
Subject: move regfile section
X-Git-Tag: opf_rfc_ls012_v1~244
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de51256e24aaf3ff1ba8ba814974bf438c10eca7;p=libreriscv.git

move regfile section
---

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 34a382f4a..aaa6eb73a 100644
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -122,6 +122,29 @@ operations under its influence into `nops` (regardless of the prefix)
  acts as if SV had not been applied at all to the instruction  (an
  "identity transformation").
 
+## Register Naming and size
+
+As expanded on below SV Registers are simply the INT, FP and CR
+register files extended linearly to larger sizes; SV Vectorisation
+iterates sequentially through these registers (LSB0 sequential ordering
+from 0 to VL-1).
+
+Where the integer regfile in standard scalar Power ISA v3.0B/v3.1B is
+r0 to r31, SV extends this as r0 to r127.  Likewise FP registers are
+extended to 128 (fp0 to fp127), and CR Fields are extended to 128 entries,
+CR0 thru CR127.
+
+The names of the registers therefore reflects a simple linear extension
+of the Power ISA v3.0B / v3.1B register naming, and in hardware this
+would be reflected by a linear increase in the size of the underlying
+SRAM used for the regfiles.
+
+Note: when an EXTRA field (defined below) is zero, SV is deliberately
+designed so that the register fields are identical to as if SV was not in
+effect i.e. under these circumstances (EXTRA=0) the register field names
+RA, RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.
+This is part of `scalar identity behaviour` described above.
+
 ## Register files, elements, and Element-width Overrides
 
 In the Upper Compliancy Levels the size of the GPR and FPR Register
@@ -208,29 +231,6 @@ write-enable line.  It is up to the Hardware Architect to then amortise
 as simultaneous non-overlapping Register File writes, to achieve High
 Performance designs.
 
-## Register Naming and size
-
-As previously mentioned SV Registers are simply the INT, FP and CR
-register files extended linearly to larger sizes; SV Vectorisation
-iterates sequentially through these registers (LSB0 sequential ordering
-from 0 to VL-1).
-
-Where the integer regfile in standard scalar Power ISA v3.0B/v3.1B is
-r0 to r31, SV extends this as r0 to r127.  Likewise FP registers are
-extended to 128 (fp0 to fp127), and CR Fields are extended to 128 entries,
-CR0 thru CR127.
-
-The names of the registers therefore reflects a simple linear extension
-of the Power ISA v3.0B / v3.1B register naming, and in hardware this
-would be reflected by a linear increase in the size of the underlying
-SRAM used for the regfiles.
-
-Note: when an EXTRA field (defined below) is zero, SV is deliberately
-designed so that the register fields are identical to as if SV was not in
-effect i.e. under these circumstances (EXTRA=0) the register field names
-RA, RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.
-This is part of `scalar identity behaviour` described above.
-
 ## Future expansion.
 
 With the way that EXTRA fields are defined and applied to register fields,