From: lkcl Date: Wed, 5 Oct 2022 16:21:03 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~152 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=de5c38189725c6fd5f1f95fb1a3f6fcc1456a46b;p=libreriscv.git --- diff --git a/nlnet_2022_ongoing/discussion.mdwn b/nlnet_2022_ongoing/discussion.mdwn index aa9c3f850..7e567129f 100644 --- a/nlnet_2022_ongoing/discussion.mdwn +++ b/nlnet_2022_ongoing/discussion.mdwn @@ -18,7 +18,8 @@ group backed by Intel!) * 3-5 months: Completion of an In-Order Single-Issue core implementing SVP64 * 3-4 months: Addition of the IEEE754 FPU to the Core * 3-4 months: Addition of other ALUs and pipelines -* 4-5 months: Addition of SMP (multi-core) support (lots of research here) +* 4-5 months: Addition of SMP (multi-core) support (lots of research here, + need help from IBM / Microwatt, the SMP Memory Model is conprehensive) * 3-4 months: Running under Verilator and on FPGAs (big ones) * 4-5 months: Continued documentation, attendance of Conferences online * 4-5 months: Begin investigating Multi-Issue Out-of-Order @@ -30,6 +31,10 @@ budget @ EUR 3,000/mo is within target (just). may need adjusting or some tasks removing, to fit. we cannot risk committing to tasks at too low a rate to be able to attract interest and committment. +Again however I do not have a problem with reducing the scope of this one +to only EUR 50,000 to cover some of the less ambitious tasks, and the +necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) first. + ** What would be the concrete (high level) outcome of that project - where would the grant get us? Would there be a new test chip made